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A 130 nm Generation Logic Technology Featuring 70nm Transistors,
Dual Vt Transistors and 6 layers of Cu Interconnects
S. Tyagi, M. Alav?,, R. Bigwood, T. Bramblett,J. Brandenburg,W. Chen,B. Crew, M. Hussein,P. Jacob, C. Kenyon, C. Lo,
B. Mcintyre, Z. Ma, P. Moon, P. Nguyen, L. Rumaner,R. Schweinfurth,S. Sivakumar,M. Stettler*, S.Thompson,B. Tufts, J. Xu,
S. Yang and M. Bohr
PortlandTechnologyDevelopment,* TCAD,’ QRE, Intel Corporation,Hillsboro, OR 97124,USA.
Abstract
A leadingedge130mn generationlogic technologywith 6
layersof dual damasceneCu interconnectsis reported. Dual Vt
transistors are employed with 1.5 nm thick gate oxide and
operating at 1.3 V. High Vt transistorshave drive currentsof
1.03 mA/pm and 0.5 mA/um for NMOS and PMOS
respectively, while low Vt transistors have currents of 1.17
mA/pm and 0.6 mA/um respectively.Technology designrules
allow a 6-T SRAM cell with an area of 2.45 pm’, while array
specific design rule give the densestSRAM reported to date,
the 6-T cell has an areaof only 2.09 urn*. Excellent yield and
performanceis demonstratedon a 18 Mbit CMOS SRAM.
Introduction
isolation is 450 nm deep to provide good intra- and inter-well
isolation. Fig. 2 shows that isolation is robust for N+ to P+
spacingbelow 300 mn.
Fig.1 TEM Cros*section of a 70 nm NMOS transistor.
Fig. 2 Percentagepassingelectrical isolation criteria for N+/NW and
High performance microprocessors require faster P+iPW spacing.
transistorsoperatingat lower voltagesto maintain the historic
speed trend at acceptable active power. In this paper we
describea 130nm generationtechnology operatingat 1.3V for
high speedand low power operation.Transistor leakagein off
stateis anotherconcern,which constrainschip performanceas
it affects standby power. Dual threshold voltages are offered
for both NMOS and PMOS transistors to improve product
performanceat acceptablestandby leakage. Increasingly the
circuit speed is also being affected by performance of
-2.50-200-150-100-50 0 50 100 150 200 250
interconnects.The technology uses6 layers of dual damascene
Spacing(nm)
Cu with fluorinated SiO, for high performanceinterconnects.
High quality gate oxide is then grown, the physical
thickness of the oxide is 1.5 nm. Complementary-doped
Process flow and front end technology features
The technology featuresare summarizedin Table I below poly-silicon is used to form surface-channel NMOS and
giving layer pitches and thicknesses.Fig. 1 shows a cross- PMOS devices. DUV lithography is used to pattern the polysilicon gate layer down to gate dimension of 70 nm as shown
sectionalTEM for a transistorwith 70nm gate length.
in Fig. 1. Shallow source-drainextensionsregions are formed
TABLE I
LAYER PITCH,THICKNESSAND ASPECTRATIO
with arsenic for NMOS and boron for PMOS. Boron and
Layer
Pitch (nm)
Thick (nm)
Aspect Ratio
arsenic halos are used in both cases for improved short
Isolation
364
450
channel
characteristics. Side-wall spacers are formed with
Poly-silicon
336
160
CVD S&N, deposition, followed by etch-back. CoSi, is
Metal 1
350
280
I.6
formed on poly-silicon and source-drain regions to provide
Metal2, 3
448
360
1.6
Metal4
756
570
1.5
low contact resistance.
Metal5
Metal6
1120
1204
900
1200
I.6
2.0
Transistors
The processflow startswith P-/P+ epitaxial silicon wafers,
followed by the formation of shallow trench isolation. N-wells
and P-wells are formed with deep phosphorousand shallow
arsenic implants, and boron implants respectively. The trench
To improve product performance at acceptablestandby
leakage,NMOS and PMOS deviceswith high and low
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threshold voltages are made by selectively adjusting well
doses.The transistor characteristicsare shown in Figs. 3 and 4
for high and low threshold devices respectively. Saturation
drive currents for high Vt devicesat Ioff value of 10 “A/urn,
are 1.03 mA/um for NMOS and 0.5 mA/um for PMOS. For
low Vt devicesthe Ioff is 100 “A/urn, and the currentsare 1.17
PMOS
1 NMOS
100 mV/V for high Vt devices and 110 mVN for low Vt
device.For the PMOS devicethe measuredDIBL is 100mV/V
1x02
1.Ero3
l.ErO4
%p05
2 l.l%6
x 1E-07
l.E-08
1.~09
1.E10
I
-0.8
Ei
2 0.6
-1.3
go.4
0.0
VGS(v)
1.3
for high Vt device and 130mVN for low Vt device.
Fig. 6 Low Vt subthresholdcharacteristics.
‘The NMOS and PMOS drive current vs. off current
characteristicsare shown in Fig. 7 for both the high and low Vt
devices.These are the best Ion-Ioff characteristicsreported to
mA/um for NMOS and 0.6 mA/um for PMOS.
- 1X-07
-0.8
Ei
h 0.6
5
z 1.BO8
s
Eo.4
date.
Fig. 7 Drive current vs. off current for NMOS and PMOS. Unfilled
Fig. 3 High Vt MOSFET Id-Vd characteristics.
Fig. 4 Low Vt MOSFET Id-Vd characteristics.
symbols are high Vt devices,while filled symbols are low Vt devices.
The subthresholdslopes for these devices are shown in
1.E-02
Table II comparesthe transistorcharacteristicsin this work
to thosereportedearlier by our group [ 11.
TABLE II
l.E-03
l.EO4
- lx-05
Ei
2 l.Ex6
4 lx-07
l&08
1.Ero9
Parameter
1.5
3
1.04
0.46
0.0
VGS (v)
Fig. 5 and 6 and are lessthan 95 mV/decade.
This Work
1.3
70
1.5
10
1.02
0.5
100
I.17
0.6
The thin 1.5 nm oxide enablesdeviceswith well controlled
short channelcharacteristicsdown to 70 run gatelengths.
Fig. 5 High Vt subthresholdcharacteristics.
The DIBL for the 70 nm NMOS device is measuredto be
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1.510
-1.3
SUMMARYOF TRANSISTORCHARACTERISTICS
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The threshold voltage roll-off characteristicsare shown in
Fig. 8 and 9 for high and low Vt devicesrespectively. Optimal
Halo and well engineering gives Vt roll off of less than 100
mV for the target 70 nm devices.This is achievedby using the
halo to boost the averagewell doping for shorter gate length
devices.This reducesthe magnitudeof Vt roll off due to short
channeleffects.
0.60 ,
I
II710
1.E!m
Ioff (A/Clm)
1.E;O8
1.I%07
Fig. 10 Propagation delay per stage of unloaded ring oscillator with
fan out =l and WpAVn ratio of 1.5.
50
60
70
80
GateLength (nm)
90
100
90
100
Fig. 8 Hi Vt threshold voltagesvs. gate length.
0.60
z 0.40
=
Vd, 0.05v
NMOS
Interconnects
Chip performance is increasingly limited by the RC
delay of the interconnect as the transistor delay progressively
decreases while the narrower lines and space actually
increase the delay associated with interconnects [2]. Using
copper interconnects helps reduce this effect. This process
technology uses dual damascene copper to reduce the
resistancesof the interconnects. Fluorinated SiO, (FSG) is
used as inter-level dielectric (ILD) to reduce the dielectric
constant, the dielectric constant k is measuredto be 3.6. Fig.
11 is a cross-sectionSEM image showing the dual damascene
interconnects.
-0.60
50
60
70
80
GateLength (nm)
Fig. 9 Low Vt threshold voltagesvs. gate length.
Junction capacitanceplays an important role in limiting
chip performance and increasing active power. Special
emphasis was placed on minimizing junction capacitance
values.Low N+ and P+ junction areacapacitancevaluesof 0.6
fFiprn2 at 0 V bias were achievedwhile maintaining the intraand inter-well isolation.
Ring oscillator propagationdelays are used to benchmark
the performance of the transistors in a circuit configuration.
Fig.10 shows the propagation delay per stage of an unloaded
ring oscillator as function of NMOS off current, the PMOS off
current is lessthan 10 nAIpm. The ring oscillator has a fanout
of 1 and a W,,/W,, ratio of 1.5, the V,, is 1.3 V and
measurementsare at room temperature. For the target high Vt
device with Ioff 10 nA/pm, the delay per stage is 8 picosecondswhile for the low Vt device with Ioff 100 nA/pm, the
delay is 7 pica-seconds.Theseare the best reported values to
date.
Fig. 11 Cross-sectionSEM image of a processedwafer
Table I. lists the metal pitches, the pitch is 350 nm at the
first metal layer and increasesto 1200 nm at the top layer.
Metal aspectratios are optimized for minimum RC delay, and
range from 1.6 to 2. The first metal layer uses a single
damasceneprocessand tungsten plugs are used as contactsto
the silicided regions on the silicon and poly-silicon.
Unlanded contacts are supported by using a Si,N, layer for
contact etch stop. Copper interconnectsare usedbecauseof the
material’s lower resistivity. The advantageis seen in Fig. 12,
where the sheet resistance is shown as a fimction of the
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minimum pitch of each metal layer and comparedto earlier
resultsfrom 18Onmtechnologiesusing Al [3] and Cu [4]. The
presenttechnology exhibits 30% lower sheetresistanceat the
samemetal pitch due to the use of Cu with high aspectratios.
The total line capacitanceis 230 IF/mm for Ml to M5 and
slightly higher for M6.
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The SRAM performance is measured using its Fmax.
Fig. I5 shows the schmoo plot for the SRAM, i.e. the Fmax
is shown as a function of voltage. The tester capability
presently limits the Fmax measurementto 1.6GHz. As is seen
in Fig. 15, at 1.3V the SRAM operates at clock period of
0.625ns,or Fmax of 1.6Ghz.
]
1000
500
Pitch (nm)
1500
2000
Fig. 14 Top down SEM of the 2.45 urn2 6-T SRAM bit cell on
left and the 2.09 Pm2 6-T SRAM on right.
Fig. 12 Sheetresistance
as a function of layer pitch.
1.6 GHz at 1.3
To benchmarkthe performance of interconnects,Fig. 13
shows the RC delay in picosecondsper millimeter of wire.
Data for each metal layer is shown as a function of the
minimum pitch at that layer. For a given pitch, 40%
reduction in RC is achieved by using Cu interconnects and
FSG ILD.
140
120
eg 100
E 80
si
3
t
\
\
60
2 40
20
0
-+
\
Y
\,
500
0
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0.6
0.8
1
AccessTime(ns)
Al [31
Fig. 15 Fmax schmoo plot for 16Mbit SRAM.
\
Conclusion
---rr
1000
1500
Pitch (nm)
2000
Fig. 13 RC delay for a wire length of 1mm as a function of layer
pitch.
SRAM Yield and Performance
A 130 nm generation logic technology has been
demonstrated with low power high performance transistors.
Excellent interconnect performance is achieved by using 6
layers of dual damascene Cu with FSG’ dielectrics. The
technology performance capabilities are demonstrated with
ring oscillator delays of 7 ps/stageand with a 18 Mbit SRAM
operating at I .6 MHz.
A I8 Mbit CMOS SRAM [5] was shrunk to technology
Acknowledgement
design rules, the shrunk die size is 103 mm2. This SRAM is
The authors would like to thank Intel logic technology
used as a yield and reliability test vehicle during the process
development and to test and refine the SRAM cell and developmentgroups of integration/device/LYA, lithography,
support circuitry to be used in logic products. The technology etch, diffusion, thin films, polish, novel device, LTD design,
featuresenablea 2.45 urn* 6-T SRAM cell (I .4 urn x I .75 urn) sort and test, TEMKIMS Lab of Oregon, TCAD, and QRE.
without the using a local interconnect layer. Array specific
References
designrules allow a smaller 2.09 urn* 6-T SRAM cell (1.23 urn
[I] T. Ghani et. al, 1EDM Tech. Digest, pp 415-419 (1999).
x 1.69 urn), this is the densestreported cell to date. Fig. 14 [2] M. Bohr. IEDM Tech. Digest, pp 24 l-244, (1995).
showsa top down SEM of the active areasand polysilicon gate [3] S. Yang et al., IEDM Tech. Dig., pp. 197-200, (1998).
for both these cells. The SRAM die yield is equivalent to [4] S. Crowder et. al. VLSI Tech. Symp. Digest, pp 105-106(1999).
past technologies at this point of time relative to ramping in [5] C. Zhao et. al, ISSCC, ~~200, (1999).
high volume manufacturing.
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