Download Design Guide 5th generation quasi resonant coolset

DG_201609_PL83_026
5th generation quasi-resonant design guide
DG-design guide-ICE5QSAG and ICE5QRxxxxAx
About this document
Scope and purpose
This document is an engineering report that describes how to design a QR flyback converter using Infineon’s
latest 5th generation QR Controller, ICE5QSAG and CoolSET™ ICE5QRxxxxAx that offer high efficiency and low
standby power. The combination also offers selectable entry and exit standby power options, a wider VCC
operating range with fast start up, robust line protection with input Over Voltage Protection (OVP), brownout
and various other modes of protection for a highly reliable system.
Intended audience
This document is intended for power supply design/application engineers, students, etc., who wish to design a
power supply with Infineon's 5th generation QR controller, ICE5QSAG and CoolSET™ ICE5QRxxxxAx.
Table of contents
About this document....................................................................................................................... 1
Table of contents ............................................................................................................................ 1
1
Abstract ........................................................................................................................ 3
2
2.1
2.2
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
2.2.7
2.2.8
2.2.9
Description ................................................................................................................... 4
List of features ......................................................................................................................................... 4
Pin layout ................................................................................................................................................. 4
Feedback (FB) and burst entry/exit control ...................................................................................... 4
VIN (input line OVP & brownout) ....................................................................................................... 5
Current sense ..................................................................................................................................... 5
Zero Crossing Detection (ZCD) .......................................................................................................... 5
Gate drive output, controller only (GATE) ......................................................................................... 5
Source, controller only (SOURCE) ..................................................................................................... 5
Drain, CoolSETTM only (DRAIN) ........................................................................................................... 5
Positive voltage supply (VCC) .............................................................................................................. 5
Ground (GND) ..................................................................................................................................... 5
3
Overview of the QR flyback converter .............................................................................. 6
4
4.1
4.1.1
4.2
4.3
4.3.1
4.3.1.1
4.3.1.2
4.3.1.3
4.3.2
4.4
Functional description and component design .................................................................. 9
VCC pre-charging and typical VCC voltage during start up ....................................................................... 9
VCC capacitor ..................................................................................................................................... 10
Soft-start ................................................................................................................................................ 10
Normal operation .................................................................................................................................. 10
Digital frequency reduction ............................................................................................................. 11
Minimum ZC count determination ............................................................................................. 11
Up/down counter ........................................................................................................................ 11
Switch on determination ............................................................................................................ 12
Switch off determination ................................................................................................................. 12
Active burst mode with selectable power level ................................................................................... 13
Application Note
www.infineon.com
Please read the Important Notice and Warnings at the end of this document
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5th generation quasi-resonant design guide
DG-design guide-ICE5QSAG and ICE5QRxxxxAx
Abstract
4.4.1
4.4.2
4.4.3
4.5
4.6
4.7
4.8
4.9
4.10
4.11
Entering active burst mode operation ............................................................................................ 13
During active burst mode operation ............................................................................................... 14
Leaving active burst mode operation ............................................................................................. 14
Current sense......................................................................................................................................... 16
Feedback ............................................................................................................................................... 16
Zero crossing detection ........................................................................................................................ 17
Gate drive (ICE5QSAG only) .................................................................................................................. 18
Line over voltage, brownout and line selection ................................................................................... 18
Protection features ............................................................................................................................... 19
Others .................................................................................................................................................... 20
5
Typical application circuit ............................................................................................. 21
6
PCB layout recommendations ........................................................................................ 23
7
Output power of 5th generation QR ICs ............................................................................ 24
8
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
8.10
8.11
8.12
8.13
8.14
8.15
5th generation QR FLYCAL design example ....................................................................... 28
Input diode bridge (BR1): ...................................................................................................................... 28
Input capacitor (C13):............................................................................................................................ 29
Transformer design (TR1): .................................................................................................................... 30
Sense resistor (R14): .............................................................................................................................. 32
Winding design: ..................................................................................................................................... 33
Reverse voltage of diode (D21, D12): .................................................................................................... 35
Clamping network (R11, C15, and D11): ............................................................................................... 36
Output capacitors (C22, C23, C24): ....................................................................................................... 36
Output filter (L21, C24): ......................................................................................................................... 37
VCC capacitors (C16, C17): ...................................................................................................................... 38
Losses: ................................................................................................................................................... 38
Heat dissipation: ................................................................................................................................... 39
Regulation loop: .................................................................................................................................... 41
Zero crossing and output OVP: ............................................................................................................. 44
Line OVP, brownout and line selection: ............................................................................................... 45
9
References ................................................................................................................... 46
Revision history ............................................................................................................................ 46
Application Note
2
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5th generation quasi-resonant design guide
DG-design guide-ICE5QSAG and ICE5QRxxxxAx
Abstract
1
Abstract
This design guide describes how to design a QR flyback converter using ICE5QSAG/ICE5QRxxxxAx, which is the
5th generation of QR PWM controllers/CoolSET™ developed by Infineon.
The IC is optimized for offline SMPS applications including home appliances/white goods, TV, PC, server, Bluray player, set top box and notebook adapters. The improved digital frequency reduction with proprietary QR
operation offers lower EMI and higher efficiency over a wide AC range by reducing the switching frequency
difference between low- and high-line. The enhanced active burst mode power enables flexibility in standby
power operation range selection and also for QR switching in burst mode. The product has a wide operating
range (10~25.5 V) for the IC power supply and lower power consumption. The numerous protection functions
including robust line protection with input OVP and brownout giving full protection of the SMPS in potential
failure situations. All of these make the ICE5QSAG an outstanding controller for QR flyback converters.
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5th generation quasi-resonant design guide
DG-design guide-ICE5QSAG and ICE5QRxxxxAx
Description
2
Description
2.1
List of features
 Integrated 700 V/800 V avalanche rugged CoolMOS™ 1
 Novel QR operation and propriety implementation for low EMI
 Enhanced active burst mode with selectable entry and exit standby power
 Active burst mode to reach the lowest standby power <100 mW
 Fast startup achieved with cascode configuration
 Digital frequency reduction for better overall system efficiency
 Built-in digital soft start
 Cycle-by-cycle peak current limitation
 Maximum on/off time limitation to avoid audible noise during start-up and power down
 Robust line protection with input OVP and brownout
 Auto restart mode protection for VCC over voltage, VCC under voltage, overload/open loop, output over
voltage, over temperature and Current Sense (CS) short to GND
 Limited charging current for VCC short to GND
 Pb-free lead plating, halogen free mold compound, RoHS compliant
2.2
Pin layout
FB
1
PG-DSO-8
8
FB
1
VIN
2
CS
3
ZCD
4
PG-DIP-7
GND
7
VCC
1
VIN
PG-DSO-12
12
GND
2
11
VCC
CS
3
10
NC
ZCD
4
9
NC
DRAIN
5
8
DRAIN
DRAIN
6
7
DRAIN
GND
VIN
2
7
VCC
CS
3
6
SOURCE
ZCD
4
5
GATE
5
ICE5QSAG
ICE5QRxxxxAZ
Figure 1
Pin configuration
2.2.1
8
FB
DRAIN
ICE5QRxxxxAG
Feedback (FB) and burst entry/exit control
The FB pin combines the functions of feedback loop control, selectable burst entry/exit control and
overload/open loop protection.
1
CoolSET™ only
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5th generation quasi-resonant design guide
DG-design guide-ICE5QSAG and ICE5QRxxxxAx
Description
2.2.2
VIN (input line OVP & brownout)
The VIN pin is connected to the bus via resistor divider (see Figure 2) to sense the line voltage. This pin
combines the functions of input line OVP, brownout and minimum zero crossing count setting between low
and high line.
2.2.3
Current sense
The CS pin is connected externally to the shunt resistor for the primary current sensing and to the PWM signal
generator block for switch-off determination (together with the feedback voltage) internally. Additionally, CS
pin short to ground protection is sensed by this pin.
2.2.4
Zero Crossing Detection (ZCD)
The ZCD pin combines the functions of start-up, ZCD and output OVP. During the start-up, it is used to provide
a voltage level to the gate of power switch CoolMOSTM to the charge VCC capacitor.
2.2.5
Gate drive output, controller only (GATE)
The GATE pin is the output of the internal driver stage, which has a rise time of 117 ns and a fall time of 27 ns
when driving a 1 nF capacitive load.
2.2.6
Source, controller only (SOURCE)
The SOURCE pin is connected to the source of the external power switch Q1 (see Figure 2), which is in series
with the internal low side MOSFET and internal VCC diode D.
2.2.7
Drain, CoolSETTM only (DRAIN)
The DRAIN pin is connected to the drain of the integrated 700 V/800 V CoolMOSTM.
2.2.8
Positive voltage supply (VCC)
The VCC pin is the positive voltage supply to the IC. The operating range is 10~25.5 V.
2.2.9
Ground (GND)
The GND pin is the common ground for the controller/CoolSETTM.
Application Note
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5th generation quasi-resonant design guide
DG-design guide-ICE5QSAG and ICE5QRxxxxAx
Overview of the QR flyback converter
3
Overview of the QR flyback converter
Figure 2 and Figure 3 show a typical application of ICE5QSAG and ICE5QRxxxxAx in a QR flyback converter. In
this converter, the mains input voltage is rectified by the diode bridge and then smoothed by the capacitor C bus
where the bus voltage Vbus is available. The transformer has one primary winding Wp, one or more secondary
windings (Ws1 and Ws1), and one auxiliary winding Wa. When QR control is used for the flyback converter, the
typical waveforms are shown in Figure 4. The voltage from the auxiliary winding provides information about
demagnetization of the power transformer and the output voltage.
As shown in Figure 4, after switch-on of the power switch the voltage across the shunt resistor RCS shows a spike
caused by the discharging of the drain-source capacitor. After the spike, the voltage VCS shows information
about the real current through the main inductance of the transformer Lp. Once the measured current signal VCS
exceeds the maximum value determined by the feedback voltage VFB, the power switch is turned-off. During
this on-time, a negative voltage proportional to the input bus voltage is generated across the auxiliary winding.
RSTARTUP
Cbus
85 ~ 300 VAC
Lf1
DO1
Ws1
CO1
DO2
Ws2
CO2
CVCC
DZC
Dr1~Dr4
Wa
RZC
ZCD
D
VIN
RI2
GND
Power
MOSFET
Power Management
PWM controller
Current Mode Control
Cycle-by-Cycle
current limitation
RZCD
Digital Control
Protections
Figure 2
Typical application of controller
Figure 3
Typical application of CoolSETTM
VO1
Cf2
VO2
CPS
GATE
Rb1
Gate
Driver
Rb2
# Rovs3
Rc1
FB
ICE5QSAG
Controller
Rovs1
SOURCE
CS
Active Burst Mode
Zero Crossing
Detection
Lf2
Cf1
CZC
RCS
# RSel
VCC
RI1
# Optional
RSel (Burst mode level 2)
Rovs3 (V02 feedback)
Wp
Snubber
RVCC DVCC
Cc1
Optocoupler
TL431
Cc2
Rovs2
The drain-source voltage of the power switch VDS will rise quickly after the MOSFET is turned-off. This is due to
the energy stored in the leakage inductance of the transformer. A snubber circuit, RCD in most cases, can be
Application Note
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5th generation quasi-resonant design guide
DG-design guide-ICE5QSAG and ICE5QRxxxxAx
Overview of the QR flyback converter
used to limit the maximum drain source voltage. After the oscillation 1, the drain-source voltage becomes a
steady value. Here, the voltage VR is the reflected value of the secondary voltage at the primary side of the
transformer and is calculated as:
𝑉𝑅 =
(𝑉𝑜𝑢𝑡 + 𝑉𝐹𝑂𝑢𝑡 ) × 𝑁𝑃
𝑁𝑆
where, VR
(Eq 23)1
: reflected voltage
Vout
: output voltage
VFOut
: forward voltage of the secondary diode
NP
: number of primary turns of the transformer
NS
: number of secondary turns of the transformer
After oscillation 1 is damped, the drain-source voltage of the power switch shows a constant value of Vbus+VR
until the transformer is fully demagnetized. This duration increases the first portion of the off-time toff1.
After the secondary side current falls to zero, the drain-source voltage of the power switch shows another
oscillation (oscillation 2 in Figure 4, this is also referred to as the main oscillation in this document). This
oscillation occurs in the circuit consisting of the equivalent main inductance of the transformer Lp and the
capacitor across the drain-source (or drain-ground) terminal CDS which includes the Co(er) of the MOSFET. The
frequency of this oscillation is calculated as:
𝑓𝑂𝑆𝐶2 =
1
(Eq 109)
2𝜋 × √𝐿𝑃 × 𝐶𝐷𝑆
where, fOSC2
: oscillation 2 in Figure 4
LP
: primary main inductance of the transformer
CDS
: capacitance across drain to source/ground of the power switch
The amplitude of this oscillation begins with a value of VR and decreases exponentially with elapsing time,
which is determined by the loss factor of the resonant circuit. The first minimum of the drain voltage appears at
the half of the oscillation period after the time t4 and can be approximated as:
𝑉𝐷𝑆_𝑀𝑖𝑛 = 𝑉𝑏𝑢𝑠 − 𝑉𝑅
(Eq 110)
In QR control, the power switch is switched on at the minimum of the drain-source voltage. In this type of
operation, the switch-on losses are minimized, and switching noise due to dVDS/dt is reduced compared to a
normal hard-switching flyback converter.
1
Equation is used in Section 8 (5th generation QR FLYCAL design example)
Application Note
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5th generation quasi-resonant design guide
DG-design guide-ICE5QSAG and ICE5QRxxxxAx
Overview of the QR flyback converter
vOUT
toff2
toff1
ton
t
vDS
oscillation 1
V
vclmp
vbus
oscillation 2
Vrefl
tdelay1
t
tdelay2
TOSC
vZCD
t
v1
tLEB
vFB
t
i SEC
t
t1 t2
Figure 4
Application Note
t3
t4 t5 t6
t7
TOSC
Typical waveforms of 5th generation QR flyback converter
8
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Functional description and component design
4
Functional description and component design
4.1
VCC pre-charging and typical VCC voltage during start up
When an AC line input voltage is applied as shown in Figure 2 and Figure 3, a rectified voltage appears across
the capacitor Cbus. The pull up resistor RSTARTUP provides a current to charge the Ciss input capacitance of the
power switch generating a single voltage level. If the voltage across Ciss is sufficiently high, the power switch
will turn-on and the VCC capacitor will be charged through the primary inductance of transformer LP, power
switch and internal diode with two steps of constant current source IVCC_ Charge11 and IVCC_ Charge31.
A very small constant current source (IVCC_Charge1) charges the VCC capacitor until VCC reaches VCC_SCP to protect the
controller from a VCC pin short to ground during start-up. After this, the second step constant current source
(IVCC_Charge3) is provided to further charge the VCC capacitor, until VCC exceeds the turned-on threshold VVCC_ON. As
shown in the time phase I in Figure 5, VCC increases almost linearly with two steps.
Note: The recommended typical value for RSTARTUP is 50 MΩ (20 MΩ~100 MΩ), the RSTARTUP value is directly
proportional to tStartUp and inversely proportional to no load standby power
VVCC
II
I
VVCC_ON
III
VVCC_OFF
tA
tB
VVCC_SCP
t
IVCC
IVCC_Normal
t
0
IVCC_Charge1
IVCC_Charge2/3
-IVCC
Figure 5
t1
t2
VCC voltage and current at start-up
The time taken for the VCC pre-charging can then be approximated as:
𝑉𝑉𝐶𝐶_𝑆𝐶𝑃 ∙ 𝐶𝑉𝐶𝐶 (𝑉𝑉𝐶𝐶_𝑂𝑁 − 𝑉𝑉𝐶𝐶_𝑆𝐶𝑃 ) ∙ 𝐶𝑉𝐶𝐶
𝑡StartUp = 𝑡A + 𝑡B =
+
𝐼𝑉𝐶𝐶_𝐶ℎ𝑎𝑟𝑔𝑒1
𝐼𝑉𝐶𝐶_𝐶ℎ𝑎𝑟𝑔𝑒3
where, VVCC_SCP
1
2
(Eq 56B)2
: VCC short circuit protection voltage
CVCC
: VCC capacitor
VVCC_ON
: VCC turn-on threshold voltage
IVCC_Charge1
: VCC charge current 1
IVCC_Charge3
: VCC charge current 3
IVCC_ Charge1/2/3 is the charging current from the controller to VCC capacitor during start up
Equation is used in Section 8 (5th generation QR FLYCAL design example)
Application Note
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DG-design guide-ICE5QSAG and ICE5QRxxxxAx
Functional description and component design
When VCC exceeds the VCC turned-on threshold VVCC_ON at time t1, the IC begins to operate with a soft-start. Due to
the power consumption of the IC and the fact that there is no energy from the auxiliary winding to charge the
VCC capacitor before the output voltage increases, the VCC voltage drops (Phase II). Once the output voltage is
rises sufficiently, the VCC capacitor receives energy from the auxiliary winding from the time t2 onward and
delivers IVCC_ Normal1 to the controller. VCC then will reach a constant value depending on the output load.
4.1.1
VCC capacitor
Since there is VCC under voltage protection, the VCC capacitor should be selected to be large enough to ensure
that enough energy is stored in the VCC capacitor so that the VCC voltage will never reach the VCC under voltage
protection threshold VVCC_OFF before the output voltage increases. Therefore, the minimum capacitance should
fulfil the following requirement:
𝐶𝑉𝐶𝐶 >
𝐼𝑉𝐶𝐶_𝐶ℎ𝑎𝑟𝑔𝑒3 × 𝑡𝑠𝑠
𝑉𝑉𝐶𝐶_𝑂𝑁 − 𝑉𝑉𝐶𝐶_𝑂𝐹𝐹
where, IVCC_Charge3
tss
4.2
(Eq 56A)2
: VCC charge current 3
: soft-start time
Soft-start
After the supply voltage of the IC exceeds 16 V, which corresponds to t1 of Figure 5, the IC will start switching
with a soft-start. The soft-start function is built into the IC digitally. During soft-start, the peak current of the
power switch is controlled by an internal voltage reference instead of the voltage on the FB pin. The maximum
voltage on the CS pin for peak current control is increased step by step as shown in Figure 6. The maximum
duration of the soft-start is 12 ms with 3 ms for each step. During soft-start, the overload protection function is
disabled.
Vcs (V)
VCS_Peak
0.75
0.60
0.45
0.30
ton
Figure 6
4.3
3
6
9
12
Time(ms)
Maximum CS voltage during soft start
Normal operation
During normal operation, the IC consists of a digital signal processing circuit including an up/down counter, a
ZC counter and a comparator, and an analog circuit including a current measurement unit and a comparator.
1
2
IVCC_ Normal is supply current from the VCC capacitor or auxiliary winding to the controller during normal operation
Equation is used in Section 8 (5th generation QR FLYCAL design example)
Application Note
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DG-design guide-ICE5QSAG and ICE5QRxxxxAx
Functional description and component design
The switch-on and -off time points are each determined by the digital circuit and the analog circuit,
respectively. As input information for the switch-on determination, the ZC input signal and the value of the
up/down counter are required, while the feedback signal VFB and the current sensing signal VCS are necessary
for switch-off determination. Details regarding the full operation of the controller in normal operation are
covered in the following paragraphs.
4.3.1
Digital frequency reduction
As mentioned above, the digital signal processing circuit consists of an up/down counter, a ZC counter and a
comparator. These three parts are the key to implementing digital frequency reduction with decreasing load. In
addition, a ringing suppression time controller is implemented to avoid mis-triggering due to the high
frequency oscillation, when the output voltage is very low under conditions such as soft-start or output short
circuit. Functionality of these parts is described below.
4.3.1.1
Minimum ZC count determination
To reduce the switching frequency difference between low- and high-line, minimum ZC count determination is
implemented. The minimum ZC count is set to 1 if VIN is less than VIN_REF that represents low line. For high line,
the minimum ZC count is set to 3 after VIN becomes higher than VIN_REF. There is also a hysteresis VIN_REF with a
certain blanking time tVIN_REF for stable AC line selection between low and high.
4.3.1.2
Up/down counter
The up/down counter stores the number of the ZC where the main power switch is switched on after
demagnetization of the transformer. This value is fixed according to the FB voltage, VFB, which contains
information about the output power. Indeed, in a typical peak current mode control, a high output power
results in a high feedback voltage, and a low output power leads to a low regulation voltage. Hence, according
to VFB, the value in the up/down counter is changed to vary the power MOSFET off-time according to the output
power. Below, the variation of the up/down counter value according to the feedback voltage is explained.
The feedback voltage VFB is internally compared with three threshold voltages VFB_LHC, VFB_HLC and VFB_R during
each clock period of 48 ms. The up/down counter then counts upward, remains unchanged or counts
downward, as shown in Table 1.
Table 1
Operation of up/down counter
VFB
Up/down counter action
Always lower than VFB_LHC
Count upwards till n=8/101
Once higher than VF_LHC, but always lower than VFB,HLC
Stop counting, no value changing
Once higher than VFB_HLC, but always lower than VFB_R
Count downwards till n=1/32
Once higher than VFB_R
Set up/down counter to n=1/32
The number of ZC is limited and therefore, the counter varies between 1 to 8 (for low line) and 3 to 10 (for high
line) and any attempt to count beyond this range is ignored. When VFB exceeds VFB_R, the up/down counter is
reset to 1 (low line) and 3 (high line) in order to allow the system to react rapidly to a sudden load increase. The
up/down counter value is also reset to 1 (low line) and 3 (high line) at start-up, to ensure an efficient maximum
load start-up. Figure 7 shows some examples of how the up/down counter is changed according to the
feedback voltage over time.
1
2
n=8 (for low line) and n=10 (for high line)
n=1 (for low line) and n=3 (for high line)
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DG-design guide-ICE5QSAG and ICE5QRxxxxAx
Functional description and component design
The use of two different thresholds VFB_LHC and VFB_HLC to count upwards or downwards is to prevent frequency
jittering when the FB voltage is close to the threshold point.
clock
clock
T=48ms
t
VFB
t
VFB
VFB_R1
VFB_R3
VFB_HLC
VFB_HLC
VFB_LHC
VFB_LHC
t
n+2
n+3
n+3
n+3
n+2
n+1
n
1
n
n+1
n+2
n+3
n+3
n+3
n+2
n+1
n
t
n+1
Up/down
counter
n
Up/down
counter
T=48ms
3
Case 1
5
6
7
8
8
8
7
6
5
1
Case 1
6
7
8
9
9
9
8
7
6
3
Case 2
2
3
4
5
5
5
4
3
2 1
Case 2
4
5
6
7
7
7
Case 3
8
8
8
8
8
8
7
6
5 1
Case 3
10 10 10 10 10 10
Figure 7
4.3.1.3
Low line
Up/down counter operation
6
5
4 3
9
8
7 3
High line
Switch on determination
After the gate drive goes low, it cannot be changed to high during the ring suppression time.
After the ring suppression time, the gate drive can be turned on when the ZC counter value is higher or equal to
the up/down counter value.
However, it is also possible that the oscillation between the primary inductor and drain-source capacitor
damps rapidly and the IC cannot detect sufficient ZCs and the ZC counter value will not be sufficient to turn-on
the gate drive. In this case, a maximum off time is implemented. After the gate drive has remained off for the
period of TOffMax, the gate drive will be turned-on again regardless of the counter values and VZCD. This function
effectively prevents the switching frequency from reducing below 20 kHz. Otherwise, it will cause audible noise
during start up.
4.3.2
Switch off determination
In a converter system, the primary current is sensed by an external shunt resistor, which is connected between
the source terminal of the internal low side MOSFET and the common ground. The sensed voltage across the
shunt resistor VCS is applied to an internal current measurement unit, and its output voltage V1 is compared
with the regulation voltage VFB. Once the voltage V1 exceeds the voltage VFB, the output flip-flop is reset. As a
result, the main power switch is switched off. The relationship between V1 and VCS is described by:
(Eq 111A)
𝑉1 = 𝐺𝑃𝑊𝑀 ∙ 𝑉𝐶𝑆 + 𝑉𝑃𝑊𝑀
where, V1
: output voltage of comparator
GPWM : PWM output gain
VCS
: voltage across the CS resistor
VPWM : offset for voltage ramp
To avoid mis-triggering caused by the voltage spike across the shunt resistor at the turn-on of the main power
switch, a leading edge blanking time, tLEB, is applied to the output of the comparator. In other words, once the
gate drive is turned-on, the minimum on-time of the gate drive is the leading edge blanking time.
Application Note
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5th generation quasi-resonant design guide
DG-design guide-ICE5QSAG and ICE5QRxxxxAx
Functional description and component design
In addition, there is a maximum on time, tOnMax, limitation implemented in the IC. Once the gate drive has been
in a high state longer than the maximum on-time, it will be turned off to prevent the switching frequency from
reducing too far.
4.4
Active burst mode with selectable power level
In light load conditions, the IC enters active burst mode operation to minimize the power consumption. Details
about active burst mode operation are explained in the following paragraphs.
The burst mode entry level can be selected by changing the resistor RSel at the FB pin. There are 2 levels to be
selected with different resistors, which are targeted for the lower range of active burst mode power (Level 1)
and the higher range of active burst mode power (Level 2). The following table shows the control logic for the
entry and exit level with the FB voltage.
Two levels entry and exit active burst mode power
Table 2
Level
RSel
VFB
VCS
Entry level
Exit level
VFB_EBLX
VFB_LB
1
Open
VFB > VREF_B
VCS_BL1 = 0.31 V
0.90 V
2.75 V
2
580 kΩ~670 kΩ
VFB < VREF_B
VCS_BL2 = 0.35 V
1.05 V
2.75 V
During IC first startup, the RefGOOD signal is logic low when VCC < 4 V. The low RefGOOD signal will reset the burst
mode level detection latch. When the burst mode level detection latch is low and the IC is in an off state, the FB
resistor is isolated from the FB pin and thecurrent source Isel is turned on.
From VCC = 4 V to the VCC on threshold, the FB pin will start to charge to a voltage level associated with the RSel
resistor. When VCC reaches the VCC on threshold, the FB voltage is sensed. The burst mode thresholds are then
chosen according to the FB voltage level. The burst mode level detection latch is then set to high. Once the
detection latch is set high, any change of the FB level will not change the threshold level. When VCC reaches the
VCC on threshold, a timer of 2 µs is started. After the 2 µs timer ends, the current source is turned off while the FB
resistor is connected to the FB pin (see Figure 8).
Vdd
Isel
S2
UVLO
2μs
delay
R
RFB
Refgood
Burst mode detection
latch
Vcsth_burst
VFB_burst
Selection
Logic
S1
Compare
logic
FB
VREF,B
RSel
S
Control unit
Figure 8
4.4.1
Burst mode detect and adjust
Entering active burst mode operation
For determination of entering active burst mode operation, three conditions apply:
 the feedback voltage is lower than the threshold of VFB_EBLX
 the up/down counter is 8 for low-line and 10 for high-line and
 a certain blanking time tFB_BEB (20 ms).
Application Note
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5th generation quasi-resonant design guide
DG-design guide-ICE5QSAG and ICE5QRxxxxAx
Functional description and component design
Once all of these conditions are fulfilled, the active burst mode flip-flop is set and the IC enters active burst
mode operation. This multi condition determination for entering active burst mode operation prevents mistriggering of entering active burst mode operation, so that the controller enters active burst mode operation
only when the output power is actually low during the preset blanking time.
4.4.2
During active burst mode operation
After entering the active burst mode, the feedback voltage rises as VOUT starts to decrease due to the inactive
PWM section. One comparator observes the feedback signal if the voltage level VFB_BOn is exceeded. In that case,
the internal circuit is again activated by the internal bias to start switching.
Turn-on of the power switch is triggered by the ZC counter with a fixed value of 8 ZC for low-line and 10 ZC for
high-line. Turn-off is the result if the voltage across the shunt resistor at the CS pin hits the threshold VCS_BL1/
VCS_BL2.
If the output load remains low, the FB signal decreases as the PWM section is operating. When the FB signal
reaches the low threshold VFB_BOff , the internal bias is reset again and the PWM section is disabled until the next
time that the regulation signal increases beyond the VFB_BOn threshold. In active burst mode, the feedback signal
is a sawtooth between VFB_BOff and VFB_BOn (see Figure 9).
4.4.3
Leaving active burst mode operation
The feedback voltage immediately increases if there is a large load jump as observed by a comparator. As the
current limit is 31% (Level 1) and 35% (Level 2) during active burst mode, a certain load is required so that the
FB voltage can exceed VFB_LB. After leaving active burst mode, maximum current can now be provided to
stabilize the output voltage. In addition, the up/down counter will be set to 1 (low line) or 3 (high line)
immediately after leaving active burst mode. This is helpful to reduce the output voltage undershoot.
Application Note
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DG-design guide-ICE5QSAG and ICE5QRxxxxAx
Functional description and component design
VFB
VFB_LB
VFB_BOn
VFB_BOff
Entering
Active Burst
Mode
Leaving Active
Burst Mode
VF_EB
VCS
1.0V
Time to 8th/10th ZC and
Blanking Window (tBEB)
t
Current limit level during
Active Burst Mode
VCS_B
VVCC
t
VVCC_OFF
VO
t
Max. Ripple < 1%
t
Figure 9
Application Note
Signals in active burst mode
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DG-design guide-ICE5QSAG and ICE5QRxxxxAx
Functional description and component design
4.5
Current sense
The PWM comparator inside the IC has two inputs; one from the CS pin and the other from the FB voltage.
Before being sent to the PWM comparator, there is an offset and operational gain on the CS voltage. In normal
operation, the relationship between the FB voltage and maximum CS voltage is determined by equation 10.
(Eq 111B)
𝑉𝐹𝐵 = 𝐺𝑃𝑊𝑀 ∙ 𝑉𝐶𝑆 + 𝑉𝑃𝑊𝑀
where, VFB
: feedback voltage
VCS
: voltage across the CS resistor
GPWM : PWM output gain
VPWM : offset for voltage ramp
The absolute maximum CS voltage, VCS is 1 V. Therefore, the CS resistor can be chosen according to the maximum
required peak current in the transformer as shown in equation 11.
𝑅𝑆𝑒𝑛𝑠𝑒 =
𝑉𝐶𝑆_𝑁
𝐼𝑃𝑀𝑎𝑥
(Eq 21)1
where, RSense : CS resistor
VCS_N : peak current limitation in normal operation (1 V)
IPMax
: peak current of primary inductance
In addition, a Leading Edge Blanking (LEB) is already built inside the CS pin. The typical value of leading edge
blanking time is 220 ns, which can be thought as a minimum on time.
Note: In case of higher switch-on noise at the CS Pin, the IC may switch-off immediately after the LEB
time especially at light load, high-line conditions. To avoid this, a noise filtering ceramic capacitor C112
(e.g., 100 pF~100 nF, see Figure 12) can be added.
4.6
Feedback
Inside the IC, the FB pin is connected to the (VREF) 3.3 V voltage source through a pull-up resistor RFB. Outside the
IC, this pin is connected to the collector of the optocoupler. Normally, a ceramic capacitor CFB, e.g. 1 nF, can be
placed between this pin and ground to smooth the signal.
The FB voltage will be used for several functions as follows:
 It determines the maximum CS voltage, equivalent to the transformer peak current.
 It determines the ZC counter value according to the load condition
A regulation loop with a single feedback calculation is explained in section 8.13. For a dual output system with
dual feedback control this can be calculated as below.
Optocoupler
VOut1
I25=W1 x I26
R22
R24
TL431
R25
R23
Application Note
I25A=W2 x I26
R25A
C25
C26
VREF_TL=2.5 V
R26
Figure 10
VOut2
I26= I25 + I25A
Regulation loop with dual feedback
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Functional description and component design
𝑅26 =
𝑉𝑅𝐸𝐹_𝑇𝐿
𝐼26
(Eq 112)
where, VREF_TL
𝑅25 =
: TL431 reference voltage
𝑉𝑂𝑢𝑡1 − 𝑉𝑅𝐸𝐹_𝑇𝐿
𝑊1 × 𝐼26
𝑅25𝐴 =
(Eq 112A)
𝑉𝑂𝑢𝑡𝐴 − 𝑉𝑅𝐸𝐹_𝑇𝐿
𝑊2 × 𝐼26
where, W1
W2
(Eq 112B)
: weighted factor of VOut1 (important factor of VOut1)
: weighted factor of VOut2 (important factor of VOut2),
{e.g., W1 has a weight of 60% (0.6) and W 2 has a weight of 40% (0.4)}
4.7
Zero crossing detection
The circuit components connected to the ZCD pin include resistors RZC, RZCD and capacitor CZC. The values of
these three components shall be chosen so that the three functions combined on this pin will perform as
designed.
At first, the ratio between RZC and RZCD is chosen to set the trigger level of output OVP. Assuming the protection
level of the output voltage is VOut_OVP, the turns of the auxiliary winding are NA and the turns of secondary output
winding are NS, the ratio is calculated as:
𝑉
×𝑁
𝑅𝑍𝐶𝐷
(Eq 113)
< 𝑍𝐶𝐷_𝑂𝑉𝑃_𝑀𝑖𝑛 𝑆
𝑅𝑍𝐶 +𝑅𝑍𝐶𝐷
𝑉𝑂𝑢𝑡_𝑂𝑉𝑃 ×𝑁𝐴
where, RZCD
RZC
RZCD_OVP_Min
NS
NA
VOut_OVP
: internal resistor at the ZCD pin
: external resistor at the ZCD pin
: minimum voltage of output over voltage threshold
: number of secondary turns of the transformer
: number of auxiliary turns of the transformer
: user defined output over voltage threshold
Secondly, as shown in Figure 4, there are two delay times for detection of the ZC and turn-on of the power
switch. The delay time tdelay1 is the delay from the drain-source voltage across the bus voltage to the ZCD
voltage following below VZCD_CT_Typ (100 mV). This delay time can be adjusted by changing CZC. The second, tdelay2,
is the delay time from when the ZC voltage follows below 100 mV to the MOSFET is turned on. This second
delay time is determined by an internal IC circuit and cannot be changed. Therefore, the capacitance CZC is
chosen to adjust the delay time tdelay1 and the power switch is turned on at the valley point the of drain-source
voltage. This is normally done through experiment.
In addition, as shown in Figure 4, an overshoot is possible on ZCD voltages when the power switch is turned off.
This is because the oscillation 1 on the drain voltage, shown in Figure 4 may be coupled to the auxiliary
winding. Therefore, the capacitance CZC and ratio can be adjusted to obtain a trade-off between the output OVP
accuracy and the valley switching performance.
If, however, the amplitude of the ring at the ZCD pin is too small and the zero crossing cannot be detected, it is
advised to increase the drain-source capacitor, CDS of the power switch. As this capacitor would incur switching
loss, the value is suggested to be as small as possible; preferably <100 pF.
Application Note
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DG-design guide-ICE5QSAG and ICE5QRxxxxAx
Functional description and component design
Furthermore, to avoid mis-triggering of the ZCD detection immediately after the power switch is turned off, a
ring suppression time is provided. The ring suppression time is 2.5 μs (typically) if VZCD is higher than 0.45 V and
is typically 25 μs if VZCD is lower than 0.45 V. During the ring suppression time, the IC cannot be turned-on again.
Therefore, the ring suppression time can be thought of as a minimum off-time.
4.8
Gate drive (ICE5QSAG only)
Inside the gate pin, a totem drive circuit is integrated. The gate drive voltage is 10 V, which is sufficient for most
available MOSFETs. In the case of a 1nF load capacitance, the typical values of rise time and fall time are 117 ns
and 27 ns respectively. In practice, a gate resistor can be used to adjust the turn-on speed of the MOSFET. In
addition, to accelerate the turn-off speed, the gate resistor can be anti-paralleled with an ultrafast diode such
1N4148. To avoid oscillation during turn-off of the MOSFET, it is suggested that the loop area of the driver,
through gate resistor and MOSFET gate, source and back to IC ground should be as small as possible.
Note: The gate to source discharge resistor of the power switch Q1 (see Figure 2) is not permitted to be
added in ICE5QSAG as the gate pin is connected to the ZCD pin internally via RZCD. (with a gate to source
discharge resistor, the IC cannot start up at all due to due to the Q1 gate being shorted to the source and
VGS (gate threshold voltage of Q1) cannot rise during the first start-up.
4.9
Line over voltage, brownout and line selection
The input line over voltage and brownout protections are detected by sensing the voltage level at the VIN pin
through the resistor divider from the bulk capacitor. Once the voltage level at the VIN pin exceeds 2.9 V, the IC
stops switching and enters into line OVP mode. When the VIN pin voltage reduces below 2.9 V and VCC reaches
16 V, the line OVP mode is released.
If the VIN pin voltage is lower than 0.4 V, the IC will stop switching and enter brownout mode. It only releases
brownout mode when the VIN pin voltage increases above 0.66 V. There is no power switch (see Figure 2/Figure
3) switching but it always detects the VIN level in every restart cycle during line OVP or brownout mode. The
input line sensing resistors (see Figure 2/Figure 3) RI1 and RI2 can be calculated as below.
Choose RI1=9 MΩ,
Case 1: Line OVP is the first priority,
𝑅𝐼2 =
𝑅𝐼1 × 𝑉𝑉𝐼𝑁_𝐿𝑂𝑉𝑃
(𝑉𝐿𝑖𝑛𝑒_𝑂𝑉𝑃_𝐴𝐶 × √2) − 𝑉𝑉𝐼𝑁_𝑂𝑉𝑃
where, RI1
RI2
VVIN_LOVP
VLINE_OVP_AC
𝑉𝐵𝑟𝑜𝑤𝑛𝐼𝑛_𝐴𝐶 =
: high side line input sensing resistor (Typ. 9 MΩ)
: low side line input sensing resistor
: line over voltage threshold (Typ. 2.9 V)
: user defined line over voltage (V AC) for the system
( 𝑉𝑉𝐼𝑁_𝐵𝐼 ×
where, VVIN_BI
VDC_Ripple
VBrownIn_AC
1
(Eq 105A) 1
𝑅𝐼1 + 𝑅𝐼2
) + 𝑉𝐷𝐶 𝑅𝑖𝑝𝑝𝑙𝑒
𝑅𝐼2
(Eq 106)1
√2
: brownin threshold voltage (Typ. 0.66 V)
: bus capacitor DC ripple voltage which depends on AC line frequency and load (0~30 V)
: brownin voltage for the system (V AC)
Equation is used in Section 8 (5th generation QR FLYCAL design example)
Application Note
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Functional description and component design
𝑉𝐵𝑟𝑜𝑤𝑛𝑂𝑢𝑡_𝐴𝐶 =
( 𝑉𝑉𝐼𝑁_𝐵𝑂 ×
where, VVIN_BO
VBrownOut_AC
𝑉𝐿𝑖𝑛𝑒𝑆𝑒𝑙𝑒𝑐𝑡𝑖𝑜𝑛_𝐴𝐶 =
𝑅𝐼1 + 𝑅𝐼2
) + 𝑉𝐷𝐶_𝑅𝑖𝑝𝑝𝑙𝑒
𝑅𝐼2
(Eq 107) 1
√2
: brownout threshold voltage (Typ. 0.4 V)
: brownout voltage for the system (V AC)
𝑅 +𝑅
( 𝑉𝑉𝐼𝑁_𝑅𝐸𝐹 × 𝐼1 𝑅 𝐼2 ) + 𝑉𝐷𝐶_𝑅𝑖𝑝𝑝𝑙𝑒
𝐼2
(Eq 108)1
√2
: VIN voltage threshold for line selection (Typ. 1.52 V)
: brownout voltage for the system (V AC)
where, VVIN_REF
VBrownOut_AC
Case 2: Brownout is the first priority,
𝑅𝐼2 =
𝑉𝑉𝐼𝑁_𝐵𝐼 × 𝑅𝐼1
(Eq 105B) 1
(𝑉𝐿𝑖𝑛𝑒𝐵𝐼_𝐴𝐶 × √2) − 𝑉𝑉𝐼𝑁_𝐵𝐼
where, VVIN_BI
VLineBI_AC
𝑉𝐵𝑟𝑜𝑤𝑛𝑂𝑢𝑡_𝐴𝐶 =
𝑉𝐿𝑖𝑛𝑒𝑂𝑉𝑃_𝐴𝐶 =
: brownin threshold voltage (Typ. 0.66 V)
: user defined brownin voltage (V AC) for the system
𝑅 + 𝑅𝐼2
( 𝑉𝑉𝐼𝑁_𝐵𝑂 × 𝐼1
) + 𝑉𝐷𝐶_𝑅𝑖𝑝𝑝𝑙𝑒
𝑅𝐼2
(Eq 107) 1
√2
𝑅𝐼1 × 𝑉𝑉𝐼𝑁_𝐿𝑂𝑉𝑃
+ 𝑉𝑉𝐼𝑁_𝐿𝑂𝑉𝑃
𝑅𝐼2
√2
: line over voltage threshold (Typ. 2.9 V)
: line over voltage (V AC) for the system
where, VVIN_LOVP
VLineOVP_AC
4.10
(Eq 114)
Protection features
Protection is one of the major factors to determine whether the system is safe and robust. Therefore sufficient
protection is necessary. ICE5QSAG and ICE5QRxxxxAx provide comprehensive protection to ensure that the
system is operating safely. The protections include line over voltage, brownout, VCC over voltage and under
voltage, overload, output over voltage, over temperature (controller junction), CS short to GND and VCC short to
GND. When those faults are found, the system will enter a protection mode. When the fault is removed, the
system resumes normal operation. A list of protections and the failure conditions are shown in the table below.
Protection function of ICE5QSAG and ICE5QRxxxxAx
Protection function
Failure condition
Table 3
Protection mode
Line over voltage
VVIN > 2.9 V
Non switch auto restart
Brownout
VVIN < 0.4 V
Non switch auto restart
VCC overvoltage
VVCC > 25.5 V
VCC undervoltage
VVCC < 10 V
Overload
VFB > 2.75 V & lasting for 30 ms
Odd skip auto restart
Output overvoltage
VZCD > 2 V & lasting for 10 consecutive
pulses
Odd skip auto restart
Over temperature (junction
TJ > 140°C with 40°C hysteresis to
1
Odd skip auto restart
Auto restart
Non switch auto restart
Equation is used in Section 8 (5th generation QR FLYCAL design example)
Application Note
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DG-design guide-ICE5QSAG and ICE5QRxxxxAx
Functional description and component design
Protection function
temperature of controller chip only )
Failure condition
reset
CS short to GND
VCS < 0.1 V, lasting for 5 µs and 3
consecutive pulses
VCC short to GND
(VVCC=0 V, RStartUp=50 MΩ and VDRAIN=90 V)
VVCC< 1.1 V, IVCC_Charge1≈0.2 A
4.11
Protection mode
Odd skip auto restart
Cannot start up
Others
For QR Flyback converters, it is possible that the operating frequency reduces too far, which normally results in
audible noise. To prevent this in the IC, a maximum on time and off time are provided.
The maximum on time is typically 35 μs. If the gate is held on for 35 μs, the IC will turn-off the gate regardless of
the CS voltage.
When the power switch is off and the IC cannot detect sufficient ZCs to turn-on, the IC will wait until the
maximum off-time, typically 42.5 μs, is reached, then turn-on the power switch. Even a non-zero ZCD pin
voltage cannot prevent the IC from turning-on the power switch. Therefore, during soft-start, a Continuous
Current Mode (CCM) operation of the converter is expected.
For the transformer design, it is recommend to design for a minimum switching frequency (at minimum line
with maximum load) greater than or equal to 40 kHz. The maximum switching frequency should not be higher
than 200 kHz in any line and load condition due to the LEB time and minimum ringing suppression time.
Application Note
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Typical application circuit
5
Typical application circuit
50 W dual output demo board with ICE5QSAG and 16 W demo board with ICE5QR4780AZ are shown below.
Figure 11
Application Note
Schematic of DEMO_5QSAG_50W1
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Typical application circuit
Figure 12
Application Note
Schematic of DEMO_5QR4780AZ_16W1
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PCB layout recommendations
6
PCB layout recommendations
In a SMPS, the PCB layout is key to a successful design. Below are some recommendations (see Figure 11 and
Figure 12).
1.
2.
3.
4.
5.
Minimize the loop with pulse share current or voltage; examples are the loop formed by the bus voltage
source, primary winding, main power switch (Q11 (see Figure 11) in the controller and CoolSET™ power
switch CoolMOS™ inside the IC) and current sensing resistor or the loop consisting of the secondary
winding, output diode and output capacitor, or the loop of the VCC power supply.
Star the ground at the bulk capacitor C13: all primary grounds should be connected to the ground of the
bulk capacitor C13 separately at one point. This can reduce the switching noise entering the sensitive pins
of the CoolSET™ device. The primary star ground can be split into four groups as follows,
i. Combine signal (all small signal grounds connecting to the CoolSET™ GND pin such as the filter
capacitor ground C17, C18, C19, C111, C112 and optocoupler ground) and power ground (CS
resistor R14 and R14A).
ii. VCC ground includes the VCC capacitor C16 ground and the auxiliary winding ground, pin 2 of the
power transformer.
iii. EMI return ground includes the Y capacitor C12.
iv. DC ground from the bridge rectifier, BR1
Filter capacitor close to the controller ground: filter capacitors, C17, C18, C19, C111 and C112 should be
placed as close to the controller ground and the controller pin as possible so as to reduce the switching
noise coupled into the controller.
High voltage traces clearance: High voltage traces should maintain sufficient spacing to the nearby traces.
Otherwise, arcing could occur.
i. 400 V traces (positive rail of bulk capacitor C13) to nearby traces: > 2.0 mm
ii. 700/800 V traces {drain pin of power switch (Q11 (see Figure 11) in controller and drain pin of
CoolSET™ IC11 (see Figure 12)} to nearby traces: > 3 mm
Recommended minimum of 232 mm2 copper area at the drain pin to add to the PCB for better thermal
performance of the CoolSET™.
Application Note
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Output power of 5th generation QR ICs
7
Table 4
Output power of 5th generation QR ICs
Output power of 5th generation QR controller
Type
Package
Marking
220VAC ±20%1
85-300 V AC1
ICE5QSAG
PG-DSO-8
5QSAG
109 W
60 W
Table 5
Output Power of 5th generation QR CoolSET™
Type
Package
Marking
VDS
RDSon2
220 V AC ±20%3
85-300 V AC3
ICE5QR4770AZ
PG-DIP-7
5QR4770AZ
700 V
4.73 Ω
27 W
15 W
ICE5QR4780AZ
PG-DIP-7
5QR4780AZ
800 V
4.13 Ω
28 W
15 W
ICE5QR2270AZ
PG-DIP-7
5QR2270AZ
700 V
2.13 Ω
41 W
22 W
ICE5QR2280AZ
PG-DIP-7
5QR2280AZ
800 V
2.13 Ω
41 W
22 W
ICE5QR0680AZ
PG-DIP-7
5QR0680AZ
800 V
0.71 Ω
74 W
41 W
ICE5QR4770AG
PG-DSO-12
5QR4770AG
700 V
4.73 Ω
27 W
15 W
ICE5QR1680AG
PG-DSO-12
5QR1680AG
800 V
1.53 Ω
50 W
27 W
ICE5QR0680AG
PG-DSO-12
5QR0680AG
800 V
0.71 Ω
77 W
42 W
The calculated output power curves showing typical output power against ambient temperature are shown
below. The curves are derived based on a typical discontinuous mode flyback in an open frame design at
Ta=50°C, TJ=125°C (integrated high voltage MOSFET), using the minimum drain pin copper area in a 2 oz copper
single sided PCB and steady state operation only (no design margins for abnormal operation modes are
included). The output power figure is for selection purpose only. The actual power can vary depending on
specific designs.
Figure 13
Output power curve of ICE5QR4770AZ
Calculated maximum output power rating in an open frame design at Ta=50°C, TJ=125°C. The output power figure is for reference
purpose only. The actual power can vary depending on particular designs. Please contact to a technical expert from Infineon for more
information.
2
Typ. at TJ =25°C (inclusive of low side MOSFET)
3
Calculated maximum output power rating in an open frame design at Ta=50°C, TJ=125°C (integrated high voltage MOSFET) and using
minimum drain pin copper area in a 2 oz copper single sided PCB. The output power figure is for selection purpose only. The actual
power can vary depending on particular designs. Please contact to a technical expert from Infineon for more information.
1
Application Note
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DG-design guide-ICE5QSAG and ICE5QRxxxxAx
Output power of 5th generation QR ICs
Figure 14
Output power curve of ICE5QR4780AZ
Figure 15
Output power curve of ICE5QR2270AZ
Figure 16
Output power curve of ICE5QR2280AZ
Application Note
25
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Output power of 5th generation QR ICs
Figure 17
Output power curve of ICE5QR0680AZ
Figure 18
Output power curve of ICE5QR4770AG
Figure 19
Output power curve of ICE5QR1680AG
Application Note
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Output power of 5th generation QR ICs
Figure 20
Application Note
Output power curve of ICE5QR0680AG
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5th generation QR FLYCAL design example
8
5th generation QR FLYCAL design example
A 16 W 12 V QR Flyback converter with ICE5QR4780AZ design example is shown below.
Procedure
Example
Define input parameters:Minimum AC input voltage:
V AC Min
85 V
Maximum AC input voltage:
V AC Max
320 V
Line frequency:
fAC
Bulk capacitor(C13) DC ripple voltage:
V DC Ripple
Output voltage:
VOut
12 V
Forward voltage of output diode:
VF Out
0.3 V
Output ripple voltage:
VOut Ripple
Maximum output power:
POut Max
16 W
Nominal output power:
POut Nom
16 W
Minimum output power:
POut Min
3.2 W
Efficiency:
ƞ
85 %
Optocoupler gain:
Gc(200%)
Reflection voltage:
VR
90 V
VCC voltage:
VVcc
14 V
Forward voltage of VCC diode(D12):
VF VCC
0.6 V
5 generation QR CoolSET™:
CoolSET™
Switching frequency at VAC Min & POut Max:
fs
th
60 Hz
24.5 V
0.24 V
2
ICE5QR4780Z
55 kHz
Breakdown voltage:
VDS Max
Drain to source capacitance of MOSFET
(including Co(er) of MOSFET):
CDS
Effective output capacitance of MOSFET: CO(er)
600 V
7 pF
3 pF
Startup resistor RStartUp(R18+R18A+R18B): RStartUp
50 MΩ
Maximum ambient temperature:
50 °C
8.1
Ta
Input diode bridge (BR1):
There is no special requirement imposed on the input
rectifier and storage capacitor in a flyback converter. The
components will be chosen to meet the power rating and
holdup requirements.
Max. input power:
PInMax 
POutMax

Power factor
PInMax 
(Eq 1)
16W
 18.82W
0.85
cosφ
0.6
Input RMS current:
I ACRMS 
PInMax
VACMin  cos 
Application Note
I ACRMS 
(Eq 2)
28
18.82W
 0.369 A
85V  0.6
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5th generation QR FLYCAL design example
Max. DC input voltage:
VDC max PK  VACMax  2
8.2
VDCMaxPk  320V  2  452.55V
(Eq 3)
Input capacitor (C13):
Min. peak input voltage at no load condition:
VDCMinPk  VACMin  2
(Eq 4)
VDCMinPk  85V  2  120.2V
VDCMin  VDCMinPk  VDCRipple
(Eq 5)
VDCMin  120.2V  24.5V  95.69V
Discharging time at each half line cycle:

1 VDCMin 
 sin

1
VDCMinPk 
TD 
 1 
(Eq 6)

4  f AC 
90




Required energy at the discharging time of input
capacitor:
WIN  PINMax  TD
(Eq 7)
95.69V

sin 1

1
120.2V
TD 
 1 
4  60 Hz 
90




  6.61ms



WIN  18.82W  6.61ms  0.12W  s
Input capacitor (cal.):
CIN 
2 WIN
2
V DCMinPk  V DCMin
2
CIN 
(Eq 8)
2  0.12W  s
 47.04F
120.2V 2  95.69V 2
Alternatively, a rule of thumb for choosing the input
capacitor may be applied:
Input voltage
Factor
115 V
2 μF/W
230 V
1 μF/W
85 V…265 V
2…3 μF/W
CIN  PINMax  factor
(Eq 9)
CIN  18.82  2.5  47.05F
Select an input capacitor from the Epcos databook of
aluminum electrolytic capacitors
The following types are preferred:
For 85°C applications:
Series B43303…
2000 hrs life time
B43501…
10000 hrs life time
For 105°C applications:
Series B43504…
2000 hrs life time
B43505…
5000 hrs life time
Choose the rated voltage to be greater or equal to the
calculated VDCMaxPk
Choose the capacitance to be greater or equal to the
calculated CIN from Eq8
Input capacitor(C13):
Application Note
Since VDCMaxPk = 452.55 V, choose 500 V
Since CIN= 47 μF, choose 47 μF
CIN
47 μF
29
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5th generation QR FLYCAL design example
Recalculation after the input capacitor has been chosen:
2
VDCMin  VDCMinPk

2  WIN
C IN
VDCMin 
(Eq 10)
120.22  2  0.12  95.69V
47 
Note that special requirements for hold up time,
including cycle skip/dropout, or other factors that
affect the resulting minimum DC input voltage and
capacitor time should be considered at this point as
well.
8.3
Transformer design (TR1):
Max. duty cycle:
DMax 
VR
VR  VDCMin
DMax 
(Eq 11)
90
 0.48
90  95.69
ton
VClamp
VDC
t
toff
B(flux density)
0
VR
VDS_Maximum
VDS_Norminl
VDS
Discontinuous Conduction Mode (DCM)
0
t
IP
ΔI
IP_Max
IAV
0
t
IS
0
Figure 21
Application Note
t
Typical waveforms for DCM operation
30
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5th generation QR FLYCAL design example
𝐿𝑃 =
1
[
2
𝑉
1
×√2×𝑓𝑠 ×𝑃𝐼𝑛 𝑀𝑎𝑥 ×( 𝐷𝐶 𝑀𝑖𝑛+1)+(𝜋×𝑓𝑠 ×√𝐶𝐷𝑆 )]
𝑉𝐷𝐶 𝑀𝑖𝑛
𝑉𝑅
I AV 
PInMax
VDCMin  DMax
𝐿𝑃 =
(Eq 12)
I AV 
(Eq 13)
V
 DMax
I  DCMin
LP  f s
I 
(Eq 14)
1
2
1
95.69
[
× √2 × 55 × 18.82 × (
+ 1) + (𝜋 × 55 × √7𝑝)]
95.69
90
= 1𝑚𝐻
18.82
 0.41A
95.69  0.48
95.69  0.48
 0.82 A
1 103  55  103
Maximum current for primary inductance:
I PMax  I AV 
I
2
IValley  I PMax  I
0.84
 0.82 A
2
(Eq 15)
I PMax  0.41 
(Eq 16)
IValley  0.82  0.82  0 A
(Eq 17)
I PRMS  [3  (0.41) 2  (
RMS current for primary inductance :
I PRMS  [3  ( I AV ) 2  (
I 2 D max
) ]
2
3
0.82 2 0.48
) ]
 0.33 A
2
3
Select Core: E 20/10/6
Material = N87
Select core type & data from the Epcos "Ferrite
BS = 390 mT @100°C
magnetic design tool" or "Datasheet".
Ae = 32 mm2
Fix max. flux density:
BW = 11 mm
Typically, BMax≈0.2T…0.4T for ferrite cross depending on
AN = 34 mm2
core material.
lN = 41.2 mm
We chose 300 mT for Material N87.
Maximum flux density
BMax
300 mT
Number of primary inductance (cal.):
NP 
I PMax  L p
BMax  Ae
Number of primary turns:
0.82 110 3
NP 
 86.57Turns
0.3  32 10 6
(Eq 18)
NP
88 turns
Number of secondary turns (cal.):
NS 
N P  VOUT  VFDIODE 
VR
Number of secondary turns:
N S _ cal 
(Eq 19)
NS
88  12  0.3
 12.03Turns
90
12 turns
Number of VCC turns (cal.):
NVcc 
N P  VVcc  VFVcc 
VR
Number of VCC turns:
Application Note
N Aux _ cal 
(Eq 20)
NVcc
66  14  0.6
 14.24Turns
90
14 turns
31
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5th generation QR FLYCAL design example
8.4
Sense resistor (R14):
The sense resistance can be used to individually define
the maximum peak current and thus the maximum
power transmitted.
Caution:
When calculating the maximum peak current, short term
peaks in output power must also be taken into
consideration.
Sense resistor(R14):
RSense 
Vcsth
I PMax
1
 1.21
0.83
(Eq 21)
RSense 
(Eq 22)
PSR  0.33 1.21  0.13W
Power rating of sense resistor:
2
PSR  I PRMS
 RSense
2
Verification of reflection voltage, duty cycle and
maximum flux density
Reflected voltage:
VR 
VOUT  VFOut   N P
NS
VR 
(Eq 23)
12  0.3  88  90.20V
12
Max. turn-on duty cycle:
Dmax 
LP  ( I PMax  IValley )  f S
VDC min
1103  (0.82 A  0 A)  55  103

 0.48
95.69
(Eq 24)
Dmax
(Eq 25)
1 103  (0.82 A  0 A)  55  103
D'max 
 0.51
90.2
Max. turn-off duty cycle:
D' max 
LP  ( I PMax  I Valley )  f S
VR
Max. flux density:
Bmax 
LP  I PMax
N P  Ae
(Eq 26)
Bmax
1103  0.82

 295mT
88  32  106
Maximum secondary current and load factor:
K L(n) 
PO ( n )
PO
I SMax  K L ( n )  I PMax 
NP
NS
16
1
16
(Eq 27)
K L (1) 
(Eq 28)
I SMax  1 0.82 
(Eq 29)
I SRMS  0.33 
88
 6.04 A
12
Secondary RMS current:
I SRMS  I PRMS 
Application Note
1  DMax
VR

DMax
VOut  VFOut
32
1  0.48
90.2

 2.49 A
0.48
12  0.3
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5th generation QR FLYCAL design example
8.5
Winding design:
Safety standard margin:
M=4 mm for European safety standard
M=3.2 mm for UL1950
M=0 for triple insulated wire
Safety standard margin:
M
Copper space factor:
fCu
0 mm
0.3
(Range 0.2 … 0.4)
Effective bobbin width:
BWE  BW  2  M 
(Eq 30)
BWe  11  0  11mm
(Eq 31)
ANe 
34  11
 34mm2
11
(Eq 32)
AP 
0.5  0.3  34
 0.06mm2
88
(Eq 33)
AS 
0.45  0.3  34mm2
 0.38mm2
12
(Eq 34)
AVcc 
Effective winding cross section:
AN  BWe
BW
ANe 
The winding cross section AN has to be subdivided
according to the number of windings:
Primary winding
0.5
Secondary winding
0.45
Auxiliary winding
0.05
Wire copper area for primary winding:
AP 
0.5  f Cu  ANe
NP
Wire copper area for secondary winding:
AS 
0.45  f Cu  ANe
NS
Wire copper area for auxiliary winding:
AVcc 
0.05  f Cu  ANe
N Aux
0.05  0.3  34mm2
 0.03mm2
14
Wire size in AWG can be calculated:
AWG  9.97  1.8277  2  logd 
(Eq 35)
Wire diameter from copper area:
A
d  2

(Eq 36)
Wire diameter from AWG:
 1.8277 AWG 



2
29.97 
d  10
(Eq 37)
Wire size in AWG using a combination of Eq. 35 and Eq.
36:



AP   

AWGPc  9.97  1.8277   2  log 2 











0.06mm2
AWG Pc  9.97  1.8277   2  log 2 







  



AWGPc = 30
Application Note
33
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5th generation QR FLYCAL design example



AS   

AWGSc  9.97  1.8277   2  log 2 











0.38mm2
AWGSc  9.97  1.8277   2  log 2 







  



AWGSc = 21



AWGVccc  9.97  1.8277   2  log 2 





AAux   

   



0.03mm2
AWGVccc  9.97  1.8277   2  log 2 







  



AWGVccc = 32
It is a good practice to use smaller wires in parallel
instead of using one large wire. However, the following
conditions should be satisfied when choosing wire size
and number of parallel wires:
- EffCuAreaX (Eq 40) ≤ AX (Eq 34/35)
- SX (Eq 41) ≤ 8 A/mm2
- NPX ≤ 10
- 0.18 mm ≤ wire diameter ≤ 0.6 mm
Note: X = P/Primary or S/Secondary winding
Wire size in AWG for primary:
AWGP
Number of parallel wires for primary:
NPP
Insulation thickness of primary wire:
INSP
Wire size in AWG for secondary:
AWGS
Number of parallel wires for secondary:
NPS
Insulation thickness of secondary wire:
INSS
30
1
0.02 mm
21
1
0.02 mm
Typically, the auxiliary winding consists of only one wire
and its size is irrelevant due to the low current carried.
Recalculate wire diameter using Eq. 37:
d P  10
d S  10
 1.8277 AWGP 



29.97 
 2
d P  10
 1.8277 AWGS 



29.97 
 2
d S  10
 1.8277 30 



29.97 
 2
 1.8277 21 



29.97 
 2
 0.25mm
 0.72mm
Effective copper area:
2
d
EffCuArea       NP
 2
(Eq 38)
2
 0.25 
2
EffCuArea P  
    88  0.05mm
 2 
2
d 
EffCuArea P   P     NPP
 2 
2
2
d 
EffCuArea S   S     NPS
 2
 0.72mm 
2
EffCuArea S  
   12  0.41mm
2 

Current Density:
S
I RMS
EffCuArea
Application Note
(Eq 39)
34
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5th generation QR FLYCAL design example
I PRMS
EffCuArea P
I SRMS
SS 
EffCuArea S
0.33
A
 6.35
0.05
mm2
2.49
A
SS 
 6.01
0.41
mm2
SP 
SP 
Wire outer diameter including insulation:
Od  d  2  INS 
(Eq 40)
OdP  0.25  2  0.02  0.29mm
OdP  d P  2  INS P 
OdS  0.72  2  0.02  0.76mm
Od S  d S  2  INS S 
Max. number of turns per layer:
 BWe 
NL  

 Od  NP 
 BWe 
NLP  

 Od P  NPP 
(Eq 41)
 11 
NLP  
 37Turns / Layer
 0.29 1
 BWe 
NLS  

 OdS  NPS 
 11 
NLS  
 14Turns / Layer
 0.76  1
Min. number of layers:
N 
Ln  
 NL 
N 
LnP   P 
 NLP 
(Eq 42)
 88 
LnP     3Layers
 37 
N 
LnS   S 
 NLS 
8.6
12 
LnS     1Layers
14 
Reverse voltage of diode (D21,
D12):
The output rectifier diodes in flyback converters are
subjected to large peak and RMS current stresses. The
values depend on the load and operating mode. The
voltage requirements depend on the output voltage and
transformer winding ratio.
Max. reverse voltage for output diode:

N
VRDiode  VOUT  VDCMaxPk  S
NP




(Eq 43A)
12 

VRDiode  12   452.54    73.71V
88 

(Eq 43B)
14 

VRDiode  14   452.54    86.00V
88 

Max. reverse voltage for the VCC diode:

N
VRDiode  VVcc  VDCMaxPk  Vcc
NP

Application Note



35
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DG-design guide-ICE5QSAG and ICE5QRxxxxAx
5th generation QR FLYCAL design example
8.7
Clamping network (R11, C15,
and D11):
Clamping voltage:
VClamp  VDSMax V DCMaxPkVR
VClamp  600  452.54  90.2  57.25V
(Eq 44)
For calculating the clamping network, it is necessary to
know the leakage inductance. The most common
approach is to have the leakage inductance value
defined as a percentage of the primary inductance.
If it is known that the transformer construction is very
consistent, measuring the primary leakage inductance
by shorting the secondary windings will give an exact
number (assuming the availability of a good LCR
analyser)
Leakage inductance in % of LP:
LLK%
1.06%
Leakage inductance:
LLK  LLK %  LP
(Eq 45)
LLK  1.06% 1103  10.7H
(Eq 46)
2

0.82  10.7  106
CClamp 
 0.9nF
90.2  57.25 57.25
Clamping capacitor :
CClamp 
2
I PMax
 LLK
VR  VClamp VClamp
Clamping capacitor:
CClamp
1 nF
Clamping resistor:
RClamp
V

2
Clamp  VR   VR
0.5  LLK  I
2
PMax
 fS
Clamping resistor:
8.8
2
2

57.25  90.2  90.2
RClamp 
2
0.5  10.7  10 6  1.51A  55  10 3
2
(Eq 47)
RClamp
 68.2k
68 kΩ
Output capacitors (C22, C23,
C24):
Output capacitors are highly stressed in Flyback
converters. Normally, capacitors are chosen based on 3
major parameters: capacitance, low ESR and ripple
current rating.
To calculate the output capacitors, the maximum voltage
overshoot when switching off at maximum load
conditions must be set.
Max. voltage overshoot:
0.5 V
ΔVOUT
After switching off the load, the control loop requires
approximately 10 to 20 internal clock periods to reduce
the duty cycle.
Number of clock periods:
nCP
20
Max. output current:
Application Note
36
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DG-design guide-ICE5QSAG and ICE5QRxxxxAx
5th generation QR FLYCAL design example
I OutMax 
POutMax
VOut
(Eq 48)
I OutMax 
(Eq 49)
I Ripple 
(Eq 50)
COut 
16
 1.33 A
12
Ripple current:
I Ripple 
I SRMS 2  I OutMax 2
2.492  1.332
 2.1A
Output capacitance (cal.):
COut 
I OUT max  nCP
VOUT  f
The output capacitor can be selected as the following
conditions can be summarized as the following:
- Rated voltage of capacitor. ≥ (1.45∙VOut)
- (IacR∙nc) close to IRipple
- (COUT∙nc) close to COUT_cal
- nc ≤ 5
1.33  20
 970F
0.5  55 103
We chose Epcos B41889 (very low impedance)
1000 μF 16 V (RESR=0.028 Ω, IacR=2.8 A @ 100 kHz 85°C)
Output capacitor:
COut
1000 μF
Number of parallel capacitors:
nc
1
8.9
Output filter (L21, C24):
The output filter consists of one capacitor and one
inductor in a L-C filter topology.
Zero frequency of output capacitors and associated ESR:
f ZCOut 
1
2    RESR  COut
(Eq 51)
f ZCOut 
1
 5.68kHz
2    0.028  1000  106
VRipple1 
6.04  0.028
 0.17V
1
This equation is based on the assumption that all output
capacitors have the same capacitance and ESR.
Ripple voltage at 1st stage:
VRipple1 
I SMax  RESR
nc
(Eq 52)
The inductance is required to compensate the zero
frequency caused by output capacitors:
L-C filter inductance:
LOUT
2.2 μH
L-C capacitor (cal.):
C LC 
COut  RESR 2
LOut
L-C capacitor:
(Eq 53)
CLC
1000 10

CLC

2
6
 0.028
 356F
2.2  106
470 μF
Frequency of L-C filter:
f LC 
1
2    CLC  LOUT
f LC 
(Eq 54)
1
2    470  106  2.2  106
 4.95kHz
Ripple voltage at 2nd stage:
VRipple2  VRipple1 
1
2    f  CLC
1
 2    f  LOUT 
2    f  CLC
Application Note
(Eq 55)
VRipple2  0.17 
37
1
2    55  103  470 10 6

1
 2    55  103  2.2  10 6
2    55  103  470 10 6

 1.36mV
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5th generation quasi-resonant design guide
DG-design guide-ICE5QSAG and ICE5QRxxxxAx
5th generation QR FLYCAL design example
8.10
VCC capacitors (C16, C17):
The VCC capacitor has to ensure the power supply to the
IC until the power can be provided by the VCC winding.
In addition, it is recommended to use a 100 nF ceramic
capacitor very close to pins 7 & 8 in parallel to the VCC
capacitor. Alternatively, an HF-type electrolytic with low
ESR and ESL may be used.
VCC capacitor:
IVCC_Charge3 from datasheet:
IVCC_Charge3
tSS from datasheet:
tSS
CVcc 
IVCC _ Charg e3  t SS
VVCC _ ON  VVCC _ OFF
VCC capacitor:
3 mA
12 ms
(Eq 56A)
CVcc 
3  103  12  103
 6F
16  10
CVcc
10 μF
Start-up time:
VVCC_SCP from datasheet:
𝑡StartUp
𝑉𝑉𝐶𝐶_𝑆𝐶𝑃 ∙ 𝐶𝑉𝐶𝐶 (𝑉𝑉𝐶𝐶_𝑂𝑁 − 𝑉𝑉𝐶𝐶_𝑆𝐶𝑃 ) ∙ 𝐶𝑉𝐶𝐶
=
+
𝐼𝑉𝐶𝐶_𝐶ℎ𝑎𝑟𝑔𝑒1
𝐼𝑉𝐶𝐶_𝐶ℎ𝑎𝑟𝑔𝑒3
8.11
VVCC_SCP
1.1 V
(Eq 56B)
𝑡StartUp
1.1 × 10 × 10−6 (16 − 1.1) ∙ 10 × 10−6
=
+
= 108𝑚𝑠
0.2 × 10−3
3 × 10−3
Losses:
Diode bridge forward voltage:
VF
1V
Input diode bridge loss:
PDIN  2  I ACRMS VF
(Eq 57)
Copper resistivity @ 100°C:
ρ100
PDIN  2  0.36  1  0.74W
0.0172 Ω∙mm2/m
Copper resistance:
RCu 
RPCu
l N  N  100
EffCuArea
(Eq 58)
l  N P  100
 N
EffCuArea P
RPCu 
l  N S  100
RSCu  N
EffCuArea S
RSCu 
41.2mm 88  0.0172
0.05mm2
  mm2
m
 1205.44m
41.2mm  12  0.0172
0.41mm2
  mm2
m
 20.57m
Copper resistance loss on primary side:
2
PPCu  I PRMS
 RPCu
(Eq 59)
PPCu  0.33  1205.44  130.26mW
(Eq 60)
PSCu  2.49  20.57  127.06mW
(Eq 61)
PCu  130.26  127.06  257.32mW
2
Copper resistance loss on secondary side:
2
PSCu  I SRMS
 RSCu
2
Total copper resistance loss:
PCu  PPCu  PSCu
Application Note
38
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DG-design guide-ICE5QSAG and ICE5QRxxxxAx
5th generation QR FLYCAL design example
Output rectifier diode loss:
PDOut  I SRMS VFOut
(Eq 62)
PDOut  2.49  0.6  0.75W
(Eq 63)
PClamper  12  10.7  106  0.82  55  103 
Clamping network loss:
2
PClamper  12  LLK  I PMax
 fS 
VClamp  VR
VClamp
Junction temperature:
2
Tj
57.25  90.2
 0.51W
57.25
125 °C
On-resistance at junction temperature:
 

RDSon@T j  RDSon@ 25C  1 

 100 
T j 25C 
12525
(Eq 64)
0.8 

RDSon@T j  4.03  1 

 100 
(Eq 65)
PSON1  12  3  4  1012  95.69  90.2  55  103  5.792W
(Eq 66)
PD1  0.33  8.59  928.3mW
(Eq 67)
PMOSFET1  5.792W  928.3mW  928.3mW
(Eq 68)
PSON1  12  3  4  1012  424.26  90.2  72  103  32.86mW
(Eq 69)
 1  103  0.82  72  103 
2
  255.15mW
PD 2  13  8.59  0.82  

424.26


(Eq 70)
PMOSFET 2  32.86mW  255.15mW  288mW
(Eq 71)
PMOSFET  max928.3mW,288mW   928.3mW
 8.59
MOSFET losses in VACmin scenario:
Switching loss in VACmin scenario:


PSON1  12  Co(er )  CDS  (VDCMin  VR ) 2  f S
2
Conduction loss in VACmin scenario:
2
PD1  I PRMS
 RDSon@T j
2
Total MOSFET loss in VACmin scenario:
PMOSFET1  PSON1  PD1
MOSFET losses in VACmax scenario:
Switching loss in VACmax scenario:


PSON 2  12  Co(er )  CDS  (VDCMaxPk  VR ) 2  f S
2
Conduction loss in VACmax scenario:
f 
L I
2
PD 2  13  R DSon@ T j  I PMax
  P PMax S 
V
DCMaxPk


Total MOSFET loss in VACmax scenario:
PMOSFET 2  PSON 2  PD 2
MOSFET losses:
PMOSFET  max PMOSFET1 , PMOSFET 2 
8.12
Heat dissipation:
No CoolSET™ device in a DSO/DIP package can use a
heatsink but using the copper area is possible. However,
all CoolMOS™ devices can use a heatsink.
Thermal resistance:
In the case of no heatsink (for CoolSET™)
Typical thermal resistance [K/W]:
RthJA=96 K/W (DIP-7)
RthJA=110 K/W (DSO-12)
RthJA=185 K/W (DSO-8)
Rth  RthJA
Application Note
Rth  96K / W
(Eq 72)
39
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DG-design guide-ICE5QSAG and ICE5QRxxxxAx
5th generation QR FLYCAL design example
In the case of a heatsink (for controller)
Rth  RthJC  RthHT  RthHS
(Eq 73)
where RthJC : TR. junction-case
RthHT : TR. case-heatsink
RthHS : TR. heatsink-ambient
From CoolMOS™/power switch datasheet
Typ. 1K/W
Depending on heat sink
Delta temperature from MOSFET losses:
T  PMOSFET  Rth
(Eq 74)
T  928.3mW  96K / W  89.1K
(Eq 75)
T j max  50C  89.1  139.1C
Max. junction temperature:
T j max  Ta  T
The maximum junction temperature must not exceed the
limitation stated in the datasheet, typically 150°C.
Controller loss:
PController  VVcc  IVCC _ Normal
(Eq 76)
PController  13.75  0.9  103  12.4mW
(Eq 77)
PLosses  0.74  0.25  0.75  0.51  0.9283 0.0124  3.2W
(Eq 78)
L 
Total loss:
PLosses  PDIN  PCu  PDOut 
PClamp  PMOSFET  PController
Efficiency after losses consideration:
L 
POutMax
POutMax  PLosses
16
 83.35%
16  3.2
Please note that the calculated efficiency above is based
on the worst case scenario where the highest loss is
present.
Application Note
40
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5th generation quasi-resonant design guide
DG-design guide-ICE5QSAG and ICE5QRxxxxAx
5th generation QR FLYCAL design example
8.13
Regulation loop:
Reference: TL431
Optocoupler: SFH617-3
VOut
R22
VREF
RFB
R24
FB
C25
C26
VFB
Figure 22
R25
R23
TL431
R26
Regulation loop
TL431 reference voltage:
VREF_TL
2.5 V
Min. current for TL431 diode:
IKAmin
1 mA
Max. current of SFH617-3 diode:
IFmax
10 mA
Forward voltage of optocoupler diode:
VFOpto
Optocoupler gain
GC(200%)
CoolSET™ trimmed reference voltage:
VREF
CoolSET™ :
VFBmax
RFB (FB pull-up resistor):
RFB
15 kΩ
R26 value of voltage divider:
R26
10 kΩ
1.25 V
2
3.3 V
2.75 V
Primary side:
Max. FB current:
VREF
RFB
(Eq 79)
I FB max 
3.3
 0.22mA
15  103
(Eq 80)
I FB min 
3.3  2.75
 0.036mA
15  103
 V

R25  R26   Out  1
V

 REF _ TL

(Eq 81)
 12

R25  15  103  
 1  38k
 2.5 
R26 value of voltage divider:
R25
I FB max 
Min. FB current:
I FB min 
VREF  VFB max
RFB
Secondary side:
R25 value of voltage divider:
Application Note
38 kΩ
41
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DG-design guide-ICE5QSAG and ICE5QRxxxxAx
5th generation QR FLYCAL design example
R22 Value to supply optocoupler diode:
R22 
VOUT  VFOpto  VREF _ TL 
R 22 
(Eq 82)
I F max
R22 Value to supply optocoupler diode:
R22
12  1.25  2.5
 825
10  103
820 Ω
R23 Value to supply TL431 diode:

I
VFOpto   R 22  FB min
Gc

R 23 
I KAmin




0.036  103 

1.25   820 

2

  1.26k
R 23 
1  103
(Eq 83)
R4 Value to supply TL431 diode:
R23
1.2 kΩ
Output voltage from regulation loop:
 R25 
VOUT _ RL  
 1 VREF _ TL
 R26 
 38  103 
VOUT _ RL  
 1  2.5V  12V
3
 10  10

(Eq 84)
Regulation loop elements:
VIN
FPWR(p)
FLC(p)
Vout
KFB
_
KVD
Fr(p)
+
Figure 23
Vref
Block diagram of regulation loop
Feedback transfer characteristic:
K FB 
Gc  RFB
R 22
2  15  103

 36.59
820
(Eq 85)
K FB
(Eq 86)
GFB  20  log 35.81  31.27dB
(Eq 87)
KVD 
Gain of feedback transfer characteristic:
GFB  20 logK FB 
Voltage divider transfer characteristic:
KVD 
VREF _ TL
VOUT _ RL

R 25
R 25  R 26
38  103
 0.21
38  103  10  103
Gain of voltage divider transfer characteristic:
GVD  20 logKVD 
GVD  20  log0.21  13.62dB
(Eq 88)
Zeroes and poles of transfer characteristics:
Resistance at Max. load pole:
RLH 
2
VOUT
_ RL
POutMax
Application Note
(Eq 89)
RLH 
42
122
 9
16
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DG-design guide-ICE5QSAG and ICE5QRxxxxAx
5th generation QR FLYCAL design example
Resistance at min. load pole:
RLL 
2
VOUT
_ RL
POutMin
(Eq. 90)
RLL 
122
 45
3.2
(Eq 91)
f OH 
1
 35.37Hz
  9  1  1000 106
(Eq 92)
f OL 
1
 7.07Hz
  45  1  1000 106
Poles of power stage at max. load pole:
f OH 
1
  RLH  nc  COUT 


Poles of power stage at min. load pole:
f OL 
1
  RLL  nc  COUT 


In order to have sufficient phase margin at low load
conditions, we chose the zero frequency of the
compensation network to be in the middle between the
min. and max. load poles of the power stage.
Zero frequency of the compensation network:
f OM  f OH 10
 f 
0.5log OL 
 f OH 
 7.07 
0.5log

 35.37 
(Eq 93)
f OM  35.37  10
 15.82Hz
With adjustment of the transfer characteristics of the
regulator, we want to attain equal gain within the
operating range and to compensate the pole fo of the
power stage FPWR(ω)
Due to the compensation of the output capacitor's zero
(Eq 53), we neglect it as well as the LC-filter pole (Eq 56).
Consequently, the transfer characteristic of the power
stage is reduced to a single-pole response.
In order to calculate the gain of the open loop, we have
to choose the crossover frequency.
We calculate the gain of the power stage with maximum
output power at the chosen crossover frequency.
Zero dB crossover frequency:
fg
3 kHz
Transient impedance calculation:
Transient impedance defines the direct relationship
between the level of the peak current and the feedback
pin voltage. It is required for the calculation of the power
stage amplification.
Transient impedance:
Z PWM 
R
VFB
 AV  Sense
I PK
Vcsth
1.21
V
 2.42
1
A
(Eq 94)
Z PWM  2 
(Eq 95)




3
3
1
 f   1  9  1  10  55  10  0.85  
F
PWR  g  2.42

2
2
 3  103 



 1 
35.37 




Power stage at crossover frequency:
FPWR  f g  
RLH
1

Z PWM


 Lp  f  P 
1


2
 f
 1  g
f

 OH




2












  0.0707





Gain of power stage at crossover frequency:
Application Note
43
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DG-design guide-ICE5QSAG and ICE5QRxxxxAx
5th generation QR FLYCAL design example

GPWR  f g   20 log FPWR  f g 

GPWR 3kHz  20  log0.0707  23.01dB
(Eq 96)
At the crossover frequency (fg), we calculate the open
loop gain:
GOL    Gs   Gr   0
(Eq 97)
With the equations for the transfer characteristics, we
calculate the gain of the regulation loop at fg:
Gs   GFB  GPWR  GVD
(Eq 98)
Gs   31.27  23.01 13.62  5.39dB
(Eq 99)
Gr    0   5.39dB  5.39dB
(Eq 100)
5.39
R24  10 20
Separated components of the regulator:
Gr   0  Gs 
R24 value of compensation network:
R24  10
Gr
20
R25  R26

R25  R26
R24 value of compensation network:
R24

38  103  10  103
 14.68k
38  103  10  103
15 kΩ
C26 value of compensation network:
C 26 
1
2    R 24  f g
C 26 
(Eq 101)
1
 3.53nF
2    15  103  3  103
Use table E12, find the closest higher value
C26 value of compensation network:
C26
3.3 nF
C25 value of compensation network:
C 25 
1
 C 26
2    R24  f OM
(Eq 102)
C25 value of compensation network:
8.14
C 25 
C25
1
 3.3  109  667.52nF
2    15  103  15.82
680 nF
Zero crossing and output OVP:
RZC(R15) value of zero crossing and output OVP:
User defined VOut_OVP value:
VOut_OVP
RZCD value from datasheet:
RZCD
 N
VOut _ OVP  VFOut
R15  RZCD   VCC 

VZCD _ OVP _ Min
 N S1
15.9 V
3 kΩ
 
  1 (Eq 103)
 
 
 14 15.9  0.3  
R15  3 103   
  1  26.84k
1.9  
 12
R15 value of zero crossing and output OVP: R15
27 kΩ
C19 value of zero crossing and output OVP:
Measured fosc2 (see Figure 4):
fosc2
800 kHz
Delay time of controller:
tdelay
100 ns

1

C19  tan2      tdelay  fosc2  
4


R15  RZCD
1

R15  RZCD 2    fosc2

1
 27  103  3  103
1
C19  tan2      100  109  800  103  

 134 pF
4
 27  103  3  103 2    800  103

(Eq 104)
C19 value of zero crossing and output OVP: C19
Application Note
120 pF
44
Revision 1.0
2017-03-10
5th generation quasi-resonant design guide
DG-design guide-ICE5QSAG and ICE5QRxxxxAx
5th generation QR FLYCAL design example
8.15
Line OVP, brownout and line
selection:
The voltage divider resistors RI1 (R18+R18A+R18B) and RI2
(R19) can be used to define the line OVP and brownout of
the system.
R19 value for line OVP and brownout:
User defined VLine_OVP_AC value:
VLine_OVP_AC
320 V
VVIN_LOVP value from datasheet:
VVIN_LOVP
2.9 V
VVIN_LOVP value from datasheet:
VVIN_BO
0.4 V
VVIN_LOVP value from datasheet:
VVIN_BI
0.66 V
VVIN_REF value from datasheet:
VVIN_REF
1.52 V
Selected RI1 (R18+R18A+R18B) value:
𝑅18 × 𝑉𝑉𝐼𝑁_𝐿𝑂𝑉𝑃
𝑅19 >
(𝑉𝐿𝑖𝑛𝑒_𝑂𝑉𝑃_𝐴𝐶 × √2) − 𝑉𝑉𝐼𝑁_𝐿𝑂𝑉𝑃
RI1
RI2 (R19) value for line OVP and brownout:
R19
9 MΩ
R19 >
(Eq 105A)
9 × 109 × 2.9
(320 × √2) − 2.9
= 58.04𝑘Ω
58.3 kΩ
VBrownIn_AC value with the selected R19:
𝑉𝐵𝑟𝑜𝑤𝑛𝐼𝑛_𝐴𝐶 =
( 𝑉𝑉𝐼𝑁_𝐵𝐼 ×
𝑅𝐼1 + 𝑅𝐼2
) + 𝑉𝐷𝐶 𝑅𝑖𝑝𝑝𝑙𝑒
𝑅𝐼2
√2
(Eq 106)
𝑉𝐵𝑟𝑜𝑤𝑛𝑂𝑢𝑡_𝐴𝐶 =
(0.66 ×
9 × 109 + 58.3 × 103
)
58.3 × 103
= 73𝑉
√2
VBrownOut_AC value with the selected R19 and VDC Ripple (for full
load condition):
𝑉𝐵𝑟𝑜𝑤𝑛𝑂𝑢𝑡_𝐴𝐶 =
( 𝑉𝑉𝐼𝑁_𝐵𝑂 ×
𝑅𝐼1 + 𝑅𝐼2
) + 𝑉𝐷𝐶 𝑅𝑖𝑝𝑝𝑙𝑒
𝑅𝐼2
√2
(Eq 107)
𝑉𝐵𝑟𝑜𝑤𝑛𝑂𝑢𝑡_𝐴𝐶 =
(0.4 ×
VBrownOut_AC value with the selected R19 and negelect
VDC Ripple (for light load condition):
𝑉𝐵𝑟𝑜𝑤𝑛𝑂𝑢𝑡_𝐴𝐶 =
(0.4 ×
9 × 109 + 58.3 × 103
) + 24.5
58.3 × 103
= 61𝑉
√2
9 × 109 + 58.3 × 103
)
58.3 × 103
= 44𝑉
√2
VLineSelection_AC value with the selected R19 and VDC Ripple (for
full load condition):
𝑉𝐿𝑖𝑛𝑒𝑆𝑒𝑙𝑒𝑐𝑡𝑖𝑜𝑛_𝐴𝐶 =
( 𝑉𝑉𝐼𝑁_𝑅𝐸𝐹 ×
𝑅𝐼1 + 𝑅𝐼2
) + 𝑉𝐷𝐶 𝑅𝑖𝑝𝑝𝑙𝑒
𝑅𝐼2
√2
(Eq 108)
𝑉𝐿𝑖𝑛𝑒𝑆𝑒𝑙𝑒𝑐𝑡𝑖𝑜𝑛_𝐴𝐶 =
(1.52 ×
VLineSelection_AC value with the selected R19 and neglect VDC
Ripple (for light load condition):
𝑉𝐿𝑖𝑛𝑒𝑆𝑒𝑙𝑒𝑐𝑡𝑖𝑜𝑛_𝐴𝐶 =
Application Note
45
(1.52 ×
9 × 109 + 58.3 × 103
) + 24.5
58.3 × 103
= 184𝑉
√2
9 × 109 + 58.3 × 103
)
58.3 × 103
= 167𝑉
√2
Revision 1.0
2017-03-10
5th generation quasi-resonant design guide
DG-design guide-ICE5QSAG and ICE5QRxxxxAx
References
9
References
[1]
ICE5QSAG datasheet, Infineon Technologies AG
[2]
ICE5QRxxxxAx datasheet, Infineon Technologies AG
[3]
AN-201609_PL83_024-50W 12V 5V SMPS Demo Board with ICE5QSAG
[4]
AN-201609_PL83_025-16W 12V 5V SMPS Demo Board with ICE5QR4780AZ
[5]
FlyCal_QR Q5 CoolSET_V1.0
Revision history
Major changes since the last revision
Page or reference
--
Application Note
Description of change
First release.
46
Revision 1.0
2017-03-10
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Edition 2017-03-10
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©AN_201609_PL83_026owners.
2017 Infineon Technologies AG.
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