Download Means for minmizing pulse reflections in linear delay lines loaded

Dec. 13, 1955
R. J. SLUTZ
2,727,143
MEANS FOR MINIMIZING PULSE REFLECTIONS IN LINEAR
DELAY LINES LOADED WITH A NONLINEAR LOAD
Filed Aug. 30, 1951
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Dec. 13. 1955
R. J. SLUTZ
2,727,143
MEANS FOR MINIMIZING PULSE REFLECTIONS IN LINEAR
DELAY LINES LOADED WITH A NONLINEAR LOAD
Filed Aug. 30, 1951
2 Sheets-Sheet 2
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2,727,143
United States Patent 0
Patented Dec. 13,: 1955
2
1
2,727,143
a certain magnitude will be attenuated or shorted to a
much greater degree than pulses below that magnitude, so
that excess pulse voltage above that needed for circuit
utilization Will be rendered ineffective to produce harm
MEANS FOR MINIMIZING PULSE REFLECTIONS
1N LINEAR DELAY LINES LOADED WITH A
NONLINEAR LOAD
ful re?ections.
Ralph J. Slutz, Kensington, Md.,'assignor to the United
the termination of a delay line, said shunt being returned
States of America as represented by the Secretary of
Commerce
,’
It is a speci?c object to provide a nonlinear shunt for
to a low voltage source to prevent the production of re
?ected pulses of su?iciently high amplitude to cause
trouble
in the utilization circuits.
10
Application August so, 1951, Serial Nb. 244,447
Another object is to provide a termination'for a delay
4 Claims. (01. 250-27)
line transmitting pulses which presents to any excess
voltage of such pulses an apparent impedance not greater
(Granted under Title 35,U. S. Code (1952), sec. 266)
than the characteristic impedance of the utilization line
The invention described herein may be manufactured 15 whereby re?ected pulses will be either absent or else of
opposite sign from the incident pulses.
and used by or for the Government of the United States
for governmental purposes without the payment to me of
any royalty thereon in accordance with the provisions of
the Act of March 3, 1883, as amended (45 Stat. 467; 35
U. S. C. 45).
-
This invention is concerned with minimizingpulse re
?ections in linear delay lines loaded with a nonlinear
load. This is a serious problem in the operation of elec
tronic digital computers of the type exempli?ed by the
The speci?c nature of the invention, as well as other
objects and advantages thereof, will clearly appear from
a description of a preferred embodiment, as shown in the
accompanying drawings in which:
Figure 1 is a schematic circuit diagram of a basic gate
circuit.
Figure 2 is a simpli?ed diagram showing those com
ponents of the circuit of Figure l which are essential to a
computer known as SEAC (Standards Eastern Automatic 25 consideration of the invention.
Figure 2a shows graphically the changes with respect to
Computer) which is in operation at the National Bureau
time which occur in the incident and re?ected voltage
of Standards.
and current in the circuit of Figure 2.
SEAC uses time-sequenced electronic pulses of approxi
Figure 3a, b, c, and d represent respectively the essential
mately 50 percent duty factor, i. e., one-half microsecond
in duration and spaced approximately one-half micro 30 load component of the basic circuit of Figure 1 and vari
ous modi?cations applied thereto in accordance with my
second apart to represent digits and orders. Such pulses
invention.
are electrically switched through various circuits for the
Figure 4a, b, c, and a‘ represent graphically the im
purpose of performing desired computations at very high
pedance conditions in Figure 3a, b, c, and a’, respectively.
speed. Absolute accuracy in transmitting the pulses is,
Referring to Figure 1, an incoming pulse on the pri-.
of course, essential to the proper operation of such a de 35
mary of transformer 1 is emitted from the secondary and
vice. Synchronization of pulses is maintained by using a
suitably delayed by arti?cial delay line 2, which may be
so-called “clock pulse” generator as a pulse source and
of any known type, and has the characteristics shown in
referring all pulses in the system to said source. The
the drawing, the particular value of impedance being
pulses are often delayed somewhat in transition through a
utilization circuit and in order to synchronize them with 40 selected, together with the impedance of the associated
elements at the termination of the line, to match the
the next available clock pulse from the pulse generator,
characteristic impedance of the line as a whole, being, in
they may be deliberately delayed still further by the use
the typical example selected, 1600 ohms. The incoming
of an arti?cial delay line of suitable electrical length so
pulse (of approximately one-half microsecond duration
that the pulse will arrive at the desired point in the correct
synchronization. In other cases delay lines are used to 45 and 50 percent duty factor in SEAC) is delayed approxi
mately 0.64 microsecond in the example shown, this being
insure the synchronous arrival at a common point of
required for the particular circuit shown in order to in
pulses from different parts of SEAC which have fallen
sure synchronization of the pulses from source 1 with
out of synchronization owing to the characteristics of the
other pulses from other sources.
circuits through which they have passed. For these and
The action of the circuit shown in Figure 1 will now
other reasons, it is necessary to use electric delay lines in
be described brie?y in order to show the manner of
many places in the computer.
application of the invention to the SEAC, since this is
The actual electric switching operations in SEAC are
a typical SEAC gate structure. Normally the grid of
performed by germanium diodes. These or any similar
tube 3 is maintained at —5 volts and there is no signal
types of diodes are nonlinear devices; that is, their resist
ance is not constant but is a function of the amplitude 55 output from the tube. To produce a signal it is desired
that the grid be raised to +2 volts at a rapid rate (in
and direction of the applied voltage. These diodes, to
practice, the rate of 100 volts per microsecond), kept
gether with their associated circuit elements, present a
close to +2 volts for somewhat less than one-half micro
nonlinear load termination to the delay lines where these
second and dropped to —5 volts at the same rate of
are used, and it has been found that such termination
100 volts per microsecond. This produces an ampli?ed
presents a serious re?ection problem in some cases, as
60 output from tube 3 which results in a pulse output from
will be shown more fully below. The production of a
the secondary of transformer 4 similar to the original
re?ected pulse travelling back along the delay line may
input pulse and with at least the same power as the
adversely affect some subsequent pulses in the same cir
original input pulse from transformer 1. To provide
cnit, since the re?ected pulse may arrive at the pulse
source in the correct phase to in effect cancel out a subse
the necessary safety factor, the voltage input from trans
by simple readily available means.
grid is kept at —5 volts by “bumper” 6, which is a
circuit arrangement whereby voltage pulses of more than
of the grid to drop below -5 results in current ?ow
quent pulse and thus produce an error in the computation. 65 former 1 is made considerably higher than +2 volts.
However, the input to the grid of tube 3 is kept to a
This has in fact been found to occur in some parts of
maximum of +2 volts by the action of the circuit which
SEAC. It is a primary object of this invention to elimi
will now be described. The potential of the unpulsed
nate the possibility of errors occurring from this cause
More speci?cally, it is a further object to provide a 70 diode connected to a —-5 volt source.
Any tendency
2,727,143
3
4
through diode 6 to keep the grid up to at least —5
volts. If the grid potential rises above —-5 volts the
anode is considerably higher, and current will ?ow as
diode has no effect, as its cathode is now higher in
potential than its anode and no current can ?ow through
diode 8 ceases to conduct (at time T3) from which point
the increase in current corresponds only to the increase
in E1, i. e., El/Zo, which is a much slower rate of in
crease than during the interval T2 to T3. During the
time interval T2 to T3 the re?ected voltage Er is dropping
as E1 is rising, since this is characteristic of short-circuited
in a short circuit until it reaches the level at which
it. ' Resistor 7 is Connected to a -—65 volt source and
tends to pull the grid voltage down, but because of
the above action the grid is maintained at —5 volts.
Another diode, 8, is connected to a —-8 volt source.
behavior. At time T3, the anode again appears more or
Between diode 8 and resistor 7 is diode 9, which nor
mally does not conduct because its anode is at a lower 10 less like an open circuit, i. e., the impedance now presented
potential (—8 volts) than its cathode (—5 volts). Re
to the pulse wave front is the relatively high impedance of
sistor 11 is connected to a +62 volt source.
resistors 11 and 13 in parallel. So'far as the gate is con
cerned, soon after T3 the necessary voltage level for
Current
normally ?ows from resistor 11 and diode 8 to resistor
13 which is returned to —-65 volts. As 13 is of lower
its proper operation is reached. However, the pulse volt
resistance than 11, it tends to pull down the voltage 15 age continues to rise to its full value which is almost
always higher than the minimum required for proper
at diode 42 to below —8 volts. The cathode of diode
gate operation. This excess voltage is the major cause
42 is, however, kept at ~8 volts by current supplied
of re?ection trouble, because now E0 rises at twice the
through diode 8. The source (secondary of transformer
rate of Bi as E1- again builds up. The re?ected positive
1) is returned to —l0 volts so that normally no cur
rent ?ows through diode 14, since its cathode is now 20 voltage wave Er may, in returning to its point of origin
through the line, arrive in the correct phase to cause
raised above its anode. However, an incoming pulse
trouble. The characteristics of the gate circuit are such
raises the potential of the anode of diode 14 to above
that negative re?ections cause little di?iculty, except that
greater power from the tube of the preceding stage will
be required to overcome them in impressing subsequent
pulses on the line, and there is usually su?icient power
output available. Furthermore, examination of Figure
2a will show that the re?ected negative voltage pulse Er
current now ?ows from resistor 11 through diode 9 and
tends to be of smaller magnitude than the positive pulse,
resistor 7. However, the rise is limited to +2 volts by
diode 16 which is connected to a +2 volt source and 30 since it can occur only during the time interval T2 to T3
and so does not have much time to build up to a high
begins to draw current to keep the grid at the +2 volt
level whenever the grid voltage tends to rise above that
negative value, while the positive pulse may build up
to a fairly high value if the excess pulse voltage is suf
point. Thus the grid voltage can ?uctuate only between
?ciently high.
—5 volts and +2 volts regardless of the voltage of the
incoming pulse. The above-described circuit is typical
In a practical computer such as SEAC, the actual cir
cuits tend to be rather complex, and the action is not
of the gate circuitry of SEAC and is per se'no part
always easy to follow. Perfect accuracy of pulse trans
of the present invention. Similar circuits working on
mission is, of course, required; i. e., not a single pulse
the same principle are shown and described in the co
may be lost or improperly transmitted without entirely
pending claims of Ralph I. Slutz, Serial No. 193,696,
?led November 2, 1950, of William L. Martin et 2.1., 40 invalidating the computation, and with pulses at the rate
of a million per second, in a run of some hours duration,
Serial No. 205,l64, ?led January 9, 1951 and of Robert
which often occurs, the number of possibilities of error
D. Elbourn and Ralph J. Slutz, Serial No. 244,446, ?led
is tremendous, yet the circuitry must be such that even
August 30, 1951, now Patent No. 2,712,065, issued June
the most remotely improbable combination of random
28, 1955.
or transient effects is rendered innocuous. The above
In order to explain the problem with whose solution
described re?ection effect does not in practice give diffi
this invention is concerned, the action of a part only
+2 volts, and the resulting conduction raises the cathode
of diode 42 above its anode potential. Since current can
no longer ?ow from resistor 11 through resistor 13, the
anode of 42 rises toward +62 volts. Diode 8 ceases
to conduct because its cathode rises above -—8 volts and
culty often, nor is it possible in some of the circuit com
of the circuit shown in Figure 1 will now be considered.
binations used, but the circuit combinations themselves
Referring to Figures 2 and 2a, the characteristic im
are electronically controlled by certain pulses acting as
pedance at the line will be considered in its relation
to the incident pulse front, and may be expressed as
50 coded orders rather than as numbers, and the circuits
Z0
are therefore changed and rearranged at the same high
speeds as those at which the computations are performed.
E.;_ E,
‘If
Under these circumstances it was found that errors can
occasionally occur, and the provision of a way to success
where
E-;=incident pulse voltage
lir=iricident pulse‘ current
E}="re?ected ‘pulse voltage
lr=re?ected pulse current
Furthermore,
E0==Ei+Er
55 fully correct the dif?culty was attained by the means de
scribed below.
where Eo=voltage at anode of diode 14.
When the pulse front arrives at the anode of diode
14 (Figure 2), this point at ?rst behaves like an open
circuit, since the diode prevents passage of current until 65
its anode voltage reaches the unlatching level of the diode,
'
According to the present invention the possibility of
delayed re?ections through lines of su?icient electrical
length to produce harmful phase relationships is mini‘
60 mized, or in practice totally eliminated, by providing an
additional terminal load of such character that it does
not appreciably affect the pulse action in the useful volt
age range of the pulse, but does provide, in all higher
voltage ranges, an apparent terminal impedance at least
equal to, or below, the characteristic impedance of the
line. At the characteristic impedance there is, of course,
no re?ection, and at‘ a discontinuity representing a lower
i. e., the level at which the diode begins to conduct.
impedance than the characteristic impedance, the re?ected
Therefore, from time T1 to T2 (Figure 2a) E0 r'ises'at
voltage pulse is opposite in sign from the incident pulse
twice the rate of E1 because of the addition of Er, as
in any open-ended line re?ecting a wave front. After 70 and therefore does no harm, as above pointed.
diode 14 begins to conduct, the line at this point behaves
This new termination is accomplished by connecting
like a short circuit from time T2 until the difference in
the current in resistor 13 and resistor 11 is furnished
entirely by the source, as at time T3. This is so be
to the load end of the line, as shown in Figure 3b, a
diode 21 returned to a voltage source of a value in the
order of the maximum grid voltage—in this case +2
cause‘ the cathode of diode 14 is at -—8 volts and the 75 volts. In practice this return voltage may be slightly
2,727,143
higher, for example +4 volts, to provide a safety factor
of voltage to take care of voltage drops further along
the line toward the grid. The curves shown in Figure 4
show the effective impedance changes which occur in the
corresponding circuits of Figure 3 as the voltage in
6
nonlinear impedance element whose impedance changes
abruptly at approximately said de?nite voltage level said
shunt being returned to a vintage source of a value sub
creases. The dotted line Z0 represents the characteristic
impedance of the line. Because of the nonlinear load
stantially the value of said de?nite voltage level.
2. In an electronic system for transmitting and utiliz
ing discrete electric pulses of very short duration at a
very high repetition rate which comprises means for
ing of the line by the gate element described, the im
producing such pulses, a delay line for retarding pulses
pedance in the range —l0 volts to +2 volts varies in
by a predetermined amount, a nonlinear pulse utilization
nonlinear fashion as shown. The curve shown in Figure 10 circuit connected to said delay line, said circuit having
4a represents the action in the circuit of Figures 1 and 2.
means presenting an impedance not higher than the char
At voltages above the maximum grid voltage of +2 volts
acteristic impedance of said line to voltages of a certain
the effective impedance is higher than the characteristic
utilized value and a much higher impedance to voltages
impedance, and therefore an undesirable positive re?ected
in excess of said value whereby harmful re?ections may
voltage occurs. Figure 4b shows impedance conditions
occur because of said excess voltage value, the improve
for the circuit of Figure 312. At the +2-volt grid level
ment which comprises an additional nonlinear load for
the load impedance drops suddenly because of the shunt
ing action of diode 21 at voltages above this level, and
thereafter is at all times less than the characteristic im
pedance of the line, so that the undesirable positive pulse 20
re?ection does not occur.
An alternative arrangement is shown in Figure 3c,
which is very similar to Figure 3b except that a resist~
ance R0 is in series with the diode 21’. This resistor is
preferably of such value that the parallel combination
of it and the resistor 13 to the —65-volt supply is ap
proximately equal to the characteristic impedance of the
line. The corresponding impedance curve is shown in
Figure 4c. This arrangement nicely absorbs the excess
voltage from a single source, but is not so effective in
the case of a gate having two inputs as shown in Figure
3d, if input A produces pulses of considerably greater
amplitude than input B, in which case a large re?ection
will be sent back toward source B if two pulses from
both sources arrive simultaneously, with the undesirable
effect previously noted. The apparent impedance to a
pulse coming in from a source B under these conditions
is represented in Figure 4d. It will be seen that the com
posite impedance characteristic beyond +2 volts is higher
than the characteristic impedance Z0 of the line. The
arrangement of Figure 30 cannot therefore be used under
these conditions, but should be used only where there is
a single gate of the type shown in Figure 30. For the
dual input of Figure 3d the arrangement of Figure 3b
should be used, i. e., a diode returned to +2 volts without
the resistor R0.
By the provision of an additional nonlinear load of the
type described, it has proved possible in SEAC to entirely
eliminate harmful re?ection effects. SEAC, in which
this invention is employed, has been able to operate on
lengthy problems, involving many hours of continuous
running, at a pulse rate of a megacycle, without a single
erorr in pulse transmission. The present invention has
been found to be a complete solution to the troublesome
said system connected to a voltage source of said utilized
value and so oriented as to present a high impedance
to said pulses at voltages below said utilization value
but a low impedance to said pulses at voltages above said
utilization value, whereby said excess voltage is shunted
and prevented from producing said harmful re?ections.
3. The invention as recited in claim 2 and a resistance
in series with said additional nonlinear load, said re
sistance being of such value that the total impedance
presented to said pulses at voltages above said utiliza
tion value is in the region of the characteristic impedance
of the line.
,
4. In a gating circuit for an electronic digital computer,
said gating circuit including a pulse transformer having
a primary and a secondary winding returned to a low
reference voltage, a delay line connected to the high
side of said secondary winding for retarding pulses pro
duced in said secondary by a predetermined amount,
a nonlinear pulse combining and amplifying circuit con
nected to said delay line, said last circuit including re
sistors and diode elements oriented and arranged to
effectively transmit said pulses within a predetermined
voltage range, said last circuit thereby presenting an
impedance not higher than the characteristic impedance
of said line to voltage pulses within said predetermined
voltage range, and a higher impedance to voltages in
excess of said value whereby such voltages may produce
harmful re?ections, means for producing in said sec
ondary, pulses of higher voltage than the upper level
of said predetermined voltage range usable by said pulse
combining and amplifying circuit, and means for pre
venting harmful re?ections due to such excess voltage,
said last means comprising an additional nonlinear ele
ment at the utilization end of said delay line, said non
linear element connected to a voltage source substan
tially at the upper level of said predetermined voltage
range, and being so oriented as to present a high im
pedance to said pulses at voltages below said level but
problem of harmful reflections despite the complex action 55 a low impedance to said pulses at voltages above said
of the normal nonlinear load coupled to a delay line.
utilization value whereby said excess voltage is shunted
It will be apparent that the embodiments shown are
and prevented from producing said harmful re?ections.
only exemplary and that various modi?cations can be
References Cited in the ?le of this patent
made within the scope of my invention as de?ned in the
appended claims.
UNITED STATES PATENTS
60
Iclaim:
1. In a pulse utilization system comprising a delay line
loaded with nonlinear pulse utilization means adapted for
operation at a de?nite voltage level, means for prevent
ing harmful re?ections which comprises a shunt con 65
nected across the load end of said delay line between
said delay line and said load, said shunt comprising a
2,085,418
2,104,336
2,262,468
2,438,367
2,525,454
Crosby ______________ __ June 29,
Tuttle _______________ __ Jan. 4,
Percival _____________ .__ Nov. 11,
Keister _____________ __ Mar. 23,
Lord ________________ __ Oct. 10,
1937
1938
1941
1948
1950
2,557,122
Leiphart ____________ __ June 19, 1951