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UNIVERSITY OF CALIFORNIA
College of Engineering
Department of Electrical Engineering and Computer Sciences
Last modified on September 25, 2005 by Ke Lu ([email protected])
Dejan Markovic
Homework #3
Due Thursday, September 22nd
EECS 141
Problem #1
Consider the inverter circuit shown in Figure 2 with an ideal square-wave input. Assume that short-channel
effects are negligible – meaning VDSAT >> VDS, VGS-VT.
VDD!
VDD!
VDD! = 2.5V
Vt = 0.5V
LM1, M2 = 0.25um
WM1 = 1.0 um
WM2 = 2.0 um
LS = 0.25 um
kn = 100uA/V2
λ = 0 V-1
γ = 0.2 V1/2
φF = -0.3V
Use Table 3.5 in the
textbook to find
capacitances.
GND!
GND!
Figure 2
Note: A node name followed by a “!” (i.e. VDD! and GND!) denotes a global node in a netlist.
Using the information above and references in the text, determine the following:
a)
Find VOH and VOL. Hint: Both the load and driver transistors are NMOS, so don’t say 2.5V and 0V!
Finding Voh: Set Vin=0
Only M1 is on and it is pulling up against the resistor. Vout (Voh), will be somewhere between Vdd – Vt
(because we are using an NMOS to pull up) and ground. Find the current running through M1 and
equate with current through resistor; solve for Vout (Voh).
Remember, Vt is not equal to Vto for M1 since there is back body biasing with Vsb = Voh (the bulk is
grounded)
Vt = 0.5 + 0.2*( sqrt(0.6 + Voh) – sqrt(0.6))
M1 is in saturation (Vgt always less than Vds) so current is:
Im1 = 100u/2 * 1/0.25 * (2.5 – Voh – Vt)2
Current through the resistor is
Iload = Voh/100K
Set Im1 = Iload and substitute in for Vt. Only unknown is Voh. Using your favorite symbolic equation
solver, we arrive at
Voh = 1.5787 V
Finding Vol: Set Vin=2.5V
When IN is high, there both M2 and the resistor is pulling against M1. Repeat the same process for Voh
except there is now 3 current branches.
Im1 = Im2 + Iload
Iml and Iload is the same as before except we use Vol instead of Voh. For Im2, we make the assumption
that the device will be in triode (reasonable since we expect the output to be low meaning Vds (Vol) to be
small compared to Vgt). We will check this assumption at the end.
Im2 = 100u * 2/0.25 * ((2.5 - 0 - 0.5) * Vol – Voh2/2)
This time, only unknown is Vol so again using any equation solver (or you can guess and iterate), you
arrive at
Vol = 0.44 V
Since Vol < Vt, M2 stays off when Vin = Vol; therefore, Voh is the same.
.
b) Calculate tpLH and tpHL. This will require you to find a Req and Ceq in each case. There’s no explicit
load so we’ll consider the self loading (only internal capacitances) that is seen at the output (there
should be two components).
We need to find Req and Ceq, which are different on the H→L and L→H transitions. You can do
a complicated integral, but for our first order approximations, you can find the resistance at the
start and end of a transition and average them. Remember the end point is the switching
threshold, which is Vm ~ (Voh – Vol)/2 = 1.
⇒ Find ReqHL:
How do we calculate the equivalent resistances? ⇒R = V/I
RM1/M2:
For M1,
VDS @ beginning = VDD -VOH = .92 V
IDS @ beginning = ½ k’ (W/L)1(VDD-VOH-Vt)2 =15.6uA, notice that due to body effect, Vt>Vt0
VDS @ end = 1V
IDS @ end = ½ k’ (W/L)1(VDD-Vm-Vt)2 = 392 uA
For M2,
VDS @ beginning = VOH = 1.5787 V
IDS @ beginning = k’(W/L)2[(VOH-Vt)VOH-VOH2/2] = 367 uA
VDS @ end = 1 V
IDS @ end = k’(W/L)2[(VOH-Vt)Vm-Vm2/2] = 464 uA
IR @ beginning = VOH/100k = 15.8 uA
IR @ end = Vm/100k = 10 uA
ReqHL @ beginning = [VOH / (IDS,M2- IDS,M1 + IR)]@beginning = 4.3 KOhm
ReqHL @ end = [Vm/ (IDS,M2- IDS,M1 + IR)]@end = 12 KOhm
ReqHL = (ReqHL@beginning+ ReqHL@end )/2= 8.15 KOhm
⇒ Find ReqLH
Thankfully, tPLH is easier to calculate because RM2 = ∞ at the start and end of the transition because VGS,
< Vt, meaning it is always off. What are the start and end points of the transition? ⇒VOL and Vm
M2
RM1:
For M1,
VDS @ beginning = VDD -VOL = 2.06 V
IDS @ beginning = ½ k’ (W/L)1 (VDD-VOL-Vt)2 =456 uA, notice that due to body effect, Vt>Vt0
VDS @ end = 1V
IDS @ end = ½ k’ (W/L)1 (VDD-VOL-Vt)2 = 196.12 uA
IR @ beginning = Vol/100k = 4.4 uA
IR @ end = Vm/100k = 10 uA At both points the resistor current is negligible compared to the current in
M1.
ReqLH @ beginning = [VDD - VOL/ IDS,M1]@beginning = 4.5 KOhm
ReqLH @ end = [VDD - Vm / IDS,M1]@end = 7.6 KOhm
ReqLH = (ReqLH@beginning+ ReqLH@end )/2= 6.05 KOhm
Ceq:
There are two components at work for the self-loading: the diffusions and the overlap capacitances. The
diffusion capacitances are the capacitors between the output and bulk of M1 (Csb1) and output and bulk
of M2 (Cdb2):
Cdiff = Keqn*Cj * L * W + Keqswn*Cjsw * (2 * L + W)
It’s good to calculate the exact value of Keq in each case; however let Keq=1 would give us fairly
accurate results. This will overestimate the total value of Cdb by a little bit but still ok, especially
for the usual case that there is an external wire/load capacitance at the output and then this error
becomes negligible. (Anyway, it’s ok if you did calculate Keq).
Using Cj = 2 fF/um2 and Cjsw = 0.28 fF/um from Table 3.5, we can easily figure out the self loading:
M1: Csb1 = 1*2f * 0.25 * 1 + 1*0.28f * (2 *0 .25 + 1) = 0.92 fF
M2: Cdb2 = 1*2f * 0.25 * 2 + 1*0.28f * (2 * 0.25 + 2) = 1.7 fF
The overlap capacitances come from the Gate to Channel capacitors seen at the output. For M1, the
device is always saturated so total Cgs = Cgs0 + Cgcs (saturation region):
Cgs1 = (Co * W) + (2/3 * Cox * W * L) = (0.31f * 1) + (2/3 * 6f * 1 * 0.25) = 1.31 fF
This does not get miller multiplied since the input to M1 does not change.
To calculate the Cgd2, the approach is the same as Cgs1 except M2 is in different regions based on a lowhigh or a high-low transition. If output swings high-low, the device is always in triode whereas when
the output swings low-high, the device is in cutoff. Therefore, there will be a different equivalent
capacitance associated with each transition much like the resistances.
(high-low)
Cgd2 = (Co * W) + (1/2*Cox * W * L) = (0.31f * 2) + (1/2 * 6f * 2 * 0.25) = 2.12 fF
(low-high)
C gd2 = (Co * W) = (0.31f * 2) = 0.62 fF
This capacitor does get miller multiplied because the input and output are toggling against each other.
Therefore:
Ceq = Csb1 + Cdb2 + Cgs1 + 2*Cgd2
(high-low) Ceq = 8.17 fF
(low-high) Ceq = 5.17 fF
Notes: The Miller effect factor of 2 above is just an estimated value since the output voltage swing
is not rail-rail. You can get a better estimation by changing this factor to 1+(Voh-Vol)/2.5 = 1.35
DELAY
To calculate both tpLH and tpHL, we cannot simply use the equation t = 0.69ReqCeq because that would
imply we were swinging from a rail to half the supply voltage. We’ll have to actually use the
exponential to find the constant * RC to find this delay.
In the high-low case, the output travels from VOH to Vm; low to high case, output travels from Vol to
Vm. The decaying exponentials are:
(high-low) V = 0.44 + 1.14 * exp(-t/RC)
(low-high) V = 1.58 – 1.14 * exp(-t/RC)
Subbing in V = VM, and solving for t, we arrive at
tHL = 47 ps
tLH = 31 ps
c)
Assuming a normal pmos/nmos inverter is the load presented at the output, what other capacitances
would we have to account for in the Ceq calculation in addition to those you used for part b)?
The extra capacitances would be the gate-drain capacitances of the gates of the following inverters
(might have to take into account the Miller effect), the gate-source capacitances as well as the
capacitance of the wire that connects the two gates.
d) Find the static power dissipation for:
Assuming no leakage current,
i) Vin = 0.0V
ii) Vin = 2.5V
i. When Vin = 0.0V, M2 is off. Current running through circuit = current through resistor. We know Vout
= Voh so I = 15.8 uA
P = IV = 15.8u * 2.5V = 39.5 uW
ii. M1 and M2 are both on. Use current through M1 from above when the input is 2.5V so Vout = Vol. I
= 512.96 uA.
P = IV = 456u * 2.5V = 1.14 mW
Problem #2
a)
It is always good to get a feel for design rules in a layout editor. Fire up Cadence with the 0.25um
technology file used in the lab session. Place a minimum sized NMOS transistor and examine the
dimensions. The layers are listed and shown below in Figure 3a. Determine and list the following:
a. Minimum Transistor Length
b. Minimum Transistor Width
c. Minimum Source/Drain Area
d. Minimum Source/Drain Perimeter
Please list the design rules you come across that lead to your results.
poly
nfet
ct
ndif
Figure 3a
Rules are:
i)
Poly minimum width = 0.24um
ii)
Minimum active width = 0.36um
iii)
Minimum contact size = 0.24um*0.24um
iv)
Minimum spacing from contact to gate = 0.24um
v)
Active enclosure of contact = 0.12um
The figure is actually misleading, because the actual minimal transistor is bone shaped.
Use these values
a. L = 0.24um
b. W = 0.36um (0.48um ok – just add or subtract a 0.12um*0.12um diffusion area at the nextto-the-gate corner of each of the diffusion regions (Source/Drain), this also means add/subtract a
diffusion area under the poly (gate) in order to form a channel).
c. Ldrain = 0.24um+0.24um+012um = 0.6um
AD=AS= 0.48 * 0.6um – 0.12um*0.12um = 0.2736um2 (0.288 um2 ok)
d. PD=PS =0.6um*2+0.48um+0.12um = 1.8um (1.68um ok)
b) We desire a minimum sized CMOS inverter with a symmetrical VTC (VM=VDD/2) in the 0.25um
technology. Calculate the following for the pull-up PMOS transistor in the design.
a. Minimum Transistor Length
b. Minimum Transistor Width
c. Minimum Source/Drain Area
d. Minimum Source/Drain Perimeter
Assume the following:
VDD = 2.5V, VM = 1.25V, and refer to Table 3.2 in the textbook.
We will use equation 5.5 from the text book:
kn'VDSAT , n(VM − Vt , n − 12 VDSAT , n)
(W / L) p
=
(W / L) n kp 'VDSAT , p (VDD − VM + Vt , p + 12 VDSAT , p )
The gate lengths will be identical and thus we can calculate Wp = 1.2544 µm,
AD = 0.3809 µm2, and PD = 2.4544 µm.
c)
Using the same minimum size inverter from part b), determine the input capacitance (i.e. the load it
presents when driven). Please calculate the capacitance during a transition. From these, determine the
total load capacitance that the inverter presents.
*Hint: Consider the Miller effect
You have three capacitances per transistor to consider on an inverter for input capacitance, gate to bulk,
gate to source and gate to drain. Cox = 6.0fF/µm2
Again, we are using Keq =1. (Ok if you calculate Keq)
From Table 3-4 Cg=Cgc+Cgs+Cgd
PMOS:
Cgc
saturated = 2/3 (CoxLpWp) = 1.204 fF
triode = CoxLpWp = 1.806 fF
cutoff = CoxLpWp = 1.806 fF
Cgd
= COWP = 0.34 fF
Cgs
= COWP = 0.34 fF
NMOS:
Cgc
Cgd
Cgs
saturated = 2/3 (CoxLnWn) = 0.346 fF
triode = CoxLnWn = 0.518 fF
cutoff = CoxLnWn = 0.518 fF
= COWn = 0.112 fF
= COWn = 0.112 fF
Let’s use Cgc=1.806 fF for PMOS and Cgc=0.518 fF for NMOS so that we will get an upper bound
(worst-case) value of Cin.
If switching Cin = (Cgcp + Cgcn) + (Cgsp + Cgsn) + 2 (Cgdp + Cgdn) = 3.68 fF
The factor of 2 is due to miller effect
NOTE!!!!!!
The Miller effect is included in the calculations purely because the inverter in question is
unloaded by anything external. THIS WILL RARELY OCCUR IN REALITY!!!! Only in this
very special unloaded case does an inverter have this Miller multiplication seen as part of it’s
input capacitance.
d) Using the g25 model provided in ‘~ee141/MODELS/g25.mod’, please verify the accuracy of your
results in part c by determining the total input capacitance in a high-low and a low-high transition with
HSPICE and comparing with your total capacitance in part c. Turn in your HSPICE input deck.
You'll notice there are five corners, TT, FF, SS, FS, and SF. These represent the different variation
extremes we can expect due to process variations. For example, TT stands for NMOS: typical, PMOS:
typical. FS stands for NMOS: fast, PMOS: slow etc. For this homework, please use the TT model.
To use these models, include the following in your HSPICE deck:
.lib '~ee141/MODELS/g25.mod' TT
Hw3 Prob3d
.lib'g25.mod' TT
.param vddp=2.5
.param ln_min=0.24u
.param lp_min=0.24u
.param l_drain=0.6
.param arean(w)='(w*l_drain*1p)'
.param areap(w)='(w*l_drain*1p)'
.param perin(w)='((w*1u)+(l_drain*2u))'
.param perip(w)='((w*1u)+(l_drain*2u))'
VDD vdd 0 'vddp'
IIN 0 in 1u
M1 out in vdd vdd pmos l='lp_min' w=1.204u
M2 out in 0 0 nmos l='ln_min' w=0.36u
.ic v(in)=0
.meas t1 trig v(in) val=0.0001 cross=1 targ v(in) val=1.25 cross=1
.meas t2 trig v(in) val=1.25 cross=1 targ v(in) val=2.5 cross=1
.options post=2 nomod
.op
.tran 0.1ns 10ns
.end
e)
Determine VIH, VIL , NMH, and NML.
*Hint: Refer to Eq’s 5.3 and 5.10 in the textbook for r and g
First find r using eqn. 5.3 in the book and then g using eqn. 5.10. Remember to account for the size
difference by applying direct ratio.
r = 1.443
g = 4.564
VM = VDD/2 = 1.25V
Then use equations 5.7 to solve:
VIH = VM + (2.5-VM)/g = 1.524V
NMH = VDD – VIH = 0.976 V
VIL = VM – VM/g = 0.976V
NML = VIL = 0.976V
Problem #3
a)
Figure 4a depicts the Id – VOUT curve of a typical NMOS transistor
Figure 4b depicts the Id – VOUT curve of a typical PMOS transistor
Assume we use these FETs to create a CMOS inverter. Using this family of curves, graph the VTC,
and calculate VM, VIL, and VIH.
2.5
2
Vout (V)
1.5
1
0.5
0
0
0.5
1
1.5
2
2.5
Vin (V)
VM = 1.25V
g = (2.35-0.15)/0.5 = 4.4
VIL = VM - (VOH-VM)/g = 0.966V
VIH = VM+ VM/g = 1.534V
b) The curves above were generated using the TT corner in Hspice. Intuitively explain how using the FS
and SF corners will affect the above I – V curves and the VTC.
FS: The VTC will shift to the left. The NMOS is stronger and will pull the output voltage down earlier.
SF: The VTC will shift to the right. The NMOS is weaker and will pull the output voltage down later.
Problem #4
The inverter below, operates with VDD=0.4V and is composed of |Vt| = 0.5V devices. The devices have identical
I0 and n but the channel modulation constants are different and are those given in table 3.2
A
Calculate the switching threshold (VM) of this inverter.
Both devices are in the subthreshold region…assuming n = 1.5 and kT/q = 26mV
I 0e
VGS
nφT
V
− DS

1 − e φT


VM
V
− M

e nφT  1 − e φT


VGS

 (1 + λnVDS ) = I 0 e nφT


VDD −VM

nφT
1
λ
V
e
+
=
(
n M )


B
Calculate VIL and VIH of the inverter.

 (1 + λ pVDS )


V −V
− DD M

φT
1
e
−



Solving this equation using a math solver:
VM = 0.24V
V
− DS

1 − e φT



 (1 + λ p (VDD − VM ) )


VIH = VM – VM/g VIL = VM + (VDD-VM)/g
From equation 5.12:

 1   VDD
g = −    e 2φT − 1
 n 

g = -1460
VIH = 0.24 – 0.24/(-1460) = 0.2402
VIL = VM + (VDD-VM)/g = 0.2399