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UNIVERSITY OF CALIFORNIA
College of Engineering
Department of Electrical Engineering and Computer Sciences
Last modified on September 22, 2002 by Henry Lam ([email protected])
Borivoje Nikolic
Homework #3: CMOS Inverters and Design Rules
EECS 141
Solutions
Problem #1
Consider the inverter circuit shown in Figure 1a with an ideal square-wave input. Assume that short-channel
effects are negligible – meaning VDSAT >> VDS, VGS-VT.
!VDD = 2.5V
Vt = 0.5V
LM1, M2 = 0.25um
WM1 = 2.0 um
WM2 = 1.0 um
LS = 0.25 um
(Ldiff = LS for this
homework when
calculating
capacitance.)
kn = 100uA/V2
 = 0 V-1
 = 0.2 V1/2
F = -0.3V
Use Table 3.5 to find
capacitances.
Figure 1a
(For your own edification, a node preceded by a “!” (i.e. !VDD and !GND) denotes a global node in a netlist.)
Using the information above and references in the text, determine the following:
a)
Find Voh and Vol. Clue: both the load and driver transistors are NMOS, so don’t say 2.5V and 0V!
Voh:
Only M1 is on and it is pulling up against the resistor. V out (Voh), will be somewhere between
Vdd – Vt (because we are using an nmos to pull up) and ground. Find the current running through M1
and equate with current through resistor; solve for Vout (Voh).
Remember, Vt != Vto for M1 since there is back body biasing with Vsb = Voh (the bulk is grounded)
Vt = .5 + .2*( sqrt(.6 + Voh) – sqrt(.6)) (refer to G.U.M equation)
M1 is in saturation (Vgt always less than Vds) so current is:
Im1 = 100u/2 * 2/.25 * (2.5 – Voh – Vt)2
Current through the resistor is
Iload = Voh/100K
Set Im1 = Iload and substitute in for Vt. Only unknown is Voh. Using your favorite symbolic equation
solver, we arrive at
Voh = 1.65 V
Vol:
When IN is high, there both M2 and the resistor is pulling against M1. Repeat the same process for Voh
except there is now 3 current branches.
Im1 = Im2 + Iload
Iml and Iload is the same as before except we use Vol instead of Voh. For Im2, we make the assumption
that the device will be in triode (reasonable since we expect the output to be low meaning V ds (Vol) to be
small compared to Vgt). We will check this assumption at the end.
Im2 = 100u * 1/.25 * ((2.5 – 0 - .5) * Vol – Vol2/2)
This time, only unknown is Vol so again using any equation solver (or you can guess and iterate), you
arrive at
Vol = .786 V
Does this value check for our original assumption? Yes it does since V gt = 2 and Vds = .786 V so this is
an acceptable answer.
b) Calculate tpLH and tpHL. This will require you to find a Req and Ceq in each case.
To calculate both tpLH and tpHL, we cannot use the equation t = 0.69ReqCeq because that would imply we
were swinging from a rail to half the supply voltage. We’ll have to actually use the exponential to find
the constant * RC to find this delay.
We need to find Req and Ceq, which are different on the H→L and L→H transitions. You can do a
complicated integral, but for our first order approximations, you can find the resistance at the start and
end of a transition and average them.
ReqHL:
The H → L transition begins at Vout = VOH and ends at Vout = Vdd/2 = 1.25V in this problem
Let’s find the equivalent resistance at the start and end points respectively. For this transition, there are
3 components that come into play. There’s the R m1, Rm2 and the resistive load.
How do we calculate the equivalent resistances? Remember V = IR!
Rm2:
VDS @ beginning = VOH = 1.65 V (device is in triode/linear region)
IDS @ beginning = k’(W/L)2[(VDD-Vt)VM-VM2/2 = 100µA/V2*4*[(2.5V-0.5V)*1.65 –(1.65)2/2]
= 775.5 uA
VDS @ end = 1.25V(device is in triode/linear region)
IDS @ end = k’(W/L)2[(VDD-Vt)VM-VM2/2] = 100µA/V2*4*[(2.5V-0.5V)*1.25V-(1.25V)2/2]
= 687.5 uA
Rm2,begin = 2.13kΩ
Rm2,end = 1.82kΩ
Rm1:
VDS @ beginning = VDD -VOH = 0.85 V
Vt = .645V (due to the body effect)
IDS @ beginning = ½ k’ (W/L) 2 (VDD-VOH-Vt)2 = ½*100µA/V2*8*(2.5V-1.65V-.645V)2
= 16.8 uA
VDS @ end = 1.25 V
Vt = .617V (due to the body effect)
IDS @ end = ½ k’(W/L)1(Vdd-VDD/2-Vt)2 = ½*100µA/V2*8*(2.5V-1.25V-.617)2
= 160 uA
Rm1,begin = 506kΩ Rm1,end = 7.8kΩ
To find the equivalent resistance, we have to see what helps and what hurts our transition. Since we are
going from High to Low, M2 and the resistive load helps pull the output down while M1 tries to pull the
output high. Thus, Rm2 and Rload will be positive resistances and Rm1 will be a negative resistance. We
find the equivalent at the beginning and end of the transitions and average the two resistive values.
RbeginHL = (1/2.13k + 1/100k – 1/506k)-1 = 2.03k
RendHL = (1/1.82k + 1/100k – 1/7.8k)-1 = 2.32k
ReqHL = ½(2.03k + 2.32k) = 2.18k
ReqLH
Thankfully, tPLH is easier to calculate because Rm2 = ∞ at the start and end of the transition because
VGS, M2 = 0V < Vt, meaning it is always off. What are the start and end points of the transition? V OL
and Vdd/2
Rm1:
VDS @ beginning = VDD -VOL = 2.5V - .786V = 1.714V
Vt = .58V due to the body effect
IDS @ beginning = ½ k’(W/L)1(VDD-VOL-Vt)2 =514 uA
VDS @ end = VDD – VDD/2 = 1.25V
Vt = .617V (as above)
IDS @ end = ½ k’(W/L)1(VDD-VDD/2-Vt)2 = 160 uA
Rm1,begin = 3.33 kΩ
Rm1,end = 7.8 kΩ
Repeating the process above (except Rm1 is now positive and Rload is negative):
RbeginLH = (1/3.33k – 1/100k)-1 = 3.44k
RendLH = (1/7.8k – 1/100k)-1 = 8.46k
ReqLH = ½(3.44k + 8.46k) = 5.95k
Ceq:
There are two components at work for the self-loading: the diffusions and the overlap capacitances. The
diffusion capacitances are the capacitors between the output and bulk of M1 (C sb1) and output and bulk
of M2 (Cdb2):
Cdiff = Cj * L * W + Cjsw * (2 * L + W)
Using Cj = 2 fF/um2 and Cjsw = .28 fF/um from Table 3.5, we can easily figure out the self loading:
M1: Csb1 = 2f * .25 * 2 + .28f * (2 * .25 + 2) = 1.7 fF
M2: Cdb2 = 2f * .25 * 1 + .28f * (2 * .25 + 1) = .92 fF
The overlap capacitances come from the Gate to Channel capacitors seen at the output. For M1, the
device is always saturated so total Cgs = Cgs0 + Cgcs (saturation region):
Cgs1 = (Co * W) + (2/3 * Cox * W * L) = (.31f * 2) + (2/3 * 6f * 2 * .25) = 2.62 fF
This does not get miller multiplied since the input to M1 does not change.
To calculate the Cgd2, the approach is the same as Cgs1 except M2 is in different regions based on a lowhigh or a high-low transition. If output swings high-low, the device is always in triode whereas when
the output swings low-high, the device is in cutoff. Therefore, there will be a different equivalent
capacitance associated with each transition much like the resistances.
(high-low) Cgd2 = (Co * W) + (Cox * W * L * ½) = (.31f * 1) + (1/2 * 6f * 1 * .25) = 1.05 fF
(low-high) C gd2 = (Co * W) = (.31f * 1) = .31 fF
This capacitor does get miller multiplied because the input and output are toggling against each other.
Therefore:
Ceq = Csb1 + Cdb1 + Cgs1 + 2*Cgd2
(high-low) Ceq = 7.34 fF
(low-high) Ceq = 5.86 fF
DELAY
To calculate the delay, we need to find that constant to multiply RC by.
In the high-low case, the output travels from Voh to Vdd/2; low to high case, output travels from Vol to
Vdd/2. The decaying exponentials are:
(high-low) V = .786 + .864 * exp(-t/RC)
(low-high) V = 1.65 - .864 * exp(-t/RC)
Subbing in V = Vdd/2, and solving for t, we arrive at the constants:
(high-low) .62
(low-high) .77
Therefore:
tHL = .62 * 2.18k * 7.84f = 10.6 ps
tLH = .77 * 5.95k * 5.86f = 26.8 ps
c)
Assuming a normal pmos/nmos inverter is the load presented at the output, what other capacitances
would we have to account for in the Ceq calculation in addition to those you used for part b)?
The extra capacitances would be the gate-drain capacitances of the gates of the following inverters
(might have to take into account the Miller effect), the gate-source capacitances as well as the
capacitance of the wire that connects the two gates.
d) Find the static power dissipation for –
i. Vin = 0.0V ii. Vin = 2.5V
Assuming no leakage current,
i. When Vin = 0.0V, M2 is off. Current running through circuit = current through resistor. We know V out
= Voh so I = 1.65/100k = 16.5 uA (found 16.8 uA for M1 above. Pretty much the same and good enough
for first order hand analysis)
P = IV = 16.5u * 2.5V = 41.25 uW
ii. M1 and M2 are both on. Use current through M1 from above when the input is 2.5V so Vout = Vol. I
= 514 uA.
P = IV = 514u * 2.5V = 1.28 mW
Problem #2
a)
It is always good to get a feel for design rules in a layout editor. Fire up max with the mmi25 (0.25 um)
technology file (this is the default setup). Place a minimum sized NMOS transistor and examine the
dimensions. The layers are listed and shown below in Figure 2a. Determine and list the following:
a. Minimum Transistor Length
b. Minimum Transistor Width
c. Minimum Source/Drain Area
d. Minimum Source/Drain Perimeter
Please list the design rules you come across that lead to your results.
*TIPS - Use Shift-G to access the grid menu. Set the coarse grid to 0.1um, fine grid to 0.01um
Use Shift-Y to explain the design rules within a selected area
poly
nfet
ct
ndif
Figure 2a
Rules are:
i)
Poly minimum width = 0.24 µm
ii)
CT minimum width = 0.3 µm
iii)
CT_NDIF to NFET MIN, spacing = 0.22 µm
iv)
ALL_POLY_DIF MIN CT enclosure = 0.14 µm
Using these values
a.
L = 0.24 µm
b.
W = 0.3 µm + 2(0.14 µm) = 0.58 µm (0.60 µm acceptable)
c.
Ldrain = 0.3 µm + 0.14 µm + 0.22 µm = 0.66 µm
AD = AS = Ldrain * W = 0.66 µm * 0.58 µm = 0.383 µm2 ≈ 0.4 µm2
d.
PD = PS = W + 2Ldrain = 0.58 µm + 2*0.66µm = 1.9 µm ≈ 2.0 µm
Note that the perimeter only includes W once and not twice!
b) We desire a minimum sized CMOS inverter with a symmetrical VTC (VM=VDD/2) in the mmi25
technology. Calculate the following for the pull-up PMOS transistor in the design.
a. Minimum Transistor Length
b. Minimum Transistor Width
c.
d.
Minimum Source/Drain Area
Minimum Source/Drain Perimeter
Assume the following:
VDD = 2.5V, VM = 1.25V, and refer to Table 3.2 in the Draft Chapters
We will use equation 5.5 from the draft chapters:
kn'VDSAT, n(VM  Vt , n  12 VDSAT, n)
(W / L) p

(W / L)n kp'VDSAT, p(VDD  VM  Vt , p  12 VDSAT, p)
The gate lengths will be identical and thus we can calculate Wp = 2.02 µm,
AD = 1.33 µm2, and PD = 3.34 µm.
c)
Using the same minimum size inverter from part b), determine the input capacitance (i.e. the load it
presents when driven). Please calculate the capacitance during a transition. From these, determine the
total load capacitance that the inverter presents.
*Hint: Consider the Miller effect
You have three capacitances per transistor to consider on an inverter for input capacitance, gate to bulk,
gate to source and gate to drain. Cox = 6.0fF/µm2
PMOS:
Cgb
saturated = 2/3 (CoxLpWp) = 2.02 fF
triode = CoxLpWp = 3.03 fF
cutoff = CoxLpWp = 3.03 fF
Cgd
= COWP = (3.1 fF/µm)*(2.02 µm) = 0.606 fF
Cgs
= COWP = (3.1 fF/µm)*(2.02 µm) = 0.606 fF
NMOS:
Cgb
Cgd
Cgs
saturated = 2/3 (CoxLnWn) = 0.595 fF
triode = CoxLnWn = 0.885 fF
cutoff = CoxLnWn = 0.885 fF
= COWn = (3.1 fF/µm)*(0.58 µm) = 0.174 fF
= COWn = (3.1 fF/µm)*(0.58 µm) = 0.174 fF
If switching Cin = (Cgbp + Cgbn) + (Cgsp + Cgsn) + 2 (Cgdp + Cgdn) = 6.225 fF
The factor of 2 is due to miller effect
NOTE!!!!!!
The Miller effect is included in the calculations purely because the inverter in question is unloaded by
anything external. THIS WILL RARELY OCCUR IN REALITY!!!! Only in this very special unloaded
case does an inverter have this Miller multiplication seen as part of it’s input capacitance.
d) Using the g25 model provided in ‘~ee141/MODELS/g25.mod’, please verify the accuracy of your
results in part c by determining the total input capacitance in a high-low and a low-high transition with
HSPICE and comparing with your total capacitance in part c. Turn in your HSPICE input deck.
You'll notice there are four corners, TT, FF, SS, FS, and SF. These represent the different variation
extremes we can expect due to process variations. For example, TT stands for NMOS: typical, PMOS:
typical. FS stands for NMOS: fast, PMOS: slow etc. For this homework, please use the TT model.
To use these models, include the following in your HSPICE deck:
.lib '~ee141/MODELS/g25.mod' TT
Input SPICE Deck:
______________________________________________________________________________
HW #3, prob. 2d (Dietrich Ho, 9/4/2000)
*****begin DEFINITIONS*****
.lib '~ee141/MODELS/g25.mod' TT
.param vddp = 5
.param ln_min = 0.25u
.param lp_min = 0.25u
.param l_drain = 0.66
.param
.param
.param
.param
arean(w)
areap(w)
perin(w)
perip(w)
=
=
=
=
'(w*l_drain*1p)'
'(w*l_drain*1p)'
'((w*1u)+(l_drain*2u))'
'((w*1u)+(l_drain*2u))'
*****end DEFINITIONS*****
VDD vdd 0 vddp
IIN 0 in 1u
M1 out vin vdd vdd pmos L=lp_min W=2.023u
M2 out vin 0 0 nmos L=ln_min W=0.6u
.ic v(in) = 0
.meas t1 trig at=2 targ v(in) val=’vddp/2’ cross=1
.meas t2 trig v(in) val=’vddp/2’ cross=1 targ v(in) val=supply cross=1
.meas CinLH param=’1u*t1/(vddp/2)’
.meas CinHL param=’1u*t2/(vddp/2)’
.options post=2 nomod
.op
.tran 0.1ns 15ns
.END
_______________________________________________________________________________
Relevant Capacitances:
CinLH = 5.9780 fF
CinHL = 5.6659 fF
The discrepancy between the measured and calculated values is probably due to fluctuation in CGB. In
our hand calculations, it is often better to err on the pessimistic side. By choosing to use CGB =
CoxWL, this gives an upper bound.
CinLH is larger than CinHL due to the fact that the gate capacitance decreases when VGS is near VT. During the H-L
transition, the PMOS gate cap is at its minimum. Thus, since the PMOS transistor is considerably larger than the
NMOS, CinHL is smaller than CinLH.
e)
Determine VIH, VIL , NMH, and NML.
*Hint: The 2 parameters r and g vary proportionally with transistor width. The equations given are
derived with the minimum width in mind. (Please refer to eqn. 5.3 and 5.10 in the draft chapters for r
and g)
First find r using eqn. 5.3 of the reader and then g using eqn. 5.10. Remember to account for the size
difference by applying direct ratio.
r = 1.94 g = 30.2
VM = VDD/2 = 1.25V
Then use equations 5.7 to solve:
VIH = VM + (2.5-VM)/g = 1.29V
NMH = VDD – VIH = 1.21 V
VIL = VM – VM/g = 1.21V
NML = VIL = 1.21V
Problem #3
a)
Figure 3a depicts the Id – VOUT curve of a typical NMOS transistor
Figure 3b depicts the Id – VOUT curve of a typical PMOS transistor
Assume we use these FETs to create a CMOS inverter. Using this family of curves, graph the VTC,
and calculate VM, VIL, and VIH.
Top: Figure 3a, Bottom: Figure 3b
Problem 3a
If you’re interested, the input SPICE Deck used to create the family of curves and the VTC seen below
in Figure Solutions.2d can be found
Figure Solutions.2d
The simplest way to determine the input voltages is to note the points on the curve where the slope is –
1, which was defined in class. VM can be determined by noting the point of intersection between the
VTC and a linear curve with slope = 1.
VIL = 1.1V
NML = 1.1V
VIH = 1.4V
NML = 1.1V
VM = 1.25V
Input Spice Deck for Prob. 3, NMOS Id-Vout Characteristics:
_______________________________________________________________________
Hw #3, Prob. 3 - NMOS (Dietrich Ho, 9/4/2000)
.lib '~ee141/MODELS/g25.mod' TT
vdd vdd 0 2.5
vin vin 0 0
vds vds 0 0
m1 vds vin 0 0 nmos w=1.0u l=0.25u
.dc vds 0 2.5 0.1 vin 0 2.5 0.5
.plot LX4(m1)
.option post=2 nomod
.END____________________________________________________________________
Input Spice Deck for Prob. 3, PMOS Id-Vout Characteristics:
_______________________________________________________________________
Hw #3, Prob. 3 - PMOS (Dietrich Ho, 9/4/2000)
.lib '~ee141/MODELS/g25.mod' TT
vdd vdd 0 2.5
vin vin 0 0
vds vds 0 0
m1 vds vin vdd vds pmos w=3.0u l=0.25u
.dc vds 0 2.5 0.1 vin 0 2.5 0.5
.plot LX4(m1)
.option post=2 nomod
.END____________________________________________________________________
Input Spice Deck for Prob. 3, VTC:
_______________________________________________________________________
Hw #3, Prob. 3 - VTC (Dietrich Ho, 9/4/2000)
.lib '~ee141/MODELS/g25.mod' TT
vdd vdd 0 2.5
vin vin 0 pulse 0 2.5 0 5n 5n 10n 10n
m1 vout vin vdd vdd pmos w=3.0u l=0.25u
m2 vout vin 0 0 nmos w=1.0u l=0.25u
.dc vin 0 2.5 0.1
.tran 1n 50n
.option post=2 nomod
.END___________________________________________________________________________
b) If we increase the W/L ratio of the pull-down NMOS (leaving the PMOS size fixed), in which direction
will the VTC shift?
The VTC will shift to the left.
c)
If instead, we increase the W/L ratio of the pull-up PMOS (and leave the NMOS the original size), in
which direction will the VTC shift?
The VTC will shift to the right.
d) Please explain how the resizing in b) and c) will affect the above I-V curves in each case and give an
intuitive explanation of how this affects the VTC of each.
If we increase the W/L of an NMOS or PMOS, it moves the I-V curves up (higher magnitude of current
for same input voltage). As such, a larger NMOS gives more pulldown “strength,” while a larger
PMOS gives more “pullup” strength.