Survey
* Your assessment is very important for improving the workof artificial intelligence, which forms the content of this project
* Your assessment is very important for improving the workof artificial intelligence, which forms the content of this project
Covariance and contravariance of vectors wikipedia , lookup
Euclidean geometry wikipedia , lookup
History of trigonometry wikipedia , lookup
Riemannian connection on a surface wikipedia , lookup
Perceived visual angle wikipedia , lookup
Trigonometric functions wikipedia , lookup
Tensor operator wikipedia , lookup
Rotation matrix wikipedia , lookup
Rotation formalisms in three dimensions wikipedia , lookup
Plane of rotation wikipedia , lookup
Proceedings of the International Conference on Emerging Trends in Engineering and Management (ICETEM14) 30 – 31, December 2014, Ernakulam, India INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATION ENGINEERING & TECHNOLOGY (IJECET) ISSN 0976 – 6464(Print) ISSN 0976 – 6472(Online) Volume 5, Issue 12, December (2014), pp. 76-83 © IAEME: http://www.iaeme.com/IJECET.asp Journal Impact Factor (2014): 7.2836 (Calculated by GISI) www.jifactor.com IJECET ©IAEME HIGH SPEED CORDIC DESIGN FOR FIXED ANGLE OF ROTATION Nidhin K.V1, 1 Meera Thampy2 M.Tech VLSI & Embedded Systems, ECE, SNGCE, Ernakulam, India, 2 Assistant Professor, ECE, SNGCE, Ernakulam, India, ABSTRACT CORDIC means coordinate rotation digital computer. Rotation of vectors through fixed and known angles has wide applications in robotics, digital signal processing, graphics, games, and animation .It is the CORDIC , A proposed scheme preferred for vector-rotation through specific angles. Therefore, this paper present optimization schemes and Basic CORDIC circuits for fixed and known rotations. Pipelined schemes are suggested further for cascading dedicated single-rotation units and bi-rotation CORDIC units for high-throughput and reduced latency implementations. Here optimized set of micro-rotations for fixed and known angles and the optimized scale-factors and its dedicated shift-add circuits are designed to implement the scaling. Here a high speed and a less complex CORDIC scheme is proposed. The number of adders/sub tractor & shifters are reduced for the area minimization & carry select adder is mapped as an adder design inside the FPGA kit to improve the latency. For the rotation of vector at large angles an argument reduction technique is proposed here .The proposed CORDIC scheme can be applied to FFT processor in order to get twiddle factor which perform the complex multiplication operation. Keywords: Angle Mapping, Angle Recoding (AR), Coordinate Rotation Digital Computer (CORDIC), Carry Select, Scale Factor, Sign Bit Register(SBR). I. INTRODUCTION CORDIC is an acronym for Coordinate Rotation Digital Computer. It is a class of shift add algorithms for rotating vectors in a plane, which is usually used for the calculation of trigonometric functions [2]. The CORDIC algorithm has become a widely used approach to elementary function evaluation when the silicon area is a primary constraint. The CORDIC algorithm was developed by J. E. Volder in 1959 for the computation of trigonometric functions. This has been recognized as the best compromise between the table look up approach requiring large memory, and polynomial approximation method, which is slow to converge to the desired precision. In 1971, Walther has generalized this algorithm to implement rotation in circular, linear and hyperbolic coordinate systems. Since then it has been used as an elegant method to realize elementary functions such as multiplication, division, logarithmic and exponential functions in addition to the computation of two dimensional vector rotations. These transcendental functions are the core for many applications such as digital signal processing, graphics, image processing and kinematic processing [11]-[13]. The implementation of CORDIC algorithm requires less complex hardware than the conventional method. 76 Proceedings of the International Conference on Emerging Trends in Engineering and Management (ICETEM14) 30 – 31, December 2014, Ernakulam, India Here the aim of the project is to introduce a high speed or low latency VLSI architecture for CORDIC algorithm. The speed improvement can be achieved by employing carry select adder and the complexity of CORDIC is optimized by the reduce of number of adders/sub tractor& shifters in CORDIC design. 2. PREVIOUS METHODOLOGIES Latency of computation is the major issue with the implementation of CORDIC algorithm due to its linear-rate convergence. Overall latency of computation increases linearly with the product of the word-length L and the CORDIC iteration period. The speed of CORDIC operations is, therefore, constrained either by the precision requirement (iteration count) or the duration of the clock period. The duration of clock period on the other hand mainly depends on the large carry propagation time for the addition/subtraction during each micro-rotation. It is a straight-forward choice to use fast adders for reducing the iteration period at the expense of large silicon area. Use of carry-select adder is a good option to reduce the iteration period and overall latency. To handle latency bottlenecks, various techniques have been developed and reported in the literature. Conventional CORDIC [1] [2] [19], a reference CORDIC requires (n+1) iteration for the n bit precision of output. Most of the well known algorithms could be grouped under, high-radix CORDIC, the angle-recoding method. A high-radix CORDIC [12] algorithm in vectoring mode is suggested, which can be used for reduced latency operation at the cost of larger size tables for storing the elementary angles and pre-scaling factors than the radix-2. The purpose of angle recoding (AR) [4]-[8] is to reduce the number of CORDIC iterations by encoding the angle of rotation as a linear combination of a set of selected elementary angles of micro-rotations. AR methods are well-suited for many signal processing and image processing application. Elementary Angle Set (EAS) AR scheme which has number of iteration reduced to half of that of conventional CORDIC. Extended Elementary Angle Set (EEAS) [6] AR scheme which has better recoding efficiency than EAS but has longer iteration period than the previous schemes. Keeping these in view, in this paper, we present the optimization schemes for reducing the latency of computation and for reducing the complexity of CORDIC for fixed-angle. Vector-rotation. Here a cascaded pipelined circuit is derived for all schemes which is faster and involves less area-delay. Complexity than the existing approaches. The contributions of this paper are as follows. 1) Optimized number of micro-rotations is derived for the implementation of fixed-angle vector-rotation. 2) Single-rotation and Bi-rotation CORDIC circuits are designed and used to derive cascaded CORDIC for high speed Fixed-angle rotation of vector. 3) Single-rotation and Bi-rotation CORDIC with sharing of adder/sub tractor and shifters are designed for the complexity reduction of CORDIC. 4) Bi-rotation CORDIC with carry select adder design is also designed for high speed addition. 5) An Angle mapped Bi-rotation CORDIC is also designed for the large vector angle rotation. 3. CORDIC THEORY: AN ALGORITHM FOR VECTOR ROTATION The CORDIC algorithm is an iterative method for the computation of two dimensional vector rotations in linear, circular and hyperbolic coordinate systems depending on the function to be realized, by using addition and shift operations. The CORDIC method can be implemented in two different modes, namely, rotation or forward rotation mode and vectoring or backward rotation mode. For the given initial coordinates of a vector and target angle, the rotation mode is used for general rotation of vector by the given angle and to compute elementary operations such as trigonometric functions, multiplication, exponential, and hyperbolic functions depending on the coordinate system. The vectoring mode is used to determine the angular argument of the original vector, and to compute division and logarithmic functions, for the given initial and final coordinates of vector. CORDIC computation is inherently sequential due to two main bottlenecks: 1) the micro-rotation for any iteration is performed on the intermediate vector computed by the previous iteration and 2) the (i+1) th iteration could be started only after the completion of the i th iteration, since the value of SBR (sign bit register) which is required to start the (i+1)th iteration could be known only after the completion of the i th iteration. 3.1 Basic concept of CORDIC Arithmetic All trigonometric functions can be computed or derived from functions using vector rotations. The CORDIC Algorithms [1] [3] can provide the calculation of vector rotation and inverse tangent. The algorithm, credited to Volder is derived from the general rotation transform: x'= x cosφ - y sinφ (1a) 77 Proceedings of the International Conference on Emerging Trends in Engineering and Management (ICETEM14) 30 – 31, December 2014, Ernakulam, India y'= y cosφ + x sinφ (1b) which rotates a vector in a Cartesian plane by the angle φ. These can be arranged so that: x'= cosφ.[ x- y tanφ ] (1c) y'= cosφ.[ y + x tanφ ] (1d) If the rotation angles are restricted such that tan (φ) = +/-2-i, the multiplication by the tangent term is reduced to simple shift operation. Arbitrary angles of rotation are obtainable by performing a series of successively smaller elementary rotations. If the decision at each iteration i, is which direction to rotate rather than whether or not to rotate, then the term cos (φ) becomes a constant. In the CORDIC method [1][3][5] , the rotation by an angle θ is implemented as an iterative process, consisting of micro-rotations during which the initial vector is rotated by pre-determined step angles represented to certain accuracy by a set of step angles αi . Any angle θ can be n step angles α i . Specifying a direction of rotation or sign σ i , the sum of the α i approximates a given angle θ as follows: n −1 θ = ∑σ α i i , σ i ∈ { − 1, 1 } (2) i =0 i −1 The sign of the difference between the angle θ and the partial sum of step angles θ − ∑ σ jα j controls the j =0 sign σ i of the step angles α i . An auxiliary variable zi is introduced that contains the accumulated partial sum of step angles and is used to determine the sign of the next micro-rotation. To simplify the computation of the matrix product , the step angles αi are chosen such that tan α i represents a series of powers of 2: tan α i = 2 − i , i = 0 , 1, 2 , ... , n − 1 (3) . The rotation mode of the CORDIC algorithm has three inputs that are initialized to the co-ordinate components of the vector x0 , y0 and the angle of rotation z0 = θ and is described by the following iteration equations: x i +1 = x i − y i σ i 2 − i (4a) y i +1 = y i + x i σ i 2 − i (4b) z i +1 = z i − σ i arctan 2 − i (4c) Where σ = − 1 if z i < 0 and i = 0, 1, 2 ,..., n − 1 i + 1 if z i ≥ 0 The outputs of the rotation mode xn , yn and zn are given by the following expressions where xn and y n being the co-ordinates of the rotated (by the angle θ ) vector: x n = K n ( x 0 cos z 0 − y 0 sin z 0 ) (5a) y n = K n ( y 0 cos z 0 + x 0 sin z 0 ) (5b) zn = 0 (5c) n −1 Kn = ∏ 1 + 2 −2i (5d) i=0 78 Proceedings of the International Conference on Emerging Trends in Engineering and Management (ICETEM14) 30 – 31, December 2014, Ernakulam, India The computation of xi + 1 or yi + 1 requires an i bit right shift and add/subtract. If the function tan-1 (2-i) is pre computed and stored in table for different values of i, a single add/ subtract suffices to compute zi + 1. The tan-1 (2-i) values corresponding to 10 iterations are listed in Table 1. Each CORDIC iteration thus involves two shifts, a table lookup and three additions. If the rotation is done by the same set of angles (with + or – signs), then the expansion factor K, is a constant, and can be pre computed. For example to rotate by 30 degrees, the following sequence of angles be followed that add up to approximately 30 degree. 30.0 ≈ 45.0 –26.6 + 14.0 – 7.1 + 3.6 + 1.8 – 0.9 + 0.4 – 0.2 + 0.1 = 30.1 Here z is initialized to 30 degree and then, in each step, the sign of the next rotation angle is selected to try to change the sign of z; that is, (µ i in figure) σi= sign (zi) is chosen, where the sign function is defined to be – 1 or 1 depending on whether the argument is negative or nonnegative. TABLE I: Arc Tan value corresponding to the Iterations Iteration (i) tan−1(2−i) ( in degree) 0 45.0 1 26.6 2 14.0 3 7.1 4 3.6 5 1.8 6 0.9 7 0.4 8 0.2 9 0.1 This is reminiscent of no restoring division. Here First three of the ‘10’ iterations leading from (x0, y0) to (x10, 0) in rotating by + 30 degree is in Rotation mode. The accuracy of computation of angle increases with the increase in number of iterations. But the latency of rotation will be a high value. 4. PROPOSED SCHEMES 4.1. Cascade single rotation CORDIC In cascade CORDIC design a rotation module performs a micro rotation step with 2 inputs corresponding to i th iteration& getting 2 outputs corresponding to (i+1)th iteration [1]. Each rotation module has a pair of adder/sub tractor with direct and shifted version of coordinates as the inputs. If the coordinates getting on iteration is not equivalent to the cosine and sine values of exact angle, it has to perform micro rotation corresponding to the next iteration. Here shifting of input is done by barrel shifter. s (i) represent number of shift at i th iteration. The influence of scaling achieved by providing scale factors , no of shift (s(i)) and SBR (sign bit register ) for each input angle ranging from ( 0- 45 )degree [1]. The circuit of cascade single rotation CORDIC is shown in Fig 1. The need of scaling for the exact magnitude of original rotated vectorproposed by two dedicated CORDIC cells for the fixed-angle rotations. In one of those cells, micro-rotations and scaling are interleaved [1] [9], and in the other they are implemented in two separate stages [1] [13]. (a) (b) Figure 1: (a) Multi-stage single-rotation cascaded CORDIC circuit (b) Structure of ith rotation module 79 Proceedings of the International Conference on Emerging Trends in Engineering and Management (ICETEM14) 30 – 31, December 2014, Ernakulam, India In cascade CORDIC design ,for reducing the area and time-complexities, a hardwired pre-shifting scheme in barrel-shifters of the proposed circuits is proposed [1] .Here CORDIC design is capable of producing angle of rotation with approximated error with in 4 iteration ( no of iteration is reduced to half of that of reference CORDIC). 4.2. Bi-Rotation CORDIC Here we design an efficient CORDIC circuit to implement a pair of micro-rotations and named as “Bi-rotation CORDIC”.Here each rotation module performs a pair of micro rotation [1], [10], [11]. The proposed circuit for birotation CORDIC is shown in Fig 2. It consists of an adder module, two 2:1 multiplexers, two barrel shifters and a signbit register (SBR) of two bit size. The adder-module consists of a pair of adders/sub tractors. The adders/sub tractors perform additions or subtractions according to the sign-bit available from the SBR. The components of the input vector (real and the imaginary parts of the input complex operand) are loaded to the input-registers through set/reset input. The output of the registers are sent in two lines where the content of the register is fed to one of the adders/sub tractors directly while that in the other line is loaded to the barrel-shifter pre-shifted by k(0) bit-locations to right by hardwired pre-shifting technique [1]. By pre shifting technique k(0) LSBs are truncated to zero and load (L-k(0) )MSBs to the shifter . The output of the adders is loaded back to the input registers for the second CORDIC iteration. The Bi-rotation CORDIC involves only a pair of barrel-shifters consisting of only one stage of 2:1 Muxes. The control-bit for the barrel-shifters is 0 for the first micro-rotation (no shift) and 1 for the second micro-rotation (shift through). The control bits are generated by a T flip-flop, since they are 1 and 0 in each alternate cycle. For reduction of adder complexity over the cascaded single-rotation CORDIC, the micro-rotations could be implemented by a cascaded bi-rotation CORDIC circuit. The first two of the micro-rotations out of the four-optimized micro-rotations in the cascade single rotation CORDIC could be implemented by first stage, while the rest two are performed by next stage. For implementing six selected micro-rotations, we can use a three-stage-cascade of bi-rotation CORDIC cells. The threestage bi-rotation cells could however be extended further when higher accuracy is required. Figure 2: Cascade Bi-rotation CORDIC 4.3. Improved Cascade Single Rotation CORDIC Scheme In a CORDIC circuit which execute CORDIC equation we are presenting it with 2 adder/sub tractor & barrel shifter. Here we reduce the number of shifters & adders from two to one. That means same adder/sub tractor & barrel shifter is shared for executing both CORDIC equations 4(a) and 4(b). With the use of 2:1 Muxes one is in front of barrel shifter & other in front of adder/sub tractor, is used to select the path which has to perform shifting or addition. The circuit of this improved design is shown in Fig 3. Suppose S (selection input) =1 then y coordinate is shifted by barrel shifter and x coordinate is direct input as (~) S=0. Using this, entire circuit complexity is reduced comparing to other cascade single rotation CORDIC. But the time to complete execution is more in this modification compared to other schemes by the need of selection process. 4.4. Improved Cascade Bi-rotation CORDIC Scheme For the bi-rotation CORDIC no of iteration is less than cascade single rotation but here again bi-rotation is modified by sharingadder/sub tractor & barrel shifter for executing both CORDIC equations with the usage of 2:1 Muxes. It will again reduce the complexity of entire high through put scheme. The latency of this less complex scheme is improved by the inclusion of carry select adder as an adder design. In an CORDIC design the use of adder is to perform addition operation to implement CORDIC equation .We use +sign as an indication for addition ,on the time of implementation we use inbuilt adder inside the FPGA kit for addition. Instead of using inbuilt adder if we design carry select adder & mapped to the FPGA kit then it performs addition in a faster mode. 80 Proceedings of the International Conference on Emerging Trends in Engineering and Management Manage (ICETEM14) 30 – 31, December 2014, Ernakulam, India Figure 3: Modification of sharing of adder & shifter from 2 to 1 Figure 4: 4 Improved Cascade Bi-rotation CORDIC The circuit of improved cascade bi-rotation bi rotation CORDIC is shown in Fig 4. Here as by the working of carry select adder we know it will found out both sum and carryout for both Cin (input carry) = 1 and 0 & will select exact sum & carry through 2:1 Muxes using intermediate input carry as selection line. 4.5. Angle Mapped CORDIC Rotation Scheme An argument reduction technique [9] is used to reduce the total angular range to be computed. The Th main objective of theargument reduction technique is to uniquely map the results of a CORDIC rotation with a large target angle to the results of a CORDIC rotation with a relatively small target angle Ø. Suppose if we want to rotate the vector in an anglee which lies in the one of the 4 quadrant (0-360 (0 360 degree), the lookup table for scale factors ,shift & SBR are listed only for odd angles within the range (0(0 45 )degree[1] .So we need to perform angle mapping technique. To do this, we divide the four quadrants rants of the coordinate system into 8 equal domains each having a uniform angular span of ∏/4(i.e., four domains per quadrant). Any target angle (+ve or -ve) ve) must lie in one of these 8 domains. If the angle of rotation is greater than 90 degree then the reference eference angle (angle made by the vector near to the x–axis) x corresponding to the large rotated angle is to found out. Then we examine the CORDIC Rotation of an input vector with target angle Ø lying in the first quadrant. 81 Proceedings of the International Conference on Emerging Trends in Engineering and Management (ICETEM14) 30 – 31, December 2014, Ernakulam, India This essentially means that vector lies in one of the two domains B (0, ∏/4), A (∏/4, ∏/2) as shown in Fig 5. In each domain, ϴ can be redefined in terms of another angle bounded in the interval by the following equations: Figure 4: Angle Mapping CORDIC Process ϴ = Ø in domain B (6a) ϴ = ∏/4+ Ø in domain A (6b) If x1+ =cos(Ø); y1+ =sin(Ø); x1- =cos(-Ø); y1- =sin(-Ø); (6c) Then xfB=x1-,yfB=y1-; Ø= Ѳ (6d) xfA=1/√2[x1-+y1-] , yfA=1/√2[-x1-+y1-] ; Ø= Ѳ -∏/4 (6e) The CORDIC rotator operation with target angles lying in any domain in the first quadrant can be computed from the results of the CORDIC rotationwith target angle Ø (bounded in the interval (0,∏/4) ). This essentially means that the domain A is effectively folded back to domain B. Hence, we call this technique as domain folding. Here an angle mapped CORDIC bi-rotation scheme presented will add an extra feature for the entire CORDIC but it does not provide the advantage of less complexity and low latency. 5. RESULT ANALYSIS In order to verify the complexity and latency, we have captured our new CORDIC design in Verilog HDL and implemented into the Xilinx Spartan 3E series of FPGA. For performance comparison, we have also captured the design of previous high through put in Verilog HDL and implemented into the FPGA. Following section gives the performance results of this implementation. Proposed cascade Bi-rotation scheme which is providing the rotation of vector at less latency. It is the CORDIC scheme which provides high through put than any other previous schemes. Circuit wise the adder/sub tractor which implements the CORDIC equation is the carry select adder which provides a latency of 25 ns where as basic cascade birotation scheme has latency of 35ns. . Improved cascade single rotation which has number of slices is 13 %.(Number of slices for cascade single rotation CORDIC is 26%).So the complexity of proposed cascade scheme is reduced to half of that of basic cascade CORDIC scheme. TABLE 2: Area and Time Complexities of Different Architectures Cascade Cascade Improved Improved parameter single Bicascade cascade Birotation rotation single rotation rotation Latency 65ns 35ns 165ns 25ns Number of 26% 8% 13% 11% slices Number of 0 1 4 0 ROM Number of 16 75 292 147 add/sub 82 Proceedings of the International Conference on Emerging Trends in Engineering and Management (ICETEM14) 30 – 31, December 2014, Ernakulam, India 6. CONCLUSION The CORDIC circuits for the rotation of vector at fixed angle with optimized micro rotation are designed. The proposed single rotation CORDIC complexity is reduced by the sharing of adder/sub tractor and shifters with the help of mux circuits the same criteria applied for bi-rotation CORDIC and improved carry select adder design is mapped to bi-rotation for low latency. An additional feature of angle mapping is applied to the bi-rotation CORDIC for the rotation of vector at higher angles. ACKNOWLEDGMENT We would like to express our sincere gratitude to the Management and staff, SNG College of Engineering for providing the facilities. REFERENCES [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] Pramod Kumar Meher and Sang Yoon Park “CORDIC Designs for Fixed Angle of Rotation” IEEE Trans VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, vol. 21, no. 2, Feb 2013. J. E. Volder, “The CORDIC trigonometric computing technique,” IRE Trans. Electron. Comput., vol. EC-8, pp. 330–334, Sep. 1959. J. S. Walther, “A unified algorithm for elementary functions,” in Proc. 38th Spring Joint Comput. Conf., 1971, pp. 379–385. Y. H. Hu and S. Naganathan, “An angle recoding method for CORDIC algorithm implementation,” IEEE Trans. Comput., vol. 42, no. 1, pp. 99–102, Jan. 1993. Y. H. Hu and H. H.M. Chern, “A novel implementation of CORDIC algorithm using backward angle recoding (BAR),” IEEE Trans.Comput., vol. 45, no. 12, pp. 1370–1378, Dec. 1996. C.-S.Wu, A.-Y.Wu, and C.-H. Lin, “A high-performance/low-latency vector rotational CORDIC architecture based on extended elementary angle set and trellis-based searching schemes,” IEEE Trans. CircuitsSyst. II, Analog Digit. Signal Process., vol. 50, no. 9, pp. 589–601, Sep. 2003. T.-B. Juang, S.-F. Hsiao, and M.-Y. Tsai, “Para-CORDIC: Parallel CORDIC rotation algorithm,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 51, no. 8, pp. 1515–1524, Aug. 2004. T. K. Rodrigues and E. E. Swartzlander, “Adaptive CORDIC: Using parallel angle recoding to accelerate CORDIC rotations,” in Proc. 40th Asilomar Conf. Signals, Syst. Comput. (ACSSC), 2006, pp. 323–327. K. Maharatna, S. Banerjee, E. Grass, M. Krstic, and A. Troya, “Modified virtually scaling free adaptive CORDIC rotator algorithm and architecture,” IEEE Trans. Circuits Syst. for Video Technol., vol. 15, no. 11, pp. 1463–1474, Nov. 2005. L. Vachhani, K. Sridharan, and P. K. Meher, “Efficient CORDIC algorithms and architectures for low area and high throughput implementation,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 56, no. 1, pp. 61–65, Jan. 2009 T. Lang and E. Antelo, “High-throughput CORDIC-based geometry operations for 3D computer graphics,” IEEE Trans. Comput., vol. 54, no. 3, pp. 347–361, Mar. 2005. P. K. Meher, J. Valls, T.-B. Juang,K. Sridharan, and K. Maharatna, “50 years of CORDIC: Algorithms, architectures and applications,” IEEETrans. Circuits Syst. I, Reg. Papers, vol. 56, no. 9, pp. 1893–1907, Sep.2009. B. G. Blundell, An Introduction to Computer Graphics and Creative 3-D Environments. London, U.K.: Springer-Verlag, 2008. Nidhin K.V and MeeraThampy, “Low Latency CORDIC Architecture in FFT ”, International Journal of Advanced Research in Electronics and Communication Engineering (IJARECE) vol3, no. 10, October 2014. Sandeep Bidwai, Saylee S. Bidwai, Prof. Dr. S.P. Patil and Sunita S. Shinde, “Implementation & Performance Analysis of CORDIC in OFDM Based WLAN System using VHDL”, International Journal of Electronics and Communication Engineering & Technology (IJECET), Volume 3, Issue 3, 2012, pp. 103 - 111, ISSN Print: 0976- 6464, ISSN Online: 0976 –6472. Mahendra Kumar M.D, Sunil MP and Vinay Kumar S.B, “Comparative Analysis of Multi Stage CORDIC using Micro-Rotation Technique”, International Journal of Electronics and Communication Engineering & Technology (IJECET), Volume 4, Issue 3, 2012, pp. 270 - 281, ISSN Print: 0976- 6464, ISSN Online: 0976 –6472. 83