Download SPC560B4x/5x, SPC560C4x/5x, SPC560B54/6x, SPC560D30/40

AN3024
Application note
SPC560B4x/5x, SPC560C4x/5x, SPC560B54/6x, SPC560D30/40
hardware design guideline
Introduction
This application note complements the information in the device datasheet (see Section A.1:
Reference documents) by describing requirements useful for a hardware implementation of
the development board features such as power supply, reset control, clock management,
boot mode setting, debug management and I/Os settings. It shows how to use the product
and defines the minimum hardware resources required to start an application development.
Sections of this document describe certain device features in brief without describing the
device blocks in detail. For a detailed description of these features, refer to the device
datasheet, the reference manual or the errata sheet, or all three documents (see
Section A.1: Reference documents).
This application note applies to the devices listed in Table 1.
Table 1.
Device summary
Reference
Part number
SPC560B4x
SPC560B40L3, SPC560B40L5, SPC560B44L3
SPC560B5x
SPC560B50L3, SPC560B50L5, SPC560B50B2
SPC560C4x
SPC560C40L3, SPC560C44L3
SPC560C50
SPC560C50L3
SPC560B54x
SPC560B54L3, SPC560B54L5
SPC560B60x
SPC560B60L3, SPC560B60L5, SPC560B60L7
SPC560B64x
SPC560B64L5, SPC560B64L7
SPC560D30x
SPC560D30L3
SPC560D40x
SPC560D40L1, SPC560D40L3
September 2013
Doc ID 16127 Rev 5
1/34
www.st.com
Contents
AN3024
Contents
1
2
Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.2
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.3
Current consumption and voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . 7
1.4
Layout recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2
Power-on reset (POR) and low voltage detectors (LVDs) . . . . . . . . . . . . . 10
2.3
System reset pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.4
3
4
2.3.1
Input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.3.2
Output characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Reset scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2
ADC performances optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
External oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.2
Fast external crystal oscillator (4 to 16 MHz) . . . . . . . . . . . . . . . . . . . . . . 16
4.3
Slow external crystal oscillator (32 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.3.1
4.4
5
6
2/34
Some recommended crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Layout recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Boot configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.2
Boot mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.3
Boot pin scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.2
JTAG I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
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AN3024
Contents
6.3
7
8
9
JTAG connector scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.2
I/O types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.3
I/Os configuration after reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.4
Maximum output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.5
I/O characteristic in STANDBY mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.6
General consideration for I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
EMC guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8.1
SPC560Bx/Dx software configurations . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8.2
Hardware guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Reference schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Appendix A Document management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
A.1
Reference documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
A.2
Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
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List of tables
AN3024
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
4/34
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
ADC module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Recomanded crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Boot mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Debug features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
I/O supply segment - SPC560B50x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
I/O weight . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
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AN3024
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Typical layout for VDD/VSS pair . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
System reset and low power circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Noise filtering on reset signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Reference reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
ADC input scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Input equivalent circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Reference oscillator circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Low power oscillator and resonator connection scheme . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Oscillator circuitry layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Boot mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Boot mode selection implementation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
JTAG connector scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Typical application schematic of SPC560B40x-LQFP144 . . . . . . . . . . . . . . . . . . . . . . . . . 29
Typical application schematic of SPC560B64-LQFP176 . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Typical application schematic of SPC560D40-LQFP100 . . . . . . . . . . . . . . . . . . . . . . . . . . 31
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Power supplies
AN3024
1
Power supplies
1.1
Introduction
The device requires a 3.3 V or 5.0 V operating voltage supply (high voltage). An embedded
regulator is used to supply the internal 1.2 V digital power (low voltage).
Three different high voltage pin supply types are used:
●
VDD_HV—high voltage external power supply for internal voltage regulators, I/O pins
and Flash
●
VDD_BV—high voltage external power supply for internal voltage regulator ballast
transistors
●
VDD_HV_ADCx—high voltage external power supply for each analog-to-digital
converter
Three different independent voltage regulators provide the 1.2 V digital power supply:
●
HPREG—high power internal voltage regulator used during normal operations. It can
be switched off in STOP mode and is automatically switched off in STANDBY mode.
●
LPREG—low power internal voltage regulator used when HPREG is off. It can be
switched off in STOP mode and is automatically switched off in STANDBY mode.
●
ULPREG—ultra low power internal voltage regulator. Always switched on and used in
STANDBY or in STOP mode when all other regulators are switched off.
External capacitors connected between the VDD_LV/VSS_LV pin pairs ensure the stability
of the internal 1.2 V HPREG and LPREG regulators.
Figure 1.
Power supply overview
VDD
VDD_BV
CBAL
Peripherals
8-KB SRAM
ctrl
ULPREG
RC
WKPU
Power Domain 0
Standby
VDD
VDD_HV
ctrl
Power Domain 21
24-KB SRAM
CDECn
LPREG
ctrl
VDD
VDD_HV_ADCx
CFlash
16-KB SRAM
ADC
VSS_HV_ADCx
HPREG
DFlash
Core
Peripherals
PLL
OSC
Power Domain 1
Main
VDD_LV
CREGm
1. PD2 is not developed in SPC560D30x/40x devices.
6/34
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AN3024
Power supplies
For a detailed list of supply-related pins for all packages, please refer to the voltage supply
pins section in device reference manual (see Section A.1: Reference documents).
1.2
Power supply scheme
The circuit is powered by a stabilized power supply VDD.
●
VDD_HV pins must be connected to VDD with external decoupling capacitors CDECn.
●
VDD_BV pin must be connected to VDD with external decoupling capacitor CBAL.
●
VDD_HV_ADC pin be connected to VDD with external decoupling capacitor CADC.
●
VDD_LV pins must be connected with external decoupling capacitors CREGm placed as
close as possible to the device pins.
●
VSS_HV and VSS_LV pins must all be connected together to GND.
Refer to the voltage regulator electrical characteristics section in the device datasheet (see
Section A.1: Reference documents) for exact capacitor values.
Figure 2.
Power supply scheme
SPC560Bx/Dx
VDD
VDD_BV
CBAL
VDD
CDECn
CREGm
VDD
VDD_HV 1/2/..n
VDD_HV_ADCx
VSS_HV 1/2/../n
VSS_HV_ADCx
CADC
VDD_LV 1/2/../m
VSS_LV 1/2/../m
Note:
The device cannot be supplied with external 1.2 V. The on-chip regulator must always be used.
Caution:
All BV and HV and ADCx supplies must be powered with a voltage level in the range
VDD 0.1 V, and all grounds must be in the range VSS 0.1 V.
1.3
Current consumption and voltage regulator
In order to select a suitable external voltage regulator and design a supply circuit, the
designer of the application must consider:
1.
The maximum consumption in steady state
2.
The maximum inrush current during device start-up
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Power supplies
AN3024
The maximum consumption in steady state depends on the frequency of the CPU, the
usage of the peripheral and the current drawn by the outputs. It can be estimated by
referring to the device datasheet (see Section A.1: Reference documents).
The inrush current required by the device during power-on reset or exit from STANDBY is
clamped at 300 mA and lasts for few microseconds (maximum 20 µs) until the CREGm
stabilization capacitors (total value ~1 µF) are charged. This current is drawn from the
VDD_BV pin.
Note:
The inrush current must be considered to dimension the decoupling capacitance of the
ballast (C_DEC1) value as during this inrush the application must ensure VDD remains in
the voltage range of the application (5 V or 3.3 V ±10 %). The steady current is used to
define the voltage regulator capability of the application.
1.4
Layout recommendations
All the supply connections, including pads, tracks and vias, must have impedance as low as
possible (less than 5 nH). This is typically achieved by using thick and wide Cu tracks and
preferably dedicated power supply planes in multilayer PCBs.
Moreover, it is recommended to use both low equivalent series resistance (ESR) and low
equivalent series inductance (ESL) capacitors. The capacitors must be placed as close as
possible to, or below, the appropriate pins on the underside of the PCB. Figure 3 shows the
typical layout of such a VDD/VSS pair.
Figure 3.
Typical layout for VDD/VSS pair
Via to VDD
Via to VSS
Capacitor
VDD
8/34
VSS
Doc ID 16127 Rev 5
AN3024
Reset
2
Reset
2.1
Introduction
The device has an integrated POR (power-on reset) to ensure a correct power-up
sequence: The device remains in reset state as long as the VDD is below the specified
threshold.
The device has four low voltage detectors to monitor VDD_HV and VDD_LV:
●
LVDHV3—monitors VDD so as to ensure that the device reset occurs for voltage values
less than minimum functional supply value
●
LVDHV5—monitors VDD when the application uses devices operating in the range
5.0 V ± 10%. By default the LVDHV5 is disabled (to allow 3.3 V operation) and must be
activated by the application.
●
LVDLVCOR—monitors the voltage provided to the main power domain (core, Flash,
PLL, JTAG and peripherals not included in the standby power domain)
●
LVDLVBKP—monitors the voltage provided to the power domain in standby mode
(8 Kbyte SRAM, optionally 24 Kbyte SRAM, power control unit, reset generation
module, voltage regulator, wake-up unit, API, CAN sampler, internal RC oscillators,
etc.)
The device has a dedicated bidirectional RESET pin (NRST) with Schmitt-Trigger
characteristics and noise filter for system reset.
For detailed information on reset sequence, please refer to the reset state machine section
in device reference manual (see Section A.1: Reference documents).
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Reset
AN3024
Figure 4.
System reset and low power circuitry
VDD
VDD_BV
CBAL
ctrl
Power Domain 0
Standby
ULPReg
VDD
VDD_HV
CDECn
ctrl
Power Domain 21
LPReg
ctrl
Power Domain 1
Main
HPReg
VDD_LV
CREGm
LVDLVCOR
POR
LVDHV3
LVDLVBKP
LVDHV5
RPU
External
Reset
NRST
Filter
Internal
Reset
System RESET
Power-on Reset
Destructive Reset (LVD & Watchdog)
Functional Reset (RGM)
1. PD2 is not developed in SPC560D30/40 devices.
2.2
Power-on reset (POR) and low voltage detectors (LVDs)
POR is required to initialize the chip during power-up and works only on the rising edge of
the VDD_HV supply. It is asserted when VDD_HV is above VPORUPmin and released when
VDD_HV is above VPORH.
Once the POR is released, power management modules, including internal LVDs, are up
and running. The system remains in reset state until the LVDHV3, LVDLVCOR and
LVDLVBKP thresholds are reached.
Note:
At power-up, although the VDD slope at the VDD_HV pad rises, it must remain in the range
of 3 V/s to 0.25 V/µs (see TVDD parameter in the device datasheet—refer to Section A.1:
Reference documents).
2.3
System reset pin
The device implements a dedicated bidirectional RESET pin (NRST) with Schmitt-Trigger
characteristics and noise filter.
10/34
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AN3024
2.3.1
Reset
Input characteristics
The external reset signal (pulse) on the NRST pin must be greater than WNFRST (500 ns).
Pulses less than WFRST (50 ns) are ignored. Any pulse between WFRST and WNFRST may or
may not generate an internal reset.
A noise applied on the reset signal might wrongly put the device in reset. In order to avoid
unexpected reset of the device, the NRST pad includes an analog filter which makes the
system immune to noise.
For additional information about filter characteristics, please refer to the nRSTIN electrical
characteristics section in the device datasheet (see Section A.1: Reference documents).
Figure 5.
Noise filtering on reset signal
VRSTIN
hw_rst
VDD
‘1’
VIH
VIL
‘0’
filtered by
hysteresis
filtered by
lowpass filter
WFRST
filtered by
lowpass filter
unknown reset
state
device under hardware reset
WFRST
WNFRST
2.3.2
Output characteristics
The NRST pad, when used as output, behaves as a MEDIUM pad (see the nRSTIN
electrical characteristics section in the device datasheet—refer to Section A.1: Reference
documents).
The duration of the NRST active time depends on the reset source and the device
configuration, but the minimum reset duration guaranteed is 80 µs.
2.4
Reset scheme
Figure 6 shows a typical circuit for controlling the NRST pin operation. The reset input pin
has an internal weak pull-up configured by default exiting from power-on, thus R1 can be
omitted. In the case in which an external capacitor is used to filter the NRST external signal,
an external pull-up reduces the charging time of this capacitor.
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Reset
AN3024
Figure 6.
Reference reset circuit
VDD
VDD
VDD_HV
Open drain
reset
MR
Manual
Reset
12/34
RST
VSS
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SPC560Bx/Dx
R1
NRST
VSS_HV
AN3024
ADC
3
ADC
3.1
Introduction
Table 2 shows ADC module present in the devices.
Table 2.
ADC module
Devices
ADC0 10-bit
ADC1 12-bit
SPC560B4x/5x,
SPC560C4x/5x
1
0
SPC560B54/6x
1
1
SPC560D30x/40x
0
1
The device uses a dedicated supply pair VDD_HV_ADC/VSS_HV_ADC for each ADC
analog module so as to decouple the ADC reference voltage from the noise generated
either by another part of the device or by the external application components.
VDD_HV_ADC must be at the same voltage level as the VDD_HV.
There are three different ADC input channels types:
●
ANP—internal multiplexed precise channels used for conversion requiring a low TUE
●
ANS—internal multiplexed standard channels used for conversion requiring a standard
TUE
●
ANX—external multiplexed channels used in conjunction with external multiplexer
controlled directly by the device
ANPs are input only pins. For channel characteristics, please refer to the ADC electrical
characteristics section in the device datasheet (see Section A.1: Reference documents).
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ADC
AN3024
Figure 7.
ADC input scheme
Up to 32 extended channels
through external MUX
MUX 8
MUX 8
MUX 8
MUX 8
Digital
Interface
Analog
switch
MUX 20
ANX[3]
ANX[2]
ANX[1]
ANX[0]
.
.
.
ANS[15] (Ch 47)
Up to 20 channels
medium accuracy
D
A
14/34
MUX 16
ANS[0] (Ch 32)
.
.
.
Doc ID 16127 Rev 5
ANP[15] (Ch 15)
ANP[0] (Ch 0)
16 channels
high accuracy
(Ch 64–71)
(Ch 72–79)
3
(Ch 80–87)
ADC system
(Ch 88–95)
MA[2:0]
AN3024
3.2
ADC
ADC performances optimization
The equivalent analog input interface for both 10-bit and 12-bit ADC channel is shown in
Figure 8.
Figure 8.
Input equivalent circuit
EXTERNAL CIRCUIT
INTERNAL CIRCUIT SCHEME
VDD
Source
RS
Filter
RF
Current Limiter
RL
CF
VA
RS
RF
CF
RL
RSW
RAD
CP
CS
CP1
Channel
Selection
Sampling
RSW
RAD
CP
CS
Source Impedance
Filter Resistance
Filter Capacitance
Current Limiter Resistance
Channel Selection Switch Impedance
Sampling Switch Impedance
Pin Capacitance (two contributions, CP1 and CP2)
Sampling Capacitance
To minimize the error induced by the voltage partitioning between this resistance (sampled
voltage on CS) and the sum of RS + RF + RL + RSW + RAD, the external circuit must be
designed to respect the Equation 1:
Equation 1
R S + R F + R L + R SW + R AD 1
V A  ----------------------------------------------------------------------  --- LSB
R EQ
2
Please refer to the analog-to-digital converter (ADC) chapter in device reference manual or
type specification versus pins and to the ADC electrical characteristics section in the device
datasheet for parameter values (see Section A.1: Reference documents).
Doc ID 16127 Rev 5
15/34
External oscillators
AN3024
4
External oscillators
4.1
Introduction
The product offers four clock sources to cover the various types of application:
●
Fast internal RC oscillator
●
Fast external crystal oscillator
●
Slow internal RC oscillator
●
Slow external crystal oscillator
An internal PLL is available to optimize the oscillator choice versus the required system
frequency.
This section is focused on the two external oscillators:
4.2
●
The fast external crystal oscillator for the system clock covering 4 MHz to 16 MHz
●
The slow external crystal oscillator for the 32 kHz low power clock
Fast external crystal oscillator (4 to 16 MHz)
The fast external crystal oscillator must be in the frequency range from 4 MHz to 16 MHz. If
the crystal (resonator) is in the range from 4 MHz to 8 MHz, the oscillator margin can be
adjusted by using an option bit which reduces the fast external crystal oscillator
consumption (low consumption configuration). The default manufacturing oscillator margin
is in the range from 4 MHz to 16 MHz.
Please refer to the device reference manual (see Section A.1: Reference documents) for
additional information about option bits and oscillator margin.
To reduce EMC emissions, it is recommended to use the slowest crystal (resonator)
together with the internal PLL, thus achieving the proper system operating frequency. The
drawback of using a slow crystal is the longer start-up time.
Figure 9 shows the external circuit needed for using the oscillator with a crystal or a
resonator.
Figure 9.
Reference oscillator circuit
EXTAL
EXTAL
Crystal
Resonator
C1
XTAL
DEVICE
XTAL
C2
DEVICE
For additional information, please refer to the fast external crystal oscillator (4 to 16 MHz)
electrical characteristics section in the device datasheet (see Section A.1: Reference
documents).
16/34
Doc ID 16127 Rev 5
AN3024
4.3
External oscillators
Slow external crystal oscillator (32 kHz)(a)
Figure 10 shows the external circuit needed for using the low power oscillator with a 32 kHz
crystal.
Figure 10. Low power oscillator and resonator connection scheme
OSC32K_EXTAL
OSC32K_EXTAL
Crystal
Resonator
C1
OSC32K_XTAL
OSC32K_XTAL
C2
DEVICE
DEVICE
For additional information, please refer to the slow external crystal oscillator (32 kHz)
electrical characteristics section in the device datasheet (see Section A.1: Reference
documents).
4.3.1
Some recommended crystal
Table 3 gives the references of recommended crystals certified by resonators suppliers and
verified through designer simulation in addition to the ones listed in the DS.
x
Table 3.
Recomanded crystal
Part number
EXS00A-MU00265
Family name
NX3215SA
1TJF0SPFP1AC00E DST310S
Freq.
CL
Supplier
32kHz
15pF
NDK
32kHz
15pF
KDS
However it is suggested to perform matching directly on customer application board, in order
to verify board parassitics.
4.4
Layout recommendations
The following recommendations should be observed for designing the oscillator circuitry
layout:
●
A current flow at the crystal fundamental frequency runs through the oscillator circuit. If
the oscillator is clipped, then the higher order harmonics are present. To minimize the
emissions generated by these currents, the oscillator circuit should be kept as compact
as possible.
a. 32 KHz external oscillator is not developed on SPC560D30x/40x device
Doc ID 16127 Rev 5
17/34
External oscillators
AN3024
●
VSS_HV should be connected directly to GND (VSS island) so that return currents can
flow easily between VSS_HV and the two capacitors (C1 and C2).
●
Avoid other high frequency signals near the oscillator circuitry.
●
Use the same GND for oscillator and oscillator driver (VSS_HV is between EXTAL and
XTAL, VSS island)
●
Layout: configure the GND supply at low impedance.
●
Shield the crystal with an additional ground plane underneath the crystal.
●
Do not place sensitive signals near the oscillator. Analyze cross-talk between different
layers.
●
The VSS pins close to the XTAL pin must be connected to GND plane (VSS island) and
decoupled from the closest VDD pin.
●
Capacitors are placed between both ends of the crystal and GND (guard ring). The ring
must be as small as possible.
●
If the crystal package is metallic, it should be connected directly to GND.
●
For isolating the noise from or to a particular area of the PCB, it is possible to surround
this area with a “guard ring.”
Figure 11 shows an example of an oscillator circuitry layout.
Figure 11. Oscillator circuitry layout
18/34
Doc ID 16127 Rev 5
AN3024
Boot configuration
5
Boot configuration
5.1
Introduction
The boot of the device is managed by the boot assist module (BAM).
The following boot modes are supported:
●
Single chip (SC)—The device boots from the first bootable section of the Flash main
array.
●
Serial boot (SBL)—The device downloads boot code from either LINFlex_0 or
FlexCAN_0 interface and executes it.
The boot mode selection is obtained by setting two pins: FAB and ABS[0].
5.2
Boot mode selection
The device detects the boot mode based on external pins (FAB and ABS[0]) and device
status. Figure 12 shows the boot sequence.
Figure 12. Boot mode selection
0/2
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9
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.
&LASH"OOT)$
INANYBOOTSECTOR
!"3
3ERIAL"OOT3",
,).&LEX
!"3
3ERIAL"OOT3",
&LEX#!.
&LASH"OOTFROM
LOWESTSECTOR
NO"OOT)$
3TATIC-ODE
'!0'2)
In Figure 12, the grey blocks represent hardware-implemented functions, while the white
ones are software-implemented functions in ROM memory.
Doc ID 16127 Rev 5
19/34
Boot configuration
AN3024
To boot either from FlexCAN_0 or LINFlex_0, the device must be forced into an alternate
boot loader mode via FAB pin (pad PA[9]). The type of alternate boot mode (CAN or LIN) is
selected according to the ABS[0] pin (pad PA[8]).
FAB and ABS[0] pins must be forced in the required state before initiating the reset
sequence.
.
Table 4.
Boot mode selection
FAB
(pad PA[9])
ABS[0]
(pad PA[8])
Boot ID
Boot mode
1
0
X
LINFlex_0
1
1
X
FlexCAN_0
0
X
Valid
Single chip
0
X
Not valid
Static mode
In single-chip mode, hardware searches the Flash boot sector for a valid boot ID. As soon as
the device detects a bootable sector, it reads the 32-bit word at offset 0x4 at the detected
sector. Single-chip mode is managed by hardware and BAM is not used.
BAM is executed only in the following cases:
●
Serial boot mode has been selected by FAB pin.
●
Hardware has not found a valid Boot-ID in any Flash boot locations.
If booting is not possible with the selected configuration (for example, if no Boot ID is found
in the selected boot location) then the device enters the static mode.
Please refer to the boot assist module (BAM) chapter in device reference manual (see
Section A.1: Reference documents) for additional information.
5.3
Boot pin scheme
To make all boot configurations possible, it is recommended to use external switches
connected to the FAB and ABS[0] pins, as shown in Figure 13.
Figure 13. Boot mode selection implementation example
6$$
41$#Y%Y
K:
&!"
6$$
K:
!"3;=
.OTE4HEPINS&!"AND!"3;=HAVETHEBOOTMODESELECTIONFUNCTIONDURINGRESETPHASE!FTERRESETPHASE
THEYARENORMAL)/PINSANDCANBEUSEDACCORDINGTOAPPLICATIONNEEDS
'!0'2)
20/34
Doc ID 16127 Rev 5
AN3024
Debug
6
Debug
6.1
Introduction
Table 5 shows debug features of the devices.
Table 5.
Debug features
Devices
JTAG
Nexus2+
SPC560B4x/5x, SPC560C4x/5x
Yes
Yes(1)
SPC560B54/6x
Yes
Yes(1)
SPC560D30x/40x
Yes
No
1. Only on the LBGA208 development package.
Nexus2+ is not discussed in this document.
6.2
JTAG I/Os
The JTAG interface is composed of:
●
Test data input (TDI) on pin PC[0]
●
Test data output (TDO) on pin PC[1]
●
Test mode select (TMS) on pin PH[10]
●
Test clock input (TCK) on pin PH[9]
Out of reset, all JTAG signals are configured for the JTAG communication. They can be
configured by software as user I/Os and made available to the application. If the application
needs to combine both the JTAG functionality for debug and programming purposes
together with the standard I/O function, some limitations must be considered:
●
PC[0], PC[1], PH[9] and PH[10] cannot be debugged using a JTAG debug interface.
●
The configuration of PC[0], PC[1], PH[9] or PH[10] as user I/Os prevents the
communication with the debugger, making impossible to debug the application.
●
These pins can only be set back to the JTAG functionality by means of a hardware or
software reset (it cannot be done through the JTAG debugger).
An external hardware application connected to those signals might interfere with JTAG
signals, making it impossible to enter debug mode without disconnecting the external
hardware. It is preferable to use these JTAG pins to define the hardware configuration of the
application rather than critical application functions.
Doc ID 16127 Rev 5
21/34
Debug
6.3
AN3024
JTAG connector scheme
Figure 14. JTAG connector scheme
6$$
0#;=4$)
0#;=4$/
0(;=4#+
K:
.234
0(;=4-3
K:
'!0'2)
22/34
Doc ID 16127 Rev 5
AN3024
I/Os
7
I/Os
7.1
Introduction
The device features a unique pad technology to sustain a current injection of IINJPAD (refer
to device datasheet , Section A.1: Reference documents) on digital and analog inputs. A
simple serial resistor is sufficient to protect the input characteristics.
7.2
I/O types
The device features three I/O types with different drive strength:
●
SLOW type—This is the most common output type suitable for most of the application
output signals and ensuring low electromagnetic emission.
It allows to drive up to 2 mA and can sustain a maximum frequency of 2 MHz.
●
MEDIUM type—This output type can sustain a higher frequency with a reduced delay
to meet the requirements of SPI communication or high speed CAN communication.
It allows to drive up to 3.8 mA and can sustain a maximum frequency of 16 MHz.
Out of reset, the medium speed outputs are configured as slow. To obtain the medium
performance the application must configure the slew rate using the SRC field in the
corresponding SIUL pad configuration register (SIUL_PCR).
●
FAST type—Only the Nexus MCKO signal features a fast pad which is not a user
signal.
Maximum output frequency depends directly on the capacitive load connected on the
output.
Please refer to the device datasheet and Reference manual (see Section A.1: Reference
documents), for the detailed electrical characteristics and port mapping.
Note:
7.3
1
All output types have a slope control (current) to reduce the EMI.
2
TDO pad is medium speed only. Writing the SRC field in the corresponding SIUL_PCR has
no effect.
I/Os configuration after reset
To avoid activating external components while under reset, all pads are forced to
high impedance inputs, with the following exceptions:
●
RESET is driven low
●
Boot mode pins
●
–
FAB is pull-down
–
ABS[0] is pull-up
JTAG pins
–
TCK, TMS and TDI are pull-up
–
TDO is high impedance
Doc ID 16127 Rev 5
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I/Os
7.4
AN3024
Maximum output current
The application must not modify the maximum current drive expected on each I/O type and
I/O segment. An I/O segment is a group of pads supplied by the same VDD_HV/VSS_HV pair.
Table 6.
I/O supply segment - SPC560B50x
Supply segment
Package
1
LBGA208(1)
2
3
4
Equivalent to LQFP144 segment pad distribution
5
6
MCKO
MDOn/MSEO
LQFP144
pin20–pin49
pin51–pin99
pin100–pin122
pin123–pin19
—
—
LQFP100
pin16–pin35
pin37–pin69
pin70–pin83
pin84–pin15
—
—
1. LBGA208 available only as development package for Nexus2+.
In order to keep the maximum current on each segment in specification, both static and
dynamic consumptions must be considered:
●
The maximum static current must remain below maximum IAVGSEG value so as to
ensure device reliability. The parameter IAVGSEG represents the average current drawn
by all outputs belonging to the same segment. For example, if VDD = 5 V then
IAVGSEG = 70 mA.
So, for example, if a body application uses loads that totally draw more than 70mA,
these loads should be distributed over more than one segment.
●
24/34
The maximum dynamic current must guarantee that the sum of the weight of
concurrent (per clock cycle) switching I/Os on a single segment should remain below
the 100%. For example, consider I/O’s weight in Table 7 related to segment 4 on
SPC560B40x device. Suppose we use the following concurrent switching I/Os for
LQFP144 package: PB3, PC9, PC14, PC15, PG5, PG4, PG3, PG2, PA2, PE0, PA1 – if
the pads are configured as slow (SRC=0), device functionality is guaranteed in case of
VDD=5 V (sum of weights=96%) but not for VDD=3.3 V (sum of weights=114%)
Doc ID 16127 Rev 5
AN3024
I/Os
I/O weight(1)
Table 7.
LQFP64(2)
LQFP144/LQFP100
Supply segment
Pad
LQFP LQFP LQFP
144
100
Weight 5 V
Weight 3.3 V
Weight 5 V
Weight 3.3 V
SRC(3) = 0 SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1
64
PB[3]
10%
—
12%
—
10%
—
12%
—
PC[9]
10%
—
12%
—
10%
—
12%
—
—
PC[14]
9%
—
11%
—
—
—
—
—
—
PC[15]
9%
13%
11%
12%
—
—
—
—
—
—
PG[5]
9%
—
11%
—
—
—
—
—
—
—
PG[4]
9%
12%
10%
11%
—
—
—
—
—
—
PG[3]
9%
—
10%
—
—
—
—
—
—
—
PG[2]
8%
12%
10%
10%
—
—
—
—
3
PA[2]
8%
—
9%
—
8%
—
9%
—
—
PE[0]
8%
—
9%
—
—
—
—
—
3
PA[1]
7%
—
9%
—
7%
—
9%
—
—
PE[1]
7%
10%
8%
9%
—
—
—
—
—
PE[8]
7%
9%
8%
8%
—
—
—
—
—
PE[9]
6%
—
7%
—
—
—
—
—
—
PE[10]
6%
—
7%
—
—
—
—
—
3
PA[0]
5%
8%
6%
7%
5%
8%
6%
7%
—
PE[11]
5%
—
6%
—
—
—
—
—
3
4
4
4
4
1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to125 °C, unless otherwise specified.
2. All LQFP64 information is indicative and must be confirmed during silicon validation.
3. SRC: “Slew Rate Control” bit in SIU_PCR.
Please refer to the I/O pad current specification section in the device datasheet and device
reference manual (see Section A.1: Reference documents) for the detailed electrical
characteristics and port mapping.
The dynamic consumption is caused by the output driver transistors during the output switch
and therefore is present only during the transition phase of the output (rising or falling edge).
7.5
I/O characteristic in STANDBY mode
In STANDBY mode the I/Os are disconnected from supply and they are in high impedance
state. Only the wake-up lines can be configured as:
●
High-impedance input (default configuration)
●
Input with weak pull-up
Doc ID 16127 Rev 5
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I/Os
AN3024
The configuration of the wake-up lines is supported in the wake-up unit. Please refer to the
wakeup unit (WKPU) chapter in reference manual (see Section A.1: Reference documents)
for additional information.
Note:
All wake-up lines left floating cause additional consumption due to their Schmitt Trigger
logic. To avoid unnecessary consumption all wake-up lines should be kept to VSS or VDD
either by the application or using the internal weak pull-up.
The TDO pad is part of the STANDBY domain in order to provide a handshaking mechanism
with a debugger in STANDBY mode. However, in STANDBY mode the TDO pin is configured
as input without pull-resistor and as a consequence, when no debugger is connected, the
TDO pad is floating causing additional current consumption.
In order to avoid additional consumption, TDO must be tied to VDD or GND by means of an
external pull-up (or pull-down) resistor in the range of 47–100 k.
If the PA[1] pin is configured as NMI the pull-up is automatically activated, but this has no
effect during STANDBY mode. In this case pull-up is then correctly configured through the
WKPU_WIPUER register; no external resistor is necessary.
7.6
General consideration for I/O
To avoid excess consumption and to improve the reliability of the application it is
recommended to configure unused I/Os as input with pull-up.
During the application design the absolute maximum voltage on I/O must be considered:
●
respect to ground: +6 V
●
respect to VDD: Voltage of each pin must remain in the range from VDD  0.3 and
VDD + 0.3
For more details refer to the device datasheet (see Section A.1: Reference documents).
26/34
Doc ID 16127 Rev 5
AN3024
8
EMC guidelines
EMC guidelines
This section summarizes recommendations for the system designers to improve the EMC
(electromagnetic compatibility) and, in particular, to reduce the radiant emissions of a
system based on the SPC560Bx/Dx devices.
Obviously, not all EMC techniques are covered. Therefore, it is recommended to refer to
other, more general EMC documentation in parallel to the present application note.
8.1
SPC560Bx/Dx software configurations
The SPC560Bx/Dx family offers some features that allow, with software configurations, to
cover some requests for reduction in the electromagnetic interference (or EMI) emissions:
8.2
●
The system clock should be chosen to avoid overlapping with known frequency (bands
of interest)
●
The FMPLL gives the possibility to modulate the system clock so to reduce the picks of
emission.
●
Choose the lowest possible slew rate of pins accordantly with the functionality choose
for the pins
●
The peripherals that are not used in the application should be disabled and clock gated
●
Configuring the unused pins as input weak pull-up (default configuration)
Hardware guidelines
Some recommendations to design a system layout are listed below:
●
VDD decoupling capacitors
Decoupling capacitors must be used to decouple BV and all HV and ADC supply pins
from GND. To avoid that the decoupling capacitors’ parasitic inductance couples with
the capacitance plane of the supply planes, certain measures of precaution should be
taken:
●
–
Place the capacitors as close as possible to the VDD pins on the SPC560Bx/Dx
device.
–
Use power planes or wide traces to connect from the SPC560Bx/Dx device to the
capacitor.
–
Use as many vias as possible in the connections from the SPC560Bx/Dx device to
the capacitors. For example, use at least two vias to connect the positive side of
the capacitor to the power plane.
Fast external crystal oscillator
To reduce EMC emissions, it is recommended to use the slowest crystal (resonator)
together with the internal PLL, thus achieving the proper system operating frequency.
The drawback of using a slow crystal is the longer startup time. In order to minimize the
amount of emissions, generated from the currents flowing in the oscillator circuit at the
crystal's fundamental frequency, the oscillator circuit should be kept as compact as
possible.
Doc ID 16127 Rev 5
27/34
EMC guidelines
●
AN3024
Grounding
Usually in a system it is possible identify different parts of circuits including digital,
analog, high current switching circuitry, I/O, and the main power supply. If these
different parts of the circuit use isolated grounds, they will be connected together at a
single point.
●
28/34
PCB considerations:
–
For single-chip applications, a minimum of four layers is used. For expanded mode
applications, a minimum of six layers is used.
–
There is at least one ground plane.
–
There is at least one power plane.
–
From the power and ground planes have not be present structures which obstruct
the flow of current, such as via overlapping (it is not allowed three via anti-pads to
merged). Furthermore, vias should be staggered as much as possible because
aligned vias create slots that obstruct the flow of current.
Doc ID 16127 Rev 5
Reference schematic
AN3024
9
Figure 15 shows a typical application schematic.
Figure 15. Typical application schematic of SPC560B40x-LQFP144
Doc ID 16127 Rev 5
Reference schematic
29/34
GAPGRI00208
6
4
2
SMBJ5339B
100uF
100uF
C10
0.1uF
5V LED
VDD_HV_ADC1
VSS_HV_ADC1
J12
TP1
GND
TP2
GND
TP3
GND
TP4
GND
1
2
+ C7
C2
0.1uF
+ C1
D1
POWER 2-BLOCK
1
2
3
4
5
6
7
8
9
1
2
VDD_BV
P5V_MCU
P3V3
P1V2_MCU
VDD_HV_ADC0
VSS_HV_ADC0
D2 ORANGE
1
2
2
R1
510Ohm
2
-
P5V
1
2
5
3
1
1
1
+
FUSE
J18
PI0
PI2
PI4
PI6
PI8
PI10
PI12
PI14
K1 POWER SW
P1
PI1
PI3
PI5
PI7
PI9
PI11
PI13
PI15
2
1
4
3
6
5
8
7
9 10
11 12
13 14
15 16
1nF 0.33uF
1nF 0.33uF
1nF
P5V_MCU
C5
32KHz CLOCK CIRCUIT
Rs1
0 Ohm
10pF
C32
470pF
C35
0.1uF
C34
470pF
C33
0.1uF
C6
P5V_MCU
P5V
J3
Rf1
Y2
2
4
1
3
32KHz_EN
10pF
3
P5V
Rs2
0 Ohm
CFS206-32.768KDZF-UB
P5V_MCU
DO NOT POPULATE
C31
0.1uF
J17
2 V_DBUG
J16
J14
R19
8 Ohm 1/4W
1
P5V_MCU
P5V
P5V
J8
2 PA9
R6
0805
DO NOT POP
3
R7
10k
R5
10k
R3
10k
P5V_MCU
FB1
VDD_HV_ADC0 P5V_MCU
FB3
R17
10k
EVTI
JCOMP
2 PA8
ABS0
FAB
V_DBUG
V_DBUG
1
1
J7
C51
470pF
C50
0.1uF
R4
10k
R2
10k
3
Doc ID 16127 Rev 5
VDD_BV
P3V3
R18
0805
DO NOT POP
VDD_HV_ADC1
FERRITE BEAD
FERRITE BEAD
C4
C3
10uF
0.1 uF
C11
C15
10uF
0.1 uF
VSS_HV_ADC1
VSS_HV_ADC0
FB2
FERRITE BEAD
C8
FB4
FERRITE BEAD
Rs
0 Ohm
10pF
NX8045GB-8.000M
C9
Rf
1M Ohm
Y1
DO NOT POPULATE
10pF
CLOCK CIRCUIT
J10
1
3
2
4
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PB10
PB11
PB12
PB13
PB14
PB15
39
40
176
1
88
91
92
93
61
60
62
97
101
103
105
107
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PC8
PC9
PC10
PC11
PC12
PC13
PC14
PC15
154
149
145
144
159
158
44
45
175
2
36
35
173
174
3
4
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
PD9
PD10
PD11
PD12
PD13
PD14
PD15
77
78
79
80
81
82
83
84
87
94
95
96
100
102
104
106
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
PE8
PE9
PE10
PE11
PE12
PE13
PE14
PE15
18
20
156
157
160
161
167
168
21
22
23
25
133
127
136
137
XTAL
EXTAL
56
58
RESET
TMS
TCK
29
148
155
PB[0]
PB[1]
PB[2]
PB[3]
PB[4]
PB[5]
PB[6]
PB[7]
PB[8]
PB[9]
PB[10]
PB[11]
PB[12]
PB[13]
PB[14]
PB[15]
PG[0]
PG[1]
PG[2]
PG[3]
PG[4]
PG[5]
PG[6]
PG[7]
PG[8]
PG[9]
PG[10]
PG[11]
PG[12]
PG[13]
PG[14]
PG[15]
PC[0]
PC[1]
PC[2]
PC[3]
PC[4]
PC[5]
PC[6]
PC[7]
PC[8]
PC[9]
PC[10]
PC[11]
PC[12]
PC[13]
PC[14]
PC[15]
PH[0]
PH[1]
PH[2]
PH[3]
PH[4]
PH[5]
PH[6]
PH[7]
PH[8]
PH[11]
PH[12]
PH[13]
PH[14]
PH[15]
PD[0]
PD[1]
PD[2]
PD[3]
PD[4]
PD[5]
PD[6]
PD[7]
PD[8]
PD[9]
PD[10]
PD[11]
PD[12]
PD[13]
PD[14]
PD[15]
PE[0]
PE[1]
PE[2]
PE[3]
PE[4]
PE[5]
PE[6]
PE[7]
PE[8]
PE[9]
PE[10]
PE[11]
PE[12]
PE[13]
PE[14]
PE[15]
XTAL
EXTAL
CLK_EN
TCKOUT
R15
0Ohm
VDD_BV
32
26
RESET
PH[10]
PH[9]
PI[0]
PI[1]
PI[2]
PI[3]
PI[4]
PI[5]
PI[6]
PI[7]
PI[8]
PI[9]
PI[10]
PI[11]
PI[12]
PI[13]
PI[14]
PI[15]
PJ[0]
PJ[1]
PJ[2]
PJ[3]
PJ[4]
VSS_HV_ADC0
VDD_HV_ADC0
VSS_HV_ADR1
VDD_HV_ADR1
VDD_HV_FLA0
VDD_HV_IO0_E1
VDD_HV_IO0_S3
VDD_HV_OSC0REG0
VDD_HV_FLA1
VDD_HV_IO0_W1
VSS_HV_IO0_N0
VSS_HV_IO0_E0
VSS_HV_IO0_S2
VSS_HV_IO0_S0
VSS_HV_IO0_W0
VSS_HV_IO0_W1
VDD_LV_FLA0
VDD_LV_PLL0
VDD_LV_COR0_W0
VDD_BV_FLA1COR0
VSS_LV_COR0_N0
VSS_LV_PLL0
VSS_26
VSS_LV_FLA1
BOLERO_176_2
122 PG0
121 PG1
16 PG2
15 PG3
14 PG4
13 PG5
38 PG6
37 PG7
34 PG8
33 PG9
138 PG10
139 PG11
116 PG12
115 PG13
134 PG14
135 PG15
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PB10
PB11
PB12
PB13
PB14
PB15
39
40
176
1
88
91
92
93
61
60
62
97
101
103
105
107
117 PH0
118 PH1
119 PH2
120 PH3
162 PH4
163 PH5
164 PH6
165 PH7
166 PH8
140 PH11
141 PH12
9 PH13
10 PH14
8 PH15
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PC8
PC9
PC10
PC11
PC12
PC13
PC14
PC15
154
149
145
144
159
158
44
45
175
2
36
35
173
174
3
4
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
PD9
PD10
PD11
PD12
PD13
PD14
PD15
77
78
79
80
81
82
83
84
87
94
95
96
100
102
104
106
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
PE8
PE9
PE10
PE11
PE12
PE13
PE14
PE15
18
20
156
157
160
161
167
168
21
22
23
25
133
127
136
137
172 PI0
171 PI1
170 PI2
169 PI3
143 PI4
142 PI5
11 PI6
12 PI7
108 PI8
109 PI9
110 PI10
111 PI11
112 PI12
113 PI13
76 PI14
75 PI15
74
73
72
71
5
PJ0
PJ1
PJ2
PJ3
PJ4
89 VSS_HV_ADC0
90 VDD_HV_ADC0
98 VSS_HV_ADC1
99 VDD_HV_ADC1
151 P5V_MCU
124 P5V_MCU
85 P5V_MCU
59 P5V_MCU
27 P5V_MCU
6 P5V_MCU
150
123
86
57
28
7
152 P1V2_MCU
54 P1V2_MCU
31 P1V2_MCU
153 VSS_LV_153
55 VSS_LV_55
30 VSS_LV_30
XTAL
EXTAL
56
58
RESET
TMS
TCK
29
148
155
VDD_BV
32
26
PA[0]
PA[1]
PA[2]
PA[3]
PA[4]
PA[5]
PA[6]
PA[7]
PA[8]
PA[9]
PA[10]
PA[11]
PA[12]
PA[13]
PA[14]
PA[15]
PF[0]
PF[1]
PF[2]
PF[3]
PF[4]
PF[5]
PF[6]
PF[7]
PF[8]
PF[9]
PF[10]
PF[11]
PF[12]
PF[13]
PF[14]
PF[15]
PB[0]
PB[1]
PB[2]
PB[3]
PB[4]
PB[5]
PB[6]
PB[7]
PB[8]
PB[9]
PB[10]
PB[11]
PB[12]
PB[13]
PB[14]
PB[15]
PG[0]
PG[1]
PG[2]
PG[3]
PG[4]
PG[5]
PG[6]
PG[7]
PG[8]
PG[9]
PG[10]
PG[11]
PG[12]
PG[13]
PG[14]
PG[15]
PC[0]
PC[1]
PC[2]
PC[3]
PC[4]
PC[5]
PC[6]
PC[7]
PC[8]
PC[9]
PC[10]
PC[11]
PC[12]
PC[13]
PC[14]
PC[15]
PH[0]
PH[1]
PH[2]
PH[3]
PH[4]
PH[5]
PH[6]
PH[7]
PH[8]
PH[11]
PH[12]
PH[13]
PH[14]
PH[15]
PD[0]
PD[1]
PD[2]
PD[3]
PD[4]
PD[5]
PD[6]
PD[7]
PD[8]
PD[9]
PD[10]
PD[11]
PD[12]
PD[13]
PD[14]
PD[15]
PE[0]
PE[1]
PE[2]
PE[3]
PE[4]
PE[5]
PE[6]
PE[7]
PE[8]
PE[9]
PE[10]
PE[11]
PE[12]
PE[13]
PE[14]
PE[15]
XTAL
EXTAL
RESET
PH[10]
PH[9]
PJ 1
PJ 3
PI[0]
PI[1]
PI[2]
PI[3]
PI[4]
PI[5]
PI[6]
PI[7]
PI[8]
PI[9]
PI[10]
PI[11]
PI[12]
PI[13]
PI[14]
PI[15]
PJ[0]
PJ[1]
PJ[2]
PJ[3]
PJ[4]
VSS_HV_ADC0
VDD_HV_ADC0
VSS_HV_ADR1
VDD_HV_ADR1
VDD_HV_FLA0
VDD_HV_IO0_E1
VDD_HV_IO0_S3
VDD_HV_OSC0REG0
VDD_HV_FLA1
VDD_HV_IO0_W1
VSS_HV_IO0_N0
VSS_HV_IO0_E0
VSS_HV_IO0_S2
VSS_HV_IO0_S0
VSS_HV_IO0_W0
VSS_HV_IO0_W1
VDD_LV_FLA0
VDD_LV_PLL0
VDD_LV_COR0_W0
VDD_BV_FLA1COR0
VSS_LV_COR0_N0
VSS_LV_PLL0
VSS_26
VSS_LV_FLA1
63 PF0
64 PF1
65 PF2
66 PF3
67 PF4
68 PF5
69 PF6
70 PF7
42 PF8
41 PF9
46 PF10
47 PF11
43 PF12
49 PF13
126 PF14
125 PF15
R12
V_DBUG
C12
0Ohm
C14
C13
J9
PB5
RESET
PC1
TCKOUT
TMS
PC0
JCOMP
P12V
117 PH0
118 PH1
119 PH2
120 PH3
162 PH4
163 PH5
164 PH6
165 PH7
166 PH8
140 PH11
141 PH12
9 PH13
10 PH14
8 PH15
R16
VCONN
J5
2
4
6
8
10
12
14
GND
TDI
GND
TDO
GND
TCK
NC
EVTI
~RESET TMS
GND
VDDE7
~RDY JCOMP
TMS
JCOMP
JTAG
4.7uF 0.1uF 0.01uF
122 PG0
121 PG1
16 PG2
15 PG3
14 PG4
13 PG5
38 PG6
37 PG7
34 PG8
33 PG9
138 PG10
139 PG11
116 PG12
115 PG13
134 PG14
135 PG15
J6
NEXUS CONNECTOR(MICTOR)
2
RSVD2
RSVD1
4
RSVD4
RSVD3
6
VEN_IO0 CLKOUT
8
VEN_IO2 VEN_IO3
10
EVTI
RESET
12
VREF
TDO
14
RDY
VEN_IO4
16
MDO7
TCK
18
MDO6
TMS
20
MDO5
TDI
22
MDO4
TRST
24
MDO3
VEN_IO1
26
MDO2
TOOL_IO3
28
MDO1
TOOL_IO2
30
MDO0
TOOL_IO1
32
EVTO
UBATT
34
MCKO
UBATT
36
TOOL_IO0 MSEO1
38
MSEO0
VALTREF
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
10K
172 PI0
171 PI1
170 PI2
169 PI3
143 PI4
142 PI5
11 PI6
12 PI7
108 PI8
109 PI9
110 PI10
111 PI11
112 PI12
113 PI13
76 PI14
75 PI15
74
73
72
71
5
1
PC0
3
PC1
TCKOUT 5
7
EVTI
RESET 9
VCONN 11
13
R13
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PA8
PA9
PA10
PA11
PA12
PA13
PA14
PA15
PA0
0Ohm
VCONN
EVTI
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PC8
PC9
PC10
PC11
PC12
PC13
PC14
PC15
G1
G2
G3
G4
G5
0.33uF
2
4
6
39
40
41
42
43
C49
U2
R8
4.7K
C19
0.1uF
R11
510 Ohm
R9
4.7K
R10
RESET
U5
SN74LVC1G08
1
A
RESET_MB 2
B
3
PJ0
PJ1
PJ2
PJ3
PJ4
Y
GND VCC
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
PE8
PE9
PE10
PE11
PE12
PE13
PE14
PE15
RED LED
D3
P5V
P5V P5V
4
3
4
1
5
U4
RSTLED
4.7K
VCC
MR RESET
2
J13
RESET
2X1 HEADER
GND
ADM6315-26D3ARTZ
P5V
RESET CIRCUIT
89 VSS_HV_ADC0
90 VDD_HV_ADC0
98 VSS_HV_ADC1
99 VDD_HV_ADC1
151 P5V_MCU
124 P5V_MCU
85 P5V_MCU
59 P5V_MCU
27 P5V_MCU
6 P5V_MCU
150
123
86
57
28
7
1
J15
153 VSS_LV_153
55 VSS_LV_55
30 VSS_LV_30
BOLERO_176_2
P1V2
2X1 HEADER
CT1
CT2
J11
5
2
152 P1V2_MCU
54 P1V2_MCU
31 P1V2_MCU
PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
PG8
PG9
PG10
PG11
PG12
PG13
PG14
PG15
PI0
PI1
PI2
PI3
PI4
PI5
PI6
PI7
PI8
PI9
PI10
PI11
PI12
PI13
PI14
PI15
P2 DO NOT POPULATE
SMA CONNECTOR
EXTAL
CLK_EXT_EN
4
C30
470pF
C47 C48
24
19
17
114
51
146
147
128
129
130
131
132
53
52
50
48
3
C29
0.1uF
C45 C46
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PA8
PA9
PA10
PA11
PA12
PA13
PA14
PA15
1
C28
470pF
C44
C27
0.1uF
63 PF0
64 PF1
65 PF2
66 PF3
67 PF4
68 PF5
69 PF6
70 PF7
42 PF8
41 PF9
46 PF10
47 PF11
43 PF12
49 PF13
126 PF14
125 PF15
2
C26
470pF
PF[0]
PF[1]
PF[2]
PF[3]
PF[4]
PF[5]
PF[6]
PF[7]
PF[8]
PF[9]
PF[10]
PF[11]
PF[12]
PF[13]
PF[14]
PF[15]
2
C25
0.1uF
PA[0]
PA[1]
PA[2]
PA[3]
PA[4]
PA[5]
PA[6]
PA[7]
PA[8]
PA[9]
PA[10]
PA[11]
PA[12]
PA[13]
PA[14]
PA[15]
1
C24
470pF
U1
1
P1V2_MCU
P5V_MCU
24
19
17
114
51
146
147
128
129
130
131
132
53
52
50
48
2
C23
0.1uF
C22
470pF
C21
0.1uF
C20
470pF
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PA8
PA9
PA10
PA11
PA12
PA13
PA14
PA15
1
3
5
PORT_J
PORT_I
9-PIN-HEADER
P5V_MCU
J19
PJ0
PJ2
PJ4
2XAMP120
2XAMP120.Sch
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PA8
PA9
PA10
PA11
PA12
PA13
PA14
PA15
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PB10
PB11
PB12
PB13
PB14
PB15
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PC8
PC9
PC10
PC11
PC12
PC13
PC14
PC15
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
PD9
PD10
PD11
PD12
PD13
PD14
PD15
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
PE8
PE9
PE10
PE11
PE12
PE13
PE14
PE15
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7
PF8
PF9
PF10
PF11
PF12
PF13
PF14
PF15
PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
PG8
PG9
PG10
PG11
PG12
PG13
PG14
PG15
PH0
PH1
PH2
PH3
PH4
PH5
PH6
PH7
PH8
PH9
PH10
PH11
PH12
PH13
PH14
PH15
PI0
PI1
PI2
PI3
PI4
PI5
PI6
PI7
PI8
PI9
PI10
PI11
PI12
PI13
PI14
PI15
PJ0
PJ1
PJ2
PJ3
PJ4
EVTI
TMS
TCKOUT
RESET_MB
RESET
P12V
P5V
P3V3
P1V2
GND
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PB10
PB11
PB12
PB13
PB14
PB15
Reference schematic
30/34
Figure 16. Typical application schematic of SPC560B64-LQFP176
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
PD9
PD10
PD11
PD12
PD13
PD14
PD15
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7
PF8
PF9
PF10
PF11
PF12
PF13
PF14
PF15
PH0
PH1
PH2
PH3
PH4
PH5
PH6
PH7
PH8
PH9
PH10
PH11
PH12
PH13
PH14
PH15
PJ0
PJ1
PJ2
PJ3
PJ4
EVTI
TMS
TCKOUT
RESET_MB
RESET
P12V
P5V
P3V3
P1V2
R14
100R
DO NOT POPULATE
CT3
GAPGRI00361
AN3024
R11
V_DBUG
0Ohm
C12
C13
C14
4.7uF
0.1uF
0.01uF
1
3
P5V
1
FUSE
R1
2
D2
ORANGE
510Ohm
+ C1
10uF
C2
0.1uF
5V LED
SMBJ5339B
VDD5B_CFLA_CORE
1
P5V_MCU
2
3
P3V3
4
P1V2_MCU
AVDDSUPPLY 5
6
AVSSSUPPLY
7
J12
TP1 TP2 TP3 TP4
GND GND GND GND
P12V
R12
VCONN
10K
EVTI
VCONN
7-PIN-HEADER
39
40
41
42
43
6
4
2
D1
TMS
JCOMP
G1
G2
G3
G4
G5
POWER SW
J6
NEXUS CONNECTOR(MICTOR)
2
RSVD1
RSVD2
4
RSVD3
RSVD4
6
CLKOUT
VEN_IO0
8
VEN_IO2
VEN_IO3
10
EVTI
RESET
12
VREF
TDO
14
VEN_IO4
RDY
16
MDO7
TCK
18
MDO6
TMS
20
MDO5
TDI
22
TRST
MDO4
24
VEN_IO1
MDO3
26
TOOL_IO3
MDO2
28
MDO1
TOOL_IO2
30
TOOL_IO1
MDO0
32
EVTO
UBATT
34
UBATT
MCKO
36
MSEO1
TOOL_IO0
38
VALTREF
MSEO0
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
TCKOUT
TMS
PC0
JCOMP
5
K1
2
4
6
8
10
12
14
GND
TDI
TDO
GND
GND
TCK
NC
EVTI
~RESET
TMS
VDDE7
GND
~RDY
JCOMP
JTAG
RESET
PC1
P1
1
P1
+
1
+
2
2
POWER 2-BLOCK
POWER 2-BLOCK
J5
1
PC0
PC1
3
TCKOUT 5
7
EVTI
9
RESET
VCONN 11
13
AN3024
Figure 17. Typical application schematic of SPC560D40-LQFP100
P5V_MCU
C23
0.1uF
C25
0.1uF
C26
470pF
C27
0.1uF
P5V_MCU
C28
470pF
C29
0.1uF
C31
0.1uF
C30
470pF
P5V_MCU
P1V2_MCU
C34
470pF
C35
0.1uF
C44
C45
C46
1nF 0.33uF
C47
C48
C49
1nF 0.33uF
1nF
P5V_MCU
1
J17
2
V_DBUG
J16
VDD5B_CFLA_CORE
2
C51
C50
3
0.1uF
470pF
P5V
V_DBUG
R6
0805
DO NOT POP
1
J7
J8
2 PA9
FAB
2 PA8
ABS0
3
R5
10k
P5V_MCU
FB1
AVDDSUPPLY
R21
10k
R7
10k
10uF
C3
0.1 uF
AVSSSUPPLY
EVTI
JCOMP
C4
R22
0805
DO NOT POP
FB2
FERRITE BEAD
Do not Populate
R3
10k
V_DBUG
FERRITE BEAD
R4
10k
1
R2
10k
J14
2X1 HEADER
P5V_MCU
P3V3
P5V
P5V
1
P5V
3
C33
0.1uF
0.33uF
3
Doc ID 16127 Rev 5
C32
470pF
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PC8
PC9
PC10
PC11
PC12
PC13
PC14
PC15
87
82
78
77
92
91
25
26
99
2
22
21
97
98
3
4
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
PD9
PD10
PD11
PD12
PD13
PD14
PD15
41
42
43
44
45
46
47
48
49
56
57
58
60
62
64
66
EXTAL
XTAL
36
34
R17
4.7K
U1
PA[0]_eMIOS0_CLKOUT
PA[1]_eMIOS1_NMI
PA[2]_eMIOS2_ABS[1]
PA[3]_eMIOS3_TXD_5
PA[4]_eMIOS4_RXD_5
PA[5]_eMIOS5_TXD_4
PA[6]_eMIOS6_RXD_4
PA[7]_eMIOS7_TXD_3
PA[8]_eMIOS8_RXD_3 _ABS[0]
PA[9]_eMIOS9_FAB
PA[10]_eMIOS10_SDA_0
PA[11]_eMIOS11_SCL_0
PA[12]_SIN_0
PA[13]_SOUT_0
PA[14]_SCK_0_PCS_0.0
PA[15]_PCS_0.0 _SCK_0
PB[0]_CNTX_0
PB[1]_CNRX_0
PB[2]_TXD_0_SDA_0
PB[3]_RXD_0_SCL_0
PB[4]_AN0
PB[5]_AN1
PB[6]_AN2
PB[7]_AN3
PB[8]_XTAL32_AN16
PB[9]_EXTAL32_AN17
PB[10]_AN18
PB[11]_eMIOS3_AN19_PCS_0.0
PB[12]_eMIOS4_AN32_PCS_1.0
PB[13]_eMIOS5_AN33_PCS_2.0
PB[14]_eMIOS6_AN34_PCS_3.0
PB[15]_eMIOS7_AN35_PCS_4.0
PC[0]_TDI
PE[0]_eMIOS16_CNRX_5
PC[1]_TDO
PE[1]_eMIOS17_CNTX_5
PC[2]_SCK_1_CNTX_4
PE[2]_eMIOS18_SIN_1
PC[3]_PCS_0.1_CNRX_4_CNRX_1
PE[3]_eMIOS19_SOUT_1
PC[4]_SIN_1_CNRX_3
PE[4]_eMIOS20_SCK_1
PC[5]_SOUT_1 _CNTX_3
PE[5]_eMIOS21_PCS_0.1_MA2
PC[6]_TXD_1
PE[6]_eMIOS22_PCS_3.0_MA1
PC[7]_RXD_1
PE[7]_eMIOS23_PCS_2.0_MA0
PC[8]_TXD_2
PE[8]_CNTX_2_eMIOS22_CNTX_3
PC[9]_RXD_2
PE[9]_CNRX_2_eMIOS23_CNRX_3
PE[10]_TXD_3 _PCS_3.1
PC[10]_CNTX_1_CNTX_4
PC[11]_CNRX_1_CNRX_4
PE[11]_RXD_3 _PCS_4.1
PC[12]_eMIOS12_SIN_2
PE[12]_SIN_2_eMIOS47
PC[13]_eMIOS13_SOUT_2
PC[14]_eMIOS14_SCK_2
TEST_VPP
PC[15]_eMIOS15_PCS_0.2
RESET
TMS
PD[0]_AN4
TCK
PD[1]_AN5
VDD5_IO_W0
PD[2]_AN6
PD[3]_AN7
VDD5_IO_S0
PD[4]_AN8
VDD5_IO_E0
VDD5_IO_N0
PD[5]_AN9
PD[6]_AN10
VDD12_CORE_W0
VDD12_CORE_S0
PD[7]_AN11
PD[8]_AN12
VDD12_CORE_N0
VDD5B_CFLA_CORE
PD[9]_AN13
PD[10]_AN14
AVDDSUPPLY
PD[11]_AN15
PD[12]_PCS_5.0_AN20_eMIOS24
VSS5_IO_W0
PD[13]_PCS_0.1_AN25_eMIOS25
VSS5_IO_S0
PD[14]_PCS_1.1_AN26_eMIOS26
VSS5_IO_N0
PD[15]_PCS_2.1_AN27_eMIOS27
VSS12_CORE_W0
VSS12_CORE_S0
EXTAL
VSS12_CORE_N0
VSS5_IO_COMP_E0
XTAL
AVSSSUPPLY
BOLERO 100LQFP
23
24
100
1
50
53
54
55
39
38
40
59
61
63
65
67
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PB10
PB11
PB12
PB13
PB14
PB15
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PA8
PA9
PA10
PA11
PA12
PA13
PA14
PA15
12
7
5
68
29
79
80
71
72
73
74
75
31
30
28
27
6
8
89
90
93
94
95
96
9
10
11
13
76
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
PE8
PE9
PE10
PE11
PE12
14
17
81
88
RESET
TMS
TCK
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PC8
PC9
PC10
PC11
PC12
PC13
PC14
PC15
87
82
78
77
92
91
25
26
99
2
22
21
97
98
3
4
15
37
70
84
19
32
85
20
52
P5V_MCU
P5V_MCU
P5V_MCU
P5V_MCU
P1V2_MCU
P1V2_MCU
P1V2_MCU
VDD5B_CFLA_CORE
AVDDSUPPLY
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
PD9
PD10
PD11
PD12
PD13
PD14
PD15
41
42
43
44
45
46
47
48
49
56
57
58
60
62
64
66
EXTAL
XTAL
36
34
16
35
83
18
33
86
69
51 AVSSSUPPLY
U2
PA[0]_eMIOS0_CLKOUT
PA[1]_eMIOS1_NMI
PA[2]_eMIOS2_ABS[1]
PA[3]_eMIOS3_TXD_5
PA[4]_eMIOS4_RXD_5
PA[5]_eMIOS5_TXD_4
PA[6]_eMIOS6_RXD_4
PA[7]_eMIOS7_TXD_3
PA[8]_eMIOS8_RXD_3 _ABS[0]
PA[9]_eMIOS9_FAB
PA[10]_eMIOS10_SDA_0
PA[11]_eMIOS11_SCL_0
PA[12]_SIN_0
PA[13]_SOUT_0
PA[14]_SCK_0_PCS_0.0
PA[15]_PCS_0.0 _SCK_0
PB[0]_CNTX_0
PB[1]_CNRX_0
PB[2]_TXD_0_SDA_0
PB[3]_RXD_0_SCL_0
PB[4]_AN0
PB[5]_AN1
PB[6]_AN2
PB[7]_AN3
PB[8]_XTAL32_AN16
PB[9]_EXTAL32_AN17
PB[10]_AN18
PB[11]_eMIOS3_AN19_PCS_0.0
PB[12]_eMIOS4_AN32_PCS_1.0
PB[13]_eMIOS5_AN33_PCS_2.0
PB[14]_eMIOS6_AN34_PCS_3.0
PB[15]_eMIOS7_AN35_PCS_4.0
PC[0]_TDI
PE[0]_eMIOS16_CNRX_5
PC[1]_TDO
PE[1]_eMIOS17_CNTX_5
PE[2]_eMIOS18_SIN_1
PC[2]_SCK_1_CNTX_4
PE[3]_eMIOS19_SOUT_1
PC[3]_PCS_0.1_CNRX_4_CNRX_1
PC[4]_SIN_1_CNRX_3
PE[4]_eMIOS20_SCK_1
PC[5]_SOUT_1 _CNTX_3
PE[5]_eMIOS21_PCS_0.1_MA2
PC[6]_TXD_1
PE[6]_eMIOS22_PCS_3.0_MA1
PC[7]_RXD_1
PE[7]_eMIOS23_PCS_2.0_MA0
PC[8]_TXD_2
PE[8]_CNTX_2_eMIOS22_CNTX_3
PC[9]_RXD_2
PE[9]_CNRX_2_eMIOS23_CNRX_3
PC[10]_CNTX_1_CNTX_4
PE[10]_TXD_3 _PCS_3.1
PC[11]_CNRX_1_CNRX_4
PE[11]_RXD_3 _PCS_4.1
PE[12]_SIN_2_eMIOS47
PC[12]_eMIOS12_SIN_2
PC[13]_eMIOS13_SOUT_2
TEST_VPP
PC[14]_eMIOS14_SCK_2
RESET
PC[15]_eMIOS15_PCS_0.2
TMS
PD[0]_AN4
TCK
PD[1]_AN5
PD[2]_AN6
VDD5_IO_W0
PD[3]_AN7
VDD5_IO_S0
PD[4]_AN8
VDD5_IO_E0
PD[5]_AN9
VDD5_IO_N0
PD[6]_AN10
VDD12_CORE_W0
PD[7]_AN11
VDD12_CORE_S0
PD[8]_AN12
VDD12_CORE_N0
VDD5B_CFLA_CORE
PD[9]_AN13
PD[10]_AN14
AVDDSUPPLY
PD[11]_AN15
PD[12]_PCS_5.0_AN20_eMIOS24
VSS5_IO_W0
PD[13]_PCS_0.1_AN25_eMIOS25
VSS5_IO_S0
VSS5_IO_N0
PD[14]_PCS_1.1_AN26_eMIOS26
PD[15]_PCS_2.1_AN27_eMIOS27
VSS12_CORE_W0
VSS12_CORE_S0
EXTAL
VSS12_CORE_N0
XTAL
VSS5_IO_COMP_E0
AVSSSUPPLY
BOLERO 100LQFP
23
24
100
1
50
53
54
55
39
38
40
59
61
63
65
67
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PB10
PB11
PB12
PB13
PB14
PB15
6
8
89
90
93
94
95
96
9
10
11
13
76
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
PE8
PE9
PE10
PE11
PE12
14
17
81
88
RESET
TMS
TCK
15
37
70
84
19
32
85
20
52
P5V_MCU
P5V_MCU
P5V_MCU
P5V_MCU
R8
4.7K
510 Ohm
R16
RESET
U5
SN74LVC1G08
1
C19
0.1uF
R15
R10
4.7K
A
RESET_MB 2
Y
B
3
GND
VCC
4
4
3
1
5
RSTLED
4.7K
VCC
MR RESET
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PA8
PA9
PA10
PA11
PA12
PA13
PA14
PA15
RESET
2X1 HEADER
RESET CIRCUIT
C5
10pF
0 Ohm
J3
3
1
J13
ADM6315-26D3ARTZ
P5V
PB8
PB9
2
GND
Rs1
4
2
32KHz_EN
Rf1
Rs2
0 Ohm
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
PD9
PD10
PD11
PD12
PD13
PD14
PD15
Y2
C6
10pF
32KHz CLOCK CIRCUIT
R9
TCKOUT
P1V2
Rs
0Ohm
J15
2X1 HEADER
XTAL
EXTAL
4
2
C8
10pF
0 Ohm
J10
Rf
1M Ohm
3
1
Y1
DO NOT POPULATE
CLK_EN
P1V2_MCU
NX8045GB-8.000M
TCKOUT
TMS
C9
10pF
VDD5B_CFLA_CORE
AVDDSUPPLY
16
35
83
18
33
86
69
51 AVSSSUPPLY
U4
CFS206-32.768KDZF-UB
C24
470pF
12
7
5
68
29
79
80
71
72
73
74
75
31
30
28
27
RED LED
D3
P5V
P5V P5V
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PA8
PA9
PA10
PA11
PA12
PA13
PA14
PA15
RESET_MB
RESET
CLOCK CIRCUIT
EXTAL
P2 DO NOT POPULATE
SMA CONNECTOR
1
5
2
J11
CLK_EXT_EN
R14
P12V
P5V
P3V3
P1V2
2XAMP 120
2XAMP 120.Sch
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PA8
PA9
PA10
PA11
PA12
PA13
PA14
PA15
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PB10
PB11
PB12
PB13
PB14
PB15
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
PD9
PD10
PD11
PD12
PD13
PD14
PD15
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PC8
PC9
PC10
PC11
PC12
PC13
PC14
PC15
TCKOUT
TMS
RESET_MB
RESET_OUT_MB
P12V
P5V
P3V3
P1V2
GND
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
PE8
PE9
PE10
PE11
PE12
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PB10
PB11
PB12
PB13
PB14
PB15
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PC8
PC9
PC10
PC11
PC12
PC13
PC14
PC15
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
PE8
PE9
PE10
PE11
PE12
3
C22
470pF
DO NOT POPULATE
C21
0.1uF
4
C20
470pF
P5V_MCU
100R
DO NOT POPULATE
GAPGRI00360
Reference schematic
31/34
Document management
Appendix A
A.1
A.2
AN3024
Document management
Reference documents
●
32-bit MCU family built on the Power Architecture® embedded category for automotive
body electronics applications (SPC560B54x, SPC560B60x and SPC560B64x
datasheet, Doc ID 15131)
●
32-bit MCU family built on the Power Architecture® embedded category for
automotive body electronics applications (SPC560D30x, SPC560D40x datasheet, Doc
ID 16315)
●
32-bit MCU family built on the Power Architecture® embedded category for
automotive body electronics applications (SPC560D30x, SPC560D40x errata sheet,
Doc ID 022965)
●
32-bit MCU family built on the Power Architecture® embedded category for automotive
body electronics applications (SPC560B4x, SPC560B5x, SPC560C4x, SPC560C5x
datasheet, Doc ID 14619)
●
32-bit MCU family built on the Power Architecture® embedded category for automotive
body electronics applications (SPC560B4x/50 – SPC560C4x/50 errata sheet,
Doc ID 15844)
Acronyms
Table 8.
Acronyms
Acronym
ADC
Analog-to-digital converter
BAM
Boot assist mode
CRC
Cyclic redundancy check
EMC
Electromagnetic compatibility
EMI
Electromagnetic interference
ESL
Equivalent series inductance
ESR
Equivalent series resistance
LVD
Low voltage detector
NVUSRO
32/34
Name
Non-volatile user options register
POR
Power-on reset
SIUL
System integration unit lite
TCK
Test clock input
TDI
Test data input
TDO
Test data output
TMS
Test mode select
Doc ID 16127 Rev 5
AN3024
Revision history
Revision history
Table 9.
Document revision history
Date
Revision
Changes
22-Sep-2009
1
Initial release.
03-Sep-2010
2
Editorial and formatting changes throughout document
Updated Section 1.3: Current consumption and voltage regulator
and Section 7.5: I/O characteristic in STANDBY mode
Added Section 8: EMC guidelines
Updated Table 8: Acronyms
04-Jun-2012
3
Added Section 4.3.1: Some recommended crystal.
17-Dec-2012
4
Added following RPN:
-SPC560B54/6x
-SPC560D30x/40x
Updated entire document.
17-Sep-2013
5
Updated Disclaimer.
Doc ID 16127 Rev 5
33/34
AN3024
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Doc ID 16127 Rev 5