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ECE 2201
LAB 4 - CMOS Circuits PRELAB
P1. In the circuit of Fig. P4-1, estimate the propagation delays tPLH and tPHL. Assume
Wp
W
A
k' n n  k' p
 2.0E  3 2
Ln
Lp
V
+
+5V
CL
100pF
+
+5V
VIN
-
0V
Figure P4-1.
1
+
VOUT
-
EE2201 - LAB 4
CMOS Circuits and Applications:
iD-vDS Characteristic
Digital Switch Applications: CMOS Logic Inverter
Analog Switch Applications: Low Dostortion Audio Mute
PURPOSE:
The purpose of this laboratory assignment is to investigate the P-channel enhancement mode
MOSFET and complementary (both P- and N-channel MOSFET) circuits. Upon completion of
this lab you should be able to:
 Recognize the cutoff and triode regions of operation for the P-channel MOSFET.
 Characterize the relationship between on resistance rDS and gate drive voltage vGS in the
resistive portion of the triode region.
 Extract MOSFET parameters k’p(W/L) and threshold voltage Vt from triode region
measurements.
 Apply the P-and N-channel MOSFET in the digital application of a CMOS logic inverter and
measure the propagation delay for high-to-low and low-to-high transition.
 Apply the P-and N-channel MOSFET in a transmission gate as an analog switch in an audio
mute application.
 Use the effect of supply voltage on propagation delay to develop a voltage controlled
oscillator (VCO).
MATERIALS:





ECE Lab Kit
DC Power Supply
DVM
Function Generator
Oscilloscope
NOTE: Be sure to record ALL results in your laboratory notebook.
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P-CHANNEL ENHANCEMENT MODE MOSFET: iD-vDS CHARACTERISTIC
L1. Build the MOSFET circuit shown in Fig. 3-1, using the MC14007 MOSFET array. By
using different values for resistor R1, you will measure the drain current iD as the MOSFET
drain-source voltage vDS varies from 0 to +10V. For this part, the gate-source voltage vGS
will be fixed at -5V.
Note: Use the fixed +5V output of your bench power supply for vGS; adjust one of the
variable supplies to obtain the +10V rail.
Note: Resistor RP is solely for protection of the high-impedance gate terminal; since iG=0
under normal conditions, there will be no voltage drop across RP and vGS will be -5V.
M1
VGS 1/6
+
+
+10
iG
14
6
RP
1k
+
VDS
iD
13
iL
+
+5V
V
iR
R1
+
VR1
-
Figure 3-1.
L2. Vary R1 to cover a range of drain-source voltages using the values: 100Ω, 750Ω,1kΩ,
1.2kΩ (use 1kΩ + 200Ω in series), 1.5kΩ, 2kΩ, 3kΩ,10kΩ, 1MΩ. In each case, measure
(using the DVM) and record the drain-source voltage vDS and the voltage drop vR1 across
resistor R1. Calculate the MOSFET drain current iD from
v
(1)
iD  R1
R1
Note that Eq. (1) assumes iL is negligible, so that iD≈iR.
L3. Plot the vDS-iD characteristic (current iD on the vertical axis, as a function of vDS). Note the
saturation and triode operating regions.
3
IMPROVING ON RESISTANCE rDS BY INCREASING GATE DRIVE vGS
L5. Modify the circuit of Fig. 3-1 as shown in Fig. 3-2, to use the DVM in ohmmeter mode to
measure the on resistance rDS directly. As you vary vGS, you will see variation in the on
resistance.
NOTE: Unfortunately, this part requires lots of DVM lead swapping and button clicking –
you need to measure the on resistance rDS between the drain and source terminals, but also
the applied gate-source voltage vGS.
ADDITIONAL NOTE: For this part, it’s very important to leave the DVM on the 20V/20kΩ
range throughout. Changing the resistance range changes the current the DVM uses to
measure resistance, which affects the resistance measured in the triode region. The problem:
in the 2kΩ range, the DVM injects a larger current than in the 20kΩ range. This causes a
larger value of vDS, violating the “small vDS” condition for the resistive portion of the triode
region. So, even though normal practice would be to use the 2kΩ range when measuring rDS
less than 2kΩ (for better measurement resolution), in this case, we’ll live with lower
resolution so as not to violate the “small vDS” condition.
L6. Starting with vGS ≈ -5V, measure rDS and vGS. The resistance rDS should be around a few
hundred ohms (which will read a few tenths of a kΩ with the DVM on the 20kΩ range).
Reduce the magnitude of gate drive (make vGS less negative) in steps of about 0.5V,
measuring rDS and vGS at each step. As vGS gets closer to the threshold voltage, you should
see rDS increase. When vGS gets very close to the threshold voltage Vt, rDS will start
increasing rapidly. Take a few data points for vGS with rDS about 2kΩ, 5kΩ, and 10kΩ. You
should end up with about 10 data points. Plot rDS as a function of vGS .
+
-
+
VGS
+
14
DV
6
-
RP
1k
M1
13
1/6
Figure 3-2.
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DIGITAL SWITCH APPLICATIONS: CMOS LOGIC INVERTER
L7. The goal of this circuit is the same as the passive load inverter from Lab 3: to take an input
voltages of either 0V (logic low) or +5V (logic high) and provide at the output a voltage
corresponding to the opposite logic level.
DC Characteristics
L8. Build the CMOS logic inverter shown in Fig. 3-3. Adjust the function generator (using the
offset knob) so that vIN is a 100kHz, 0 to +5V square wave.
L9. Set up the oscilloscope to view the gate input vIN on channel 1 at 2V/div, and vOUT on
channel 2 at 2V/div. Set both inputs to zero (GND) and adjust the vertical position of each
trace so that the input is on the upper half of the display, and the output on the lower half.
Once the vertical position is adjusted correctly, when viewing the voltage waveforms, be
sure both channels are on DC coupling.
Set up the time base of the scope to show at least one full cycle of the square wave.
L10. Sketch the input and output waveforms as shown on the oscilloscope. Measure the high and
low voltage levels at the logic output. In particular, note how well the output high and low
logic levels reproduce the input levels. How well does this circuit meet the functional goal
expressed in part L7?
14
+
M1
1/6
6
+5
RP
1k
13
8
+5
0
+
6
-
M2
VIN
1/6
7
Fig. 3-3
5
AC Characteristics
L11. As stated in the previous section, the goal of this circuit is provide at the output a logic level
corresponding to the opposite of the input. Ideally, if the input changes state, the output
would change instantaneously; in practice, there will be a delay which is referred to as the
propagation delay.
L12. Add a 100pF load capacitance the logic inverter, as shown in Fig. 3-4. This capacitance
corresponds to the capacitive load that the output might “see” due to the capacitance of a PC
board trace, bus wiring, or other logic gate inputs.
L13. Sketch the input and output waveforms. Compare to the waveforms from part L10, with no
capacitive load.
L14. Measure the high-to-low (tPHL) and low-to-high (tPLH) propagation delays. Measurement
hint: for the high-to-low measurement, trigger the scope off the rising edge of the input,
expand the horizontal scale to get a good look at the delay, and use the time cursors to
measure the delay time. For the low-to-high measurement, trigger off the falling edge of the
input.
L15. How well does this circuit meet the “instantaneous” functional goal expressed in section
L11?
14
+
M1
1/6
6
+5
RP
1k
13
8
+5
0
+
6
-
M2
VIN
1/6
CL
100pF
7
Figure 3-4.
6
+
VOUT
-
IMPROVED AUDIO MUTE SWITCH (CMOS TRANSMISSION GATE)
L16. As in Lab 3, our goal is a switch with two states: one state that passes an audio signal
undistorted to a speaker, another state that blocks the signal completely. In lab 3, with only
an N-channel device, significant distortion was observed since the switch “on” resistance
varied as a function of signal voltage. In this lab, by placing a P-channel device in parallel,
the total resistance combination remains relatively constant as the signal voltage varies.
Since the P-channel device requires an inverted gate drive signal, you will use the CMOS
inverter from the previous section to develop the required gate drive from the control logic
signal VCTL.
L17. Build the circuit shown in Figure 3-6. Note that you will need to use two of the MC14007
MOSFETs that have uncommitted source terminals, allowing a separate substrate tie to –
10V (for the N-channel MOSFET) and +10V (for the P-channel MOSFET). This ensures
that the body-source and body-drain diodes remain reverse biased at all times, for all
possible signal voltages.
Fake the logic control “switch” with a length of wire. Set up the +10V and –10V rails using
the two adjustable supplies of your bench power supply. Set up the function generator so
that vIN is a 2V peak-to-peak sine wave at about 1kHz.
L18. Listen to the speaker output with the “switch” in each position. Look at vIN and vOUT on the
oscilloscope. In particular, sketch the shape of the output waveform when the “switch” is on
and off. How well does this circuit meet the functional goal expressed in part L16?
7
+10
SWITCH
10k
VCTL
-
M3
3
1/6
4
5
+
VOUT
-
+
7
vIN
-
-
+10
14
+10
M1
14
11
1/6
6
M4
13
VCTL
VCTL 1/6
8
6
M2
1/6
12
7
Figure 3-6.
8
10
SPEAKER
(8Ω
2:1 ANALOG MULTIPLEXER
L19. The goal of this circuit is to switch one of two analog input signals to an output, with the
choice of signal routed to the output determined by a digital control signal.
L20. Keeping your wiring the same for MOSFETs M1-M4, build the circuit shown in Figure 3-7.
(Note that the 8Ω speaker is gone; in this circuit, we won’t be concerned with driving a low
impedance load – just look at the output waveform on the oscilloscope). Since there is only
one function generator per bench, use a potentiometer to generate the second “signal” input
to the multiplexer. By adjusting the potentiometer, the DC level of vIN2 can be changed,
allowing you to see whether the output is changing or not.
Again, fake the logic control “switch” with a length of wire.
L21. Observe the output voltage on the oscilloscope with the “switch” in each position. Record
which state of the VCTL logic signal correspond with which input being routed to the
output, and why. How well does this circuit meet the functional goal expressed in part L19?
L22. [Optional - If there’s an empty bench next to you in lab] Instead of the “switch” (manually
operated, and therefore slow) use an extra function generator to generate the VCTL signal.
Set VCTL to be a –10V to +10V square wave, at a frequency of 10kHz. Set the time base
on the oscilloscope to 100µsec/div, so that the scope display shows several cycles of the
mutliplexer switching. While observing vOUT on the scope, change the vIN1 and vIN2 inputs.
On the output, note how when you’re changing one of the inputs, the output changes
accordingly during the time that input is switched to the output, but during the “other”
output time, the waveform is unchanged.
9
+10V
SWITCH
10k
VCT
M3
1/6 MC14007
v IN1
-10V
3
4
5
+
v IN1
7
-10V
-
+10V
14
+10V
M1
1/6 MC14007
14
11
6
VCT
13
M4
1/6 MC14007
VCT
M5
1/6 MC14007
8
6
M2
1/6 MC14007
12
10
10
9
12
7
-10V
7
-10V
+10V
+10V
14
100k
TRIMPO
v IN2
1
-10V
M6
1/6 MC14007
Figure 3-7
10
2
3
V OUT
VOLTAGE CONTROLLED OSCILLATOR (VCO)
L23. An important functional block in communication circuits is the voltage controlled oscillator,
or VCO. This block is an oscillator for which the output frequency is controlled by a
voltage.
One simple type of VCO is the ring oscillator, shown in Fig. 3.8. The ring oscillator is
simply a string of inverters connected in a ring. With an odd number of inversions, there is
no stable state for vOUT, and the result (after any power-up transients die out) is a single
transition “chasing itself” around the ring. Assuming the rising and falling propagation
delay times are equal to tPD, the resulting frequency (for an N stage ring) is simply 1/NtPD.
As we have seen, the propagation delay of the CMOS inverter depends on the supply voltage
VDD: a higher VDD increases the gate drive to the MOSFET, reducing rDS, thus reducing
the propagation delay. Since the frequency of the ring oscillator is determined by the
propagation delay, changing VDD should allow us to change the frequency of the waveform
at vOUT.
L24. Build the circuit shown in Fig 3.8.
L25. Measure the frequency of the output waveform at vOUT for VDD=+10V. Measure at
different values of VDD, decreasing in increments of ≈ 1V down to ≈ 3V.
+V DD
M1
1/6 MC14007 14
6
+
M1
1/6 MC14007 11
10
M1
1/6 MC14007 2
3
13
12
1
8
12
5
6
10
3
+VDD
M2 7
1/6 MC14007
M2 9
1/6 MC14007
Fig. 3.8
11
M2 4
1/6 MC14007
VOUT
LAB WRITEUP
P-CHANNEL ENHANCEMENT MODE MOSFET: iD-vDS CHARACTERISTIC
W1. Plot the vDS-iD characteristic (current iD on the vertical axis, as a function of vDS) for the Pchannel MOSFET. Note the saturation and triode operating regions.
W2. Determine the slope of the vDS-iD characteristic near the origin (the resistive part of the
triode operating region). From the slope, determine the value of rDS as ∆vDS/∆iD.
W3. Compare your P-channel results from W1 and W2 to your N-channel results from parts W1
and W2 of lab 3.
IMPROVING ON RESISTANCE rDS BY INCREASING GATE DRIVE vGS
W4.
Plot rDS as a function of vGS. Compare your measured rDS resistance at vGS = -5V to the
value obtained from the slope of the vDS-iD plot in part W2.
W5.
Plot 1/rDS as a function of vGS. Using this plot, extract the MOSFET model parameters
W
and threshold voltage Vtp for the triode region "on" resistance expression:
k' p
L
1
rDS 
(2)
W
k' p
vGS  Vtp
L

W6.

Using your parameters from W5, plot the prediction of the MOSFET rDS model on the
same axes with your measured data from parts W4 and W5. How well does the model
predict the measured data?
W7. Compare your P-channel results from to your N-channel results from parts W3 and W4 of
lab 3.
DIGITAL SWITCH APPLICATIONS: CMOS LOGIC INVERTER
W8. Plot the input and output waveforms (without CL) as shown on the oscilloscope. Indicate
the measured high and low voltage levels of the logic output waveform. In particular, note
how well the output high and low logic levels reproduce the input levels. How well does
this circuit meet the inverter functional goal?
W9. Plot the input and output waveforms with CL. Compare to the waveforms from part W8,
with no capacitive load.
W10. Analysis: Derive equations (in terms of CL and rDS) predicting the high-to-low (tPHL) and
low-to-high (tPLH) propagation delays for this logic gate.
12
W11. Compare the measured high-to-low (tPHL) and low-to-high (tPLH) propagation delays to the
numerical predictions of your analysis in part W9. Also, compare to your results for the
passive load logic inverter from lab 3.
W12. Discussion: How well does this circuit meet the “instantaneous switching” functional goal?
Can you suggest any changes in the circuit that would improve delay performance?
IMPROVED AUDIO MUTE SWITCH (CMOS TRANSMISSION GATE)
W13. Describe (qualitatively) the speaker output with the “switch” in each position.
W14. Plot vIN and vOUT from the oscilloscope for each position of the "switch". Compare to your
result for the N-channel-only switch from lab 3.
W15. Discussion: How well does this circuit meet the functional goal of the analog switch? Can
you suggest any improvements?
2:1 ANALOG MULTIPLEXER
W16. Describe the behavior of the circuit for each state of the VCTL logic signal. Explain which
state of the VCTL logic signal correspond with which input being routed to the output, and
why. How well did this circuit meet the functional goal expressed in part L19? If you were
able to do the optional part, show the input and output waveforms and the VCTL signal.
VOLTAGE CONTROLLED OSCILLATOR (VCO)
W17. Plot your measurements of the frequency of the output waveform at vOUT as a function of
the supply voltage VDD. How well does this circuit perform VCO the functional goal
expressed in part L23?
13