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High Speed Digital Signals
Why Study High Speed Digital Signals
Already at 500-600 MHz microprocessors
Alphas
Pentiums
Higher speeds -> greater data bandwidth required to keep processor busy
Still must deal with black holes
Moving into and out of memory
Slower speed I/O
Can view data bandwidth as
Number of data pins or bits * data rate
VLSI is scaling faster than number of interface pins
Data rate must be increased to meet bandwidth
New Rules
At 500 MHz per pin data rates
Old assumptions and approaches don't work
Must now consider
RLC transmission line analysis
New signal transfer methods
Low excursion signals
Current mode
High Speed Digital Design
Emphasizes behaviour of passive circuit elements
Examines how passive circuit elements
Affect signal propagation
Ringing and reflection
Interaction between signals
Crosstalk
Interactions with the physical world
Electromagnetic interference
Time and Frequency
At low frequencies
Ordinary wire will effectively short two circuits
At high frequencies
Same wire has much to much inductance to function as short
If one plots basic electrical parameters on log scale
Few remain constant for more than 10 to 20 decades
For every electrical parameter
Must consider range over which it is valid
Changes
As move up in frequencies
Ground wire measuring 0.01  at 1 kHz
Measures 1.0  at 1 gHz
Acquires 50  of inductive resistance
Due to skin effect
Knee Frequency
For digital signal
Spectral power density of digital signal
Flat or some decrease upto point called knee frequency
Above knee frequency
Drop off much greater
Define knee frequency
0.5
Fknee 
Trise
Fknee - Frequency below which most of energy in digital pulse concentrated
Trise - Pulse rise time
Important time domain characteristics of any digital signal
Determined primarily by signal's spectral power density below Fknee
Such principle leads to following qualitative properties of digital circuits
 Any circuit that has flat frequency response up to and including Fknee will
pass a digital signal practically undistorted
 Behaviour above Fknee will have little affect on how it processes digital
signals
Can use Fknee as practical upper bound of spectral content in digital signals
Let's see how non-flat frequency response below Fknee will distort signal
500 pf
50 ohm
1 ns
Look at circuit at Fknee
T
1
 r  0.6
2  Fknee C  C
At such frequency capacitor acts like virtual short
Full amplitude of leading edge comes through
XC 
5 ns
25 ns
Over 25 ns time interval - approximately 25 ns
Capacitive reactance increases to 15 
Now have considerable droop
Time and Distance
Electrical signals in conducting wires or circuit traces
Propagate at speed dependent upon surrounding medium
Measured in picosec per inch
Delay increases in proportion to square root of
Dielectric constant of surrounding medium
Medium
Air - Radio Waves
Coax Cable
PCB Outer Trace1
PCB Inner Trace2
Delay (ps/in)
85
129
140-180
180
Dielectric Const
1
2.3
2.8-4.5
4.5
1. Determines if electric field stays within board or goes into air
2. Note: Outer layer signals will always be faster than those on the inner
layers
Distributed vs Lumped
If we look at
Speed of signal with respect to propagation delay through system
Find interesting phenomenon
Can define property called effective length of electrical feature
l
Tr
D
Tr - rise time in ps
D - delay time in ps / in
Consider signal
1 ns rise time - typical for ECL 10K
140 ps/in
Compute electrical length of 7.1 in
What this means is
As signal enters trace and propagates along
Potential not uniform along trace
Reaction of system to incoming pulse
Distributed along trace
We see then
Systems physically small enough to react together
With uniform potential called lumped
Larger systems with non-uniform potential
Called distributed
Classification into lumped vs distributed
Depends upon signal rise time
Rule of thumb
For printed circuit board traces point to point wiring etc
Wiring shorter 1/6 effective length of rising edges
Behaves mostly in lumped fashion
Transmission Lines
At high frequencies
Transmission lines superior to ordinary point to point wiring
Less distortion
Less radiation (EMI)
Less crosstalk
However transmission lines
Require more drive power
Shortcomings of Point to Point Wiring
Signal Distortion
Distributed circuits will ring if unterminated
Lumped circuit may or may not ring
Depends upon Q of circuit
Q gives measure of how quickly signals die out
Assume we've designed lumped circuit
Kept geometries small
Line lengths short
Using series RLC circuit discussed earlier can illustrate point
Compute output voltage across capacitor
Differentiate and find max value
Evaluate solution at that point
We get




Vovershoot
e 
Vstep



4 Q 1 

2
Based upon earlier solution
Have decaying exponential
Maximum overshoot given above
Rule of thumb for perfect step input
Q
% Overshoot
1
2
<0.5
16%
44%
None
Calculating Q
Recall Q given by
L
C
Q
Rs
Assume a wire wrapped system using TTL
For TTL driver
Rs = 30 
C = 15 pF (typical load)
Compute L as follows
Assume round wire suspended above ground plane
  4 H
L   5.08x109  X  ln

  D 
H Height of wire above ground - assume 0.3 in
D Diameter of wire wrap wire - 0.01 in
X Length of wire - assume 4 in for this example
L = 89 nH
From which we get
Q of 2.6
Peak overshoot of 2.0 volts
Assumes VOH or 3.7 V
n 
Fring
1
LC
1

2 LC
Fring = 138 MHz
EMI in Point to Point Wiring
EMI is electromagnetic interference
Wirewrapped (and printed circuit boards as well)
Filled with current loops
Large current loops carrying rapidly changing signals
Functions as very good transmitters
Crosstalk in Point to Point Wiring
Consider the following circuit
Represents two subcircuits within larger system
Loop A
Loop B
Current flowing in Loop A produces magnetic flux
Some flux coupled into Loop B
Coupled signals represent crosstalk
Can compute for this system
Mutual inductance between two parallel wires given as




1 

LM  L
  s 2 
 1   
  h 
LM - Mutual inductance
L - Inductance of single wire
From above 89 nH
s - Separation of two wires
Assume 0.1 in
h - Height above board (ground plane)
Assume 0.2 in
LM = 71 nH
The voltage induced in second loop given by
di
V  LM
dt
di
= maximum value in driving loop
dt
Can show max
di
in above load capacitor given by
dt
. V
di 152

C
dt
Trise 2
V
- Voltage swing
Assume 3.7
Trise - Rise time
Assume 4 ns
C
- Load capacitance
Assume 15 pF
di
= 5.3 x 106 A/sec
dt
V= 374 mV
As we can see
Significant amount of voltage
Using Transmission Lines
Tline > Trise
When should we consider using transmission line techniques
Round trip delay of signal propagating down line
Close to or greater than signal frequency
Reflections of original signal
Delayed by the line propagation time
Will increase settling time relative to signal frequency
High Speed Conduction
Several configurations used for high speed paths
Involve
Discrete wiring
Printed wiring
Geometries
Examine cross sections
Parallel Lines
Twisted Pair
Co-axial Line
Image Line
Micro Strip Line
Twisted
Shielded Pair
Strip Line
Model
Can model incremental section of transmission line as two port device
v
i
+
x
-
i + i
+
v
x
x
v
v
i
i
+
i
v + v
x
distance co-ordinate measured from one end of the line
increment of x co-ordinate
potential at point x of line
increment of potential over distance x
current in conductor at point x
increment of current between wires
due to both conductive and capacitance effects in interval x
For infinite transmission line
Electrically we have
L dx
L dx
R dx
R dx
G dx
C dx
G dx
C dx
From above we can write following equations
v x  x   v x   v x    Rxi x   j L xi x 
i x  x   i x   i x   Gx v x   j C x v x 
Divide by x and let dx -> 0
d v x 
  Ri x   j Li x 
dx
d i x 
 G v x   j C v x 
dx
Solving these for separate equations in v and i
d 2 v x 
  R  j L G  j C  v x   0
dx 2
d 2 i x 
  R  j L G  j C i x   0
dx 2
Solutions now become
v x   v1e  x  v2 e  x
i x   i1e  x  i2 e  x
 
 R  j  LG  j  C
 Called propagation constant
With a little bit of math
Can write characteristic impedance of transmission line as
Z0 
V

I
R  jL
G  jC
Lossless Transmission Line
If we let R = G = 0
Transmission line will be purely reactive
Characteristic impedance now becomes
L
C
Z0 
Phase Velocity - inverse of propagation delay
1
p 
LC
Signal attenuation
 0
Transmission line now perfect delay line
Vin
t=length*p
Vin
t=0
Finite Transmission Line
We terminate at source and far end
We now have
-
I0 +
I0
ZS
+
+
+
-
VS
(V0)
+
(V0)
x=0
Using superposition of forward and backward signals
V  V0  V0
I  I 0  I 0
Z0 
V0
V0

I 0  I 0
Let Vs be a sinusoid with frequency 
ZL
x=L
We then have V0 of forms
V0 sin t   
V0 sin t   
Ratio of V/I at load end must equal ZL
V V0  V0
 
 ZL
I
I 0  I 0
V0  V0
V0 V0

Z0 Z0
With a little bit of math we get
ZL 

V0 Z L  Z0

V0 Z L  Z0
-
+
(V0) =(V0)
ZS
+
VS
+
Z0
(V0)
ZL
We call  the reflection coefficient
Observe
V0  V0
Gives measure of percent of incident signal reflected back
Boundary Conditions
Open Line ZL = 
Z  Z0
 L
1
Z L  Z0
Shorted Line ZL = 0
Z  Z0
 L
 1
Z L  Z0
Matched Line ZL = Z0
Z  Z0
 L
0
Z L  Z0
In general
||1
Transient Input
Let's now consider a step input
Analysis
Initial voltage divider between source impedance and line
VZ
V1  s 0
Z s  Z0
Voltage travels down transmission line
Reflects when hits load
V1  loadV1
Reflected wave travels back towards source
V2  source loadV1
Reflected wave re-reflects when it hits source
Reflections die out because  < 1
Terminations
Unterminated
TTL Driver
Low Source Impedance
Rs < Zo -> L < 0
Result - Oscillating output
CMOS Driver
High Source Impedance
Rs > Zo -> L > 0
Result - Buildup waveform
Parallel Termination - End Terminated
When terminating resistance placed at receiving end of transmission line
Called parallel termination
To eliminate reflections
Value must match effective impedance of line
Goal
RS = 0, RL = Z0
Full amplitude input waveform
Reflections damped by terminating resistor
Static power dissipation
0
+
Vs
Vs
Z0
Biased Terminations
R0
R1
C0
R2
(DC balanced)
Z0=R1||R 2
Common implementation
Implement termination as split resistor shown above
VCC
R1
R2
R1 R2
R1  R2
R2
Vth  Vcc
R1  R2
Rth 
Often cannot match line impedance exactly
Resulting reflections affect receiver's noise margin
May be acceptable
Series Termination - Source Terminated
Rs
Goal
RS = Z0, RL = 
R0
Half amplitude input waveform
Reflections at load creates full magnitude
Reflections damped at source
No Static power dissipation
Half the rise time of parallel termination
Select Rs
Z0 - ZOH < Rs < ZO - ZOL
0.5 Vs
Z0
+
Vs
0.5 Vs
Z0
Strengths
Has low power consumption between transients
Can be implemented with one resistor
Weaknesses
Degrades edge rate more per unit of capacitive load
Requires transmission round trip delay to achieve full step level
Diode Clamping
Diode turns on at 0.6 to 1 V limiting reflections
May not respond fast enough
Should look familiar as IC input circuit
Z0
+
Vs
Z0