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Logic Circuit Design Based on MOS-NDR Devices and Circuits Fabricated by CMOS Process Kwang-Jow Gan, Dong-Shong Liang*, Chung-Chih Hsiao, Shih-Yu Wang, Feng-Chang Chiang, Cher-Shiung Tsai, Yaw-Hwang Chen, Shun-Huo Kuo, and Chi-Pin Chen Department of Electronic Engineering, Kun Shan University of Technology, Taiwan, R.O.C. Abstract--We propose a new MOS-NDR device that is composed of the metal-oxide-semiconductor field-effecttransistor (MOS) devices. This device could exhibit the negative differential resistance (NDR) characteristics in the current-voltage characteristics by suitably modulating the MOS parameters. We design a logic circuit which can operate the inverter, NOR, and NAND gates. The devices and circuits are fabricated by the standard 0.35μm CMOS process. and mp4 is cutoff. The second situation: mn1 is saturation, mn2 is saturation, mn3 is from linear to saturation, and mp4 is cutoff. The third situation: mn1 is saturation, mn2 is saturation, mn3 is saturation, and mp4 is cutoff. Finally, the fourth situation: mn1 is saturation, mn2 is linear, mn3 is cutoff, and mp4 is linear until saturation. Vdd 1. INTRODUCTION Functional devices and circuits based on negative differential resistance (NDR) devices have generated substantial research interest owing to their unique NDR characteristic [1]-[2]. Taking advantage of the NDR feature, circuit complexity can be greatly reduced and novel circuit applications have also obtained. Some applications make use of the monostablebistable transition logic element (MOBILE) as a highly functional logic gate [3]-[4]. A MOBILE consists of two NDR devices connected in series and is driven by a suitable bias voltage. The voltage at the output node between the two NDR devices could hold on one of the two possible stable states (low and high, corresponding to “0” and “1”), depending on the relative difference of peak current (IP) between two devices. We propose a MOS-NDR device that is composed of the metal-oxide-semiconductor field-effect-transistor (MOS) devices. Then we design a logic circuit that can operate the inverter, NOR, and NAND function in the same circuit. It is different from the CMOS logic family constructed by NMOS and PMOS devices. Finally, we fabricate the MOS-NDR devices and logic circuits by standard 0.35μm CMOS process. mn1 mn3 mp4 Vgg mn2 Fig. 1 The circuit configuration for a MOS-NDR device. 2. DEVICE STRUCTURE AND OPERATION Figure 1 shows a MOS-NDR device, which is composed of three NMOS devices and one PMOS device. This circuit is derived from a Λ-type topology described in [5]-[6]. This MOS-NDR device can exhibit various NDR current-voltage (I-V) characteristics by choosing appropriate MOS parameters. Figure 2 shows the simulation results by HSPICE program. If the Vgg voltage is fixed at some value, the operation of this MOS-NDR device can be divided into four situations by gradually increasing the bias Vdd. The first situation: mn1 is saturation, mn2 is cutoff, mn3 is linear, Fig2 Simulation result for the MOS-NDR device by HSPICE program. The value of Vgg voltage will affect the I-V curve, especially in its peak current. Figure 3 shows the I-V characteristics, measured by Tektronix 370B, with the Vgg voltage varied from 1.5V to 3.3V, gradually. The width parameters are designed as mn1=5μm, mn2=100μm, mn3=10μm, and mp4=100μm. The length parameters are all fixed at 0.35μm. The I-V characteristic could be divided into three segments as: the first PDR segment, the NDR segment, and the second PDR segment in sequence. 6.0 2.0 Vgg=3.3V 1st PDR 2nd PDR NDR Current (mA) Current (mA) 3.0 Figure 5 shows the measure I-V characteristics of a MOS-NDR device with T1 varying from 0 to 3.3V, gradually. As seen, we can modulate the peak current of the MOS-NDR device through T1 gate. Vgg=3V 1.0 Vgg=2.5V Vgg=2V Vgg=1.5V 0.0 0 0.4 T1 varied from 0V to 3.3V 3.3V 4.0 3V 2.5V 2V 1.5V 1V 2.0 0V 0.8 1.2 1.6 Voltage (V) 0.0 Fig. 3 The measured I-V characteristics for a MOS-NDR devices with different Vgg voltages. 3. LOGIC CIRCUIT DESIGN Our logic circuit design is based on the MOBILE theory. A MOBILE circuit consists of two NDR devices connected in series and is driven by a bias voltage VS. The logic circuit configuration is shown in Fig. 4. T1 is used as the controlled gate. T2 and T3 are the input gates with square wave signal. The width parameters are all 5μm. The upper NDR1 device is treated as a load device to the pull-down NDR2 driver device. When the bias voltage is smaller than twice the peak voltage (2VP), there is one stable point (monostable) in the series circuit. However when the bias voltage is larger than two peak voltages but smaller than two valley voltages (2VV), there is two possible stable points (bistable) that respect the low and high states (corresponding to “0” and “1”), respectively. A small difference between the peak currents of the series-connected NDR devices determines the state of the circuit. 0 0.4 0.8 1.2 1.6 Voltage (V) Fig. 5 Measured I-V characteristics with different T1 voltages. If the IP of the driver is smaller than IP of the load (with T2 or T3 OFF), the circuit switches to the stable point Q corresponding to a high output voltage, as shown in Fig. 6. The operation point Q is located at the second PDR region of the driver’s I-V curve. On the other hand, a bigger peak current (with T2 or T3 ON) of the driver will result in the stable point Q with low output voltage. At this time, the operation point Q is located at the second PDR region of the load’s I-V curve. Therefore, an inverter operation can be obtained at the output node between the two NDR devices. Similarly, if we design the logic function according to the MOBILE theory and truth table, we can obtain the NOR and NAND gate logic operation. I Driver + T2 or T3 VS Driver T1 NDR1 Load Q Q Load Vout T2 NDR2 Driver T3 Out(L) Fig. 4 Configuration of the logic circuit. The circuit shown at upper left corner of Fig. 4 is a MOS-NDR device with parallel connection of a T1 NMOS. The total current ITotal is the sum of the currents through the MOS-NDR and NMOS devices: ITotal=INDR+IMOS. Since IMOS is modulated by the gate voltage (T1), so is ITotal. V Out(H) VS Fig. 6 The MOBILE operation is dependent on the relative difference in the peak current of load and driver devices. 4. EXPERIMENT RESULTS The MOS-NDR devices and logic fabricated by the standard 0.35μm CMOS length parameters for all MOS are fixed at width parameters of the two MOS-NDR circuits process. 0.35μm. devices are The The are designed as mn1=5μm, mn2=100μm, mn3=10μm, and mp4=100μm. The width parameters for T1, T2, and T3 are fixed at 5μm. For the inverter operation, T2 gate is chosen as the input square wave with signal varied from 0 to 2V. The supply voltage VS is fixed at 1.5V that is bigger than 2VP but is small than 2VV voltage. The operation of T1 control gate is cutoff. The Vgg voltages are 3.3V and 2.8V for NDR1 and NDR2, respectively. The inverter operation is shown in Fig. 7. As seen, when the input voltage has reached the low state (0V), the output voltage will be at the high state. On the other hand, when the input voltage has reached the high state (2V), the output voltage must be at the low state. point will be located at the relative “low” level. On the other hand, the peak current of ITotal of NDR2 device must be smaller than the peak current of ITotal of NDR1 device for the other cases. The stable operating point will be located at the relative “high” level. Therefore, the control gate T1 is designed fixed at 3.3V. The Vgg voltages are fixed at 3.3V and 2.5V for NDR1 and NDR2, respectively. The parameters are designed and shown in Table I. The operation results for this logic circuit are shown in Fig. 7, respectively. As seen, we can obtain the inverter, NOR, and NAND gate operation at the same circuit only by modulating the relative parameters. Table I. The parameters condition for the logic circuit. Inverter NOR NAND VS 1.5V 1.5V 1.5V T1 OFF 1.2V 3.3V T2 INPUT INPUT INPUT T3 OFF INPUT INPUT 3.3V 3.3V 3.3V 2.8V 2.5V 2.5V NDR1 Vgg NDR2 Vgg 5. CONCLUSIONS Fig. 7 The measured results for the logic circuit. For the NOR gate operation, T2 and T3 gates both are the input square wave with signal varied from 0 to 2V. The period of T2 is two times of the period of T3 signal. The controlling gate T1 is fixed at 1.2V. According to the truth table, when the input T2 and T3 gates are located at low level, the peak current of ITotal of NDR2 device must be smaller than the peak current of ITotal of NDR1 device. Then the stable operating point will be located at the relative “high” level at the output node. If one (or both) of the input T2 and T3 is (are) located at high voltage level, the peak current of ITotal of NDR2 device must be bigger than the peak current of ITotal of NDR1 devices. The stable operating point will be located at the relative “low” level at this case. Therefore, we design the Vgg voltages with 3.3V and 2.5V for NDR1 and NDR2, respectively. As for the operation of a NAND gate, when the input T2 and T3 gates both are located at high level, the peak current of ITotal of NDR2 device must be bigger than the peak current of ITotal of NDR1 device. The stable operating We have demonstrated the logic circuit design based on the MOS-NDR devices and circuits. This circuit design is operated according to the principle of MOBILE theory. Our MOS-NDR devices and circuits are fabricated by the technique of Si-based CMOS technique. The fabrication cost will be cheaper than that of resonant tunneling diodes (RTD) implemented by the technique of compound semiconductor. Furthermore, our NDR devices are composed of the MOS devices, so these NDR devices are easy to combine with other devices and circuit to achieve the system-on-a-chip (SoC). If the integrated circuit is fabricated with transistor dimensions less than 0.1μm technique, the applications based on the MOS-NDR devices and circuits are still useful. Therefore, the MOS-NDR devices and circuit have high potential in the SoC applications. ACKNOWLEDGMENTS The authors would like to thank the Chip Implementation Center (CIC) of Taiwan for their great effort and assistance in arranging the fabrication of this chip. This work was supported by the National Science Council of Republic of China under the contract no. NSC93-2218E-168-002. REFERENCES [1] S. Sen, F. Capasso, A. Y. Cho, and D. Sivco, “Resonant tunneling device with multiple negative differential resistance: digital and signal processing applications with reduced circuit complexity,”IEEE Trans. Electron Devices, vol. 34, pp. 2185-2191, 1987. [2] T. H. Kuo, H. C. Lin, R. C. Potter, and D. Shupe,“A novel A/D converter using resonant tunneling diodes,” IEEE J. Solid-State Circuits, vol. 26, pp. 145-149, 1991. [3] K. Maezawa, H. Matsuzaki, M. Yamamoto, and T. Otsuji, “High-speed and low-power operation of a resonant tunneling logic gate MOBILE,” IEEE Electron Device Lett., vol. 19, pp. 80-82, 1998. [4] K. J. Chen, K. Maezawa, and M. Yamamoto, “InP-based high-performance monostable-bistable transition logic elements (MOBILE's) using integrated multiple-input resonant-tunneling devices”, IEEE Electron Device Lett., vol. 17, pp. 127-129, 1996. [5] C. Y. Wu and K. N. Lai, “Integrated Λ -type differential negative resistance MOSFET device,” IEEE J. Solid-State Circuits, vol. 14, pp. 1094-1101, 1979. [6] A. F. Gonzalez and P. Mazumder, “Multiple-valued signed-digit adder using negative differentialresistance devices”, IEEE Trans. Comput, vol. 47, pp. 947-959, 1998.