ADS7800 数据资料 dataSheet 下载
... resistors at the input divide standard input ranges (±10V or ±5V for the ADS7800) into levels compatible with the CMOS characteristics of the internal capacitor array. While in the sampling mode, the capacitor array switch for the MSB capacitor (S1) is in position “S”, so that the charge on the MSB ...
... resistors at the input divide standard input ranges (±10V or ±5V for the ADS7800) into levels compatible with the CMOS characteristics of the internal capacitor array. While in the sampling mode, the capacitor array switch for the MSB capacitor (S1) is in position “S”, so that the charge on the MSB ...
MAX5100 +2.7V to +5.5V, Low-Power, Quad, Parallel General Description
... Digital-to-Analog Section The MAX5100 uses a matrix decoding architecture for the DACs. The external reference voltage is divided down by a resistor string placed in a matrix fashion. Row and column decoders select the appropriate tab from the resistor string to provide the needed analog voltages. T ...
... Digital-to-Analog Section The MAX5100 uses a matrix decoding architecture for the DACs. The external reference voltage is divided down by a resistor string placed in a matrix fashion. Row and column decoders select the appropriate tab from the resistor string to provide the needed analog voltages. T ...
LT6553 - 650MHz Gain of 2 Triple Video Amplifier
... The LT6553 has a TTL compatible shutdown mode controlled by the EN pin and referenced to the DGND pin. If the amplifier will be enabled at all times, the EN pin can be connected directly to DGND. If the enable function is desired, either driving the pin above 2V or allowing the internal 46k pull-up ...
... The LT6553 has a TTL compatible shutdown mode controlled by the EN pin and referenced to the DGND pin. If the amplifier will be enabled at all times, the EN pin can be connected directly to DGND. If the enable function is desired, either driving the pin above 2V or allowing the internal 46k pull-up ...
DATA SHEET SAA1305T On/off logic IC Product specification
... impedance register bits 1 and 0; see Table 15). When the 1⁄ V 2 DD value is detected the EXNOR output will be set to logic 1 (active) and after the programmed delay time the status register bit 6 will be set to logic 1 (active). This event will also be indicated via pin CHI and (if enabled) pin RP. ...
... impedance register bits 1 and 0; see Table 15). When the 1⁄ V 2 DD value is detected the EXNOR output will be set to logic 1 (active) and after the programmed delay time the status register bit 6 will be set to logic 1 (active). This event will also be indicated via pin CHI and (if enabled) pin RP. ...
EASY2504 / IEC 61131 + CANopen Master / Slave - frenzel
... based on the Toshiba T6963C or compatible display controller. A list of possible displays is given in the following table. Please note, this is only a very small example list. Graphic LCD modules Type Resolution LMG7422 PLFF 240 x 128 DMF-50316 ...
... based on the Toshiba T6963C or compatible display controller. A list of possible displays is given in the following table. Please note, this is only a very small example list. Graphic LCD modules Type Resolution LMG7422 PLFF 240 x 128 DMF-50316 ...
MAX1482/MAX1483 20µA, ⁄ -Unit-Load, Slew-Rate-Limited
... A low-power shutdown mode is initiated by bringing RE high and DE low. The devices will not shut down unless both the driver and receiver are disabled. In shutdown, the devices typically draw only 0.1µA of supply current. RE and DE may be driven simultaneously; the parts are guaranteed not to enter ...
... A low-power shutdown mode is initiated by bringing RE high and DE low. The devices will not shut down unless both the driver and receiver are disabled. In shutdown, the devices typically draw only 0.1µA of supply current. RE and DE may be driven simultaneously; the parts are guaranteed not to enter ...
Datasheet - Integrated Device Technology
... pin allow other differential signal families such as LVDS, LVPECL, SSTL and CML to be easily interfaced to the input with minimal use of external components. The ICS858S011I is packaged in a small 3mm x 3mm 16-pin VFQFN package which makes it ideal for use in space-constrained applications. ...
... pin allow other differential signal families such as LVDS, LVPECL, SSTL and CML to be easily interfaced to the input with minimal use of external components. The ICS858S011I is packaged in a small 3mm x 3mm 16-pin VFQFN package which makes it ideal for use in space-constrained applications. ...
Low Power Tips for CoolRunner Design Summary
... Historically, low power designs and CPLD devices have been mutually exclusive. Early PLDs, implemented on the bipolar processes, consumed hundreds of milliamperes during quiescent operation. Migration to the CMOS process has decreased power consumption, but most chip designers fabricate product term ...
... Historically, low power designs and CPLD devices have been mutually exclusive. Early PLDs, implemented on the bipolar processes, consumed hundreds of milliamperes during quiescent operation. Migration to the CMOS process has decreased power consumption, but most chip designers fabricate product term ...
ADS1253 数据资料 dataSheet 下载
... computes the digital result based on the most recent outputs from the delta-sigma modulator. At the most basic level, the digital filter can be thought of as simply averaging the modulator results in a weighted form and presenting this average as the digital output. The digital output rate, or data ...
... computes the digital result based on the most recent outputs from the delta-sigma modulator. At the most basic level, the digital filter can be thought of as simply averaging the modulator results in a weighted form and presenting this average as the digital output. The digital output rate, or data ...
MAX11646/MAX11647 Low-Power, 1-/2-Channel, I C, 10-Bit ADCs in Ultra-Tiny 1.9mm x 2.2mm Package
... Low-Power, 1-/2-Channel, I2C, 10-Bit ADCs in Ultra-Tiny 1.9mm x 2.2mm Package The MAX11646/MAX11647 low-power, 10-bit, 1-/2channel analog-to-digital converters (ADCs) feature internal track/hold (T/H), voltage reference, a clock, and an I 2 C-compatible 2-wire serial interface. These devices operate ...
... Low-Power, 1-/2-Channel, I2C, 10-Bit ADCs in Ultra-Tiny 1.9mm x 2.2mm Package The MAX11646/MAX11647 low-power, 10-bit, 1-/2channel analog-to-digital converters (ADCs) feature internal track/hold (T/H), voltage reference, a clock, and an I 2 C-compatible 2-wire serial interface. These devices operate ...
Videotape recorder/reproducer - European Patent Office
... that when shifted from a record mode to a pause mode at the edit point, the tape is rewound by a first predetermined amount (to B), determined by the counting of a predetermined number of control signals recorded in a control track lengthwise of the tape, the tape is then rewound (to D) for a second ...
... that when shifted from a record mode to a pause mode at the edit point, the tape is rewound by a first predetermined amount (to B), determined by the counting of a predetermined number of control signals recorded in a control track lengthwise of the tape, the tape is then rewound (to D) for a second ...
A 400-MHz S/390 Microprocessor
... state of the processor is maintained with ECC protection. The state updates sent to the RU from the FXU and FPU are also broadcast to the BCE and IU so that local copies of architected facilities (e.g., certain ESA/390 control registers) are maintained in lock step with changes to the master copy in ...
... state of the processor is maintained with ECC protection. The state updates sent to the RU from the FXU and FPU are also broadcast to the BCE and IU so that local copies of architected facilities (e.g., certain ESA/390 control registers) are maintained in lock step with changes to the master copy in ...
EF NI H K Test results of the Prototype Outer Tracker Front
... Otis read-out; the LVDS receiver is powered by the +3V that is also used for the ASDBLR. This causes noise hits at thresholds < 750 mV. In the next version this LVDS receiver is not needed anymore. Bx-Clock; there is a capacitive coupling between the power to the ASDBLR boards (-3V) and the digital ...
... Otis read-out; the LVDS receiver is powered by the +3V that is also used for the ASDBLR. This causes noise hits at thresholds < 750 mV. In the next version this LVDS receiver is not needed anymore. Bx-Clock; there is a capacitive coupling between the power to the ASDBLR boards (-3V) and the digital ...
ADL5358 数据手册DataSheet 下载
... networks. C2, C3, C6, and C7 provide bypassing for the center taps of the main and diversity on-chip input baluns. IF Main and Diversity Output Interface. The open collector IF output interfaces are biased through pull-up choke inductors L1, L2, L4, and L5, with R3 and R6 available for additional su ...
... networks. C2, C3, C6, and C7 provide bypassing for the center taps of the main and diversity on-chip input baluns. IF Main and Diversity Output Interface. The open collector IF output interfaces are biased through pull-up choke inductors L1, L2, L4, and L5, with R3 and R6 available for additional su ...
Ku-Band VSAT Block Up Converters
... Monitor and Control The Block Up Converter can communicate with a host computer by means of a 2-wire RS-485 interface or 650 KHz Frequency Shift Keying (FSK) interface. The 2-wire RS-485 interface is available at the circular M&C connector, MS3102E20-29P. The FSK input must be diplexed onto the coax ...
... Monitor and Control The Block Up Converter can communicate with a host computer by means of a 2-wire RS-485 interface or 650 KHz Frequency Shift Keying (FSK) interface. The 2-wire RS-485 interface is available at the circular M&C connector, MS3102E20-29P. The FSK input must be diplexed onto the coax ...
MAX3665 622Mbps, Ultra-Low-Power, 3.3V Transimpedance Preamplifier for SDH/SONET ________________General Description
... 375MHz and 622MHz. Lower bandwidth causes pattern-dependent jitter and a lower signal-to-noise ratio, while higher bandwidth increases thermal noise. The MAX3665 typical bandwidth is 470MHz, making it ideal for 622Mbps applications. The preamplifier’s transimpedance must be high enough to ensure tha ...
... 375MHz and 622MHz. Lower bandwidth causes pattern-dependent jitter and a lower signal-to-noise ratio, while higher bandwidth increases thermal noise. The MAX3665 typical bandwidth is 470MHz, making it ideal for 622Mbps applications. The preamplifier’s transimpedance must be high enough to ensure tha ...
SA-500 - Carson Manufacturing
... - DIP Switch Programmable: Flexible DIP Switch programming allows the installer to sample different settings before selecting desired functions. Options include disabling Phaser and Air Horn to be California Title 13 compatible, replacing Phases with Two-Tone/HiLo, Yelp override, Short Manual, selec ...
... - DIP Switch Programmable: Flexible DIP Switch programming allows the installer to sample different settings before selecting desired functions. Options include disabling Phaser and Air Horn to be California Title 13 compatible, replacing Phases with Two-Tone/HiLo, Yelp override, Short Manual, selec ...
A 3 BITS DISCRETE PURE LINEAR ANALOG PREPROCESSING FOLDING
... Considering architectures, for some applications just about any architecture could work well; for others, there is a “best choice”. In some cases the choice is simple because there is a clear-cut advantage to using one architecture over another [1]. In the field of very high speed, the flash ADC rem ...
... Considering architectures, for some applications just about any architecture could work well; for others, there is a “best choice”. In some cases the choice is simple because there is a clear-cut advantage to using one architecture over another [1]. In the field of very high speed, the flash ADC rem ...
AN008: Using Differential I/O (LVDS, SubLVDS, LVPECL) in iCE65
... The higher potential switching speeds of differential I/O allows data to be multiplexed onto a reduced number of wires at a much higher data rate per line. The reduced number of wires reduces system cost and in some cases simplifies the system design. The internal phase-locked loop (PLL) available i ...
... The higher potential switching speeds of differential I/O allows data to be multiplexed onto a reduced number of wires at a much higher data rate per line. The reduced number of wires reduces system cost and in some cases simplifies the system design. The internal phase-locked loop (PLL) available i ...
74ALVT16823 1. General description 18-bit bus-interface D-type flip-flop with reset and enable;
... packages required to buffer existing registers and provide extra data width for wider data/address paths of buses carrying parity. The 74ALVT16823 has two 9-bit wide buffered registers with clock enable (pin nCE) and master reset (pin nMR) which are ideal for parity bus interfacing in high microprog ...
... packages required to buffer existing registers and provide extra data width for wider data/address paths of buses carrying parity. The 74ALVT16823 has two 9-bit wide buffered registers with clock enable (pin nCE) and master reset (pin nMR) which are ideal for parity bus interfacing in high microprog ...
Flip-flop (electronics)
In electronics, a flip-flop or latch is a circuit that has two stable states and can be used to store state information. A flip-flop is a bistable multivibrator. The circuit can be made to change state by signals applied to one or more control inputs and will have one or two outputs. It is the basic storage element in sequential logic. Flip-flops and latches are a fundamental building block of digital electronics systems used in computers, communications, and many other types of systems.Flip-flops and latches are used as data storage elements. A flip-flop stores a single bit (binary digit) of data; one of its two states represents a ""one"" and the other represents a ""zero"". Such data storage can be used for storage of state, and such a circuit is described as sequential logic. When used in a finite-state machine, the output and next state depend not only on its current input, but also on its current state (and hence, previous inputs). It can also be used for counting of pulses, and for synchronizing variably-timed input signals to some reference timing signal.Flip-flops can be either simple (transparent or opaque) or clocked (synchronous or edge-triggered). Although the term flip-flop has historically referred generically to both simple and clocked circuits, in modern usage it is common to reserve the term flip-flop exclusively for discussing clocked circuits; the simple ones are commonly called latches.Using this terminology, a latch is level-sensitive, whereas a flip-flop is edge-sensitive. That is, when a latch is enabled it becomes transparent, while a flip flop's output only changes on a single type (positive going or negative going) of clock edge.