Chap09
... stimulus at its input. The rise and fall times of a pulse describe how long it takes for the voltage to travel between its 10% and 90% levels. ...
... stimulus at its input. The rise and fall times of a pulse describe how long it takes for the voltage to travel between its 10% and 90% levels. ...
MAX3291,92 - Part Number Search
... becomes 10% or more of the baud period. ISI is caused by the effect of the cable’s RC time constant on different bit patterns. If a series of ones is transmitted, followed by a zero, the transmission-line voltage rises to a high value at the end of the string of ones (signal 1 in Figure 12). As the ...
... becomes 10% or more of the baud period. ISI is caused by the effect of the cable’s RC time constant on different bit patterns. If a series of ones is transmitted, followed by a zero, the transmission-line voltage rises to a high value at the end of the string of ones (signal 1 in Figure 12). As the ...
Evaluates: MAX5088/MAX5089 MAX5089 Evaluation Kit General Description Features
... provide 3.3V at up to 2A of output current. The MAX5089 IC features an internal low RDSON MOSFET to achieve high efficiency and lower overall system cost. The MAX5089 EV kit’s internal switching frequency is preset at 2MHz. The MAX5089 SYNC input can be used to synchronize the converter to an extern ...
... provide 3.3V at up to 2A of output current. The MAX5089 IC features an internal low RDSON MOSFET to achieve high efficiency and lower overall system cost. The MAX5089 EV kit’s internal switching frequency is preset at 2MHz. The MAX5089 SYNC input can be used to synchronize the converter to an extern ...
BDTIC www.BDTIC.com/infineon Industrial & Multimarket
... If no LED is used an external resistor of 2 kΩ should be connected between IxL and GNDBB. The specified switching thresholds may change if the resistor is used. The LED drive short-circuits the status LED if the comparator detects “0”. A constant current sink in parallel with the LED reduces the ope ...
... If no LED is used an external resistor of 2 kΩ should be connected between IxL and GNDBB. The specified switching thresholds may change if the resistor is used. The LED drive short-circuits the status LED if the comparator detects “0”. A constant current sink in parallel with the LED reduces the ope ...
ADS1254 数据资料 dataSheet 下载
... computes the digital result based on the most recent outputs from the delta-sigma modulator. At the most basic level, the digital filter can be thought of as simply averaging the modulator results in a weighted form and presenting this average as the digital output. The digital output rate, or data ...
... computes the digital result based on the most recent outputs from the delta-sigma modulator. At the most basic level, the digital filter can be thought of as simply averaging the modulator results in a weighted form and presenting this average as the digital output. The digital output rate, or data ...
AD9214 数据手册DataSheet下载
... The AD9214 is a 10-bit monolithic sampling analog-to-digital converter (ADC) with an on-chip track-and-hold circuit, and is optimized for low cost, low power, small size, and ease of use. The product operates up to 105 MSPS conversion rate with outstanding dynamic performance over its full operating ...
... The AD9214 is a 10-bit monolithic sampling analog-to-digital converter (ADC) with an on-chip track-and-hold circuit, and is optimized for low cost, low power, small size, and ease of use. The product operates up to 105 MSPS conversion rate with outstanding dynamic performance over its full operating ...
AM26LV32 数据资料 dataSheet 下载
... receiver inputs are never left floating, and fault conditions don’t exist. In actuality, most applications have the capability to either place the drivers in a high-impedance mode or power down the drivers altogether, and cables may be purposely (or inadvertently) disconnected, both of which lead to ...
... receiver inputs are never left floating, and fault conditions don’t exist. In actuality, most applications have the capability to either place the drivers in a high-impedance mode or power down the drivers altogether, and cables may be purposely (or inadvertently) disconnected, both of which lead to ...
12-Bit Input-Buffered 80 MSPS ADC with JESD204A Output Interface
... Figure 1. Mapping of ADC Output to Two 8B10B Codes The two octets can be either transmitted on the same lane (single lane interface) or on two lanes (dual lane interface). By default, the device operates in single lane interface. Conversion clock (CLKP-CLKM) CML output Lane1 (ADC_OUTP<0> ADC_OUTM<0> ...
... Figure 1. Mapping of ADC Output to Two 8B10B Codes The two octets can be either transmitted on the same lane (single lane interface) or on two lanes (dual lane interface). By default, the device operates in single lane interface. Conversion clock (CLKP-CLKM) CML output Lane1 (ADC_OUTP<0> ADC_OUTM<0> ...
Hex Inverters (Rev. B)
... B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators ...
... B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators ...
NB6N239S - Any Differential Clock IN to LVDS OUT
... signal driven or auto oscillation may result. the common output edges are precisely aligned. The common enable (EN) is synchronous so that the The NB6N239S clock inputs can be driven by a variety of internal divider flip−flops will only be enabled/disabled differential signal level technologies incl ...
... signal driven or auto oscillation may result. the common output edges are precisely aligned. The common enable (EN) is synchronous so that the The NB6N239S clock inputs can be driven by a variety of internal divider flip−flops will only be enabled/disabled differential signal level technologies incl ...
NB3N106K 3.3V Differential 1:6 Fanout Clock Driver with HCSL Outputs
... NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functiona ...
... NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functiona ...
CUSTOMER_CODE SMUDE DIVISION_CODE SMUDE
... according to the truth table to the right. A HIGH output (1) results if both the inputs to the gate are LOW (0). If one or both inputs are is HIGH (1), a LOW output (0) results. NOR is the result of the negation of the OR operator. NOR is a functionally complete operation - combinations of NOR gates ...
... according to the truth table to the right. A HIGH output (1) results if both the inputs to the gate are LOW (0). If one or both inputs are is HIGH (1), a LOW output (0) results. NOR is the result of the negation of the OR operator. NOR is a functionally complete operation - combinations of NOR gates ...
High-Speed and High-Precision Current Winner-Take
... The fact that the WTA operation is fully parallel and can be distributed makes these circuits very useful in visual attention and tracking systems, where the localization of the most salient regions in an image and selection of salient targets in the field of view (FOV) are very important tasks. In ...
... The fact that the WTA operation is fully parallel and can be distributed makes these circuits very useful in visual attention and tracking systems, where the localization of the most salient regions in an image and selection of salient targets in the field of view (FOV) are very important tasks. In ...
ADS7824 数据资料 dataSheet 下载
... NOTES: (1) An asterik (✻) specifies same value as grade to the left. (2) LSB means Least Significant Bit. For the 12-bit, ±10V input ADS7824, one LSB is 4.88mV. (3) Typical rms noise at worst case transitions and temperatures. (4) Full scale error is the worst case of –Full Scale or +Full Scale untr ...
... NOTES: (1) An asterik (✻) specifies same value as grade to the left. (2) LSB means Least Significant Bit. For the 12-bit, ±10V input ADS7824, one LSB is 4.88mV. (3) Typical rms noise at worst case transitions and temperatures. (4) Full scale error is the worst case of –Full Scale or +Full Scale untr ...
AD7783 数据手册DataSheet下载
... Table I shows the output rms noise and output peak-to-peak resolution in bits (rounded to the nearest 0.5 LSB) for the two input voltage ranges. The numbers are typical and are generated at a differential input voltage of 0 V. The peak-to-peak resolution figures represent the resolution for which th ...
... Table I shows the output rms noise and output peak-to-peak resolution in bits (rounded to the nearest 0.5 LSB) for the two input voltage ranges. The numbers are typical and are generated at a differential input voltage of 0 V. The peak-to-peak resolution figures represent the resolution for which th ...
www.BDTIC.com/TI Implications of Slow or Floating CMOS Inputs SCBA004C
... Both CMOS and BiCMOS families have a CMOS input structure. This structure is an inverter consisting of a p-channel to VCC and an n-channel to GND as shown in Figure 1. With low-level input, the p-channel transistor is on and the n-channel is off, causing current to flow from VCC and pulling the node ...
... Both CMOS and BiCMOS families have a CMOS input structure. This structure is an inverter consisting of a p-channel to VCC and an n-channel to GND as shown in Figure 1. With low-level input, the p-channel transistor is on and the n-channel is off, causing current to flow from VCC and pulling the node ...
AD9851 数据手册DataSheet 下载
... +VS collectively refers to the positive voltages applied to DVDD, PVCC, and AVDD. Voltages applied to these pins should be of the same potential. ...
... +VS collectively refers to the positive voltages applied to DVDD, PVCC, and AVDD. Voltages applied to these pins should be of the same potential. ...
Flip-flop (electronics)
In electronics, a flip-flop or latch is a circuit that has two stable states and can be used to store state information. A flip-flop is a bistable multivibrator. The circuit can be made to change state by signals applied to one or more control inputs and will have one or two outputs. It is the basic storage element in sequential logic. Flip-flops and latches are a fundamental building block of digital electronics systems used in computers, communications, and many other types of systems.Flip-flops and latches are used as data storage elements. A flip-flop stores a single bit (binary digit) of data; one of its two states represents a ""one"" and the other represents a ""zero"". Such data storage can be used for storage of state, and such a circuit is described as sequential logic. When used in a finite-state machine, the output and next state depend not only on its current input, but also on its current state (and hence, previous inputs). It can also be used for counting of pulses, and for synchronizing variably-timed input signals to some reference timing signal.Flip-flops can be either simple (transparent or opaque) or clocked (synchronous or edge-triggered). Although the term flip-flop has historically referred generically to both simple and clocked circuits, in modern usage it is common to reserve the term flip-flop exclusively for discussing clocked circuits; the simple ones are commonly called latches.Using this terminology, a latch is level-sensitive, whereas a flip-flop is edge-sensitive. That is, when a latch is enabled it becomes transparent, while a flip flop's output only changes on a single type (positive going or negative going) of clock edge.