Download unit2

UNIT II
COMBINATIONAL LOGIC CIRCUITS
Combinational vs. Sequential Logic
In
Combinational
Logic
Circuit
In
Out
Combinational
Logic
Circuit
State
Combinational
Output = f(In)
Sequential
Output = f(In, Previous In)
Out
Static Complementary CMOS

Pull-up network (PUN) and pull-down network (PDN)
VDD
PMOS transistors only
In1
In2
PUN
InN
In1
In2
InN
pull-up: make a connection from VDD to F
when F(In1,In2,…InN) = 1
F(In1,In2,…InN)
PDN
pull-down: make a connection from F to
GND when F(In1,In2,…InN) = 0
NMOS transistors only
PUN and PDN are dual logic networks
NMOS Transistors
in Series/Parallel Connection
Transistors can be thought as a switch controlled by its gate signal
NMOS switch closes when switch control input is high
A
B
X
Y
Y = X if A and B
A
X
B
Y
Y = X if A OR B
NMOS Transistors pass a “strong” 0 but a “weak” 1
PMOS Transistors
in Series/Parallel Connection
PMOS switch closes when switch control input is low
A
B
X
Y
Y = X if A AND B = A + B
A
X
B
Y
Y = X if A OR B = AB
PMOS Transistors pass a “strong” 1 but a “weak” 0
Threshold Drops
VDD
PUN
VDD
S
D
VDD
D
0  VDD
VGS
S
CL
VDD  0
PDN
D
VDD
S
CL
0  VDD - VTn
CL
VGS
VDD  |VTp|
S
D
CL
Complementary CMOS Logic Style
Example Gate: NAND
Example Gate: NOR
Complex CMOS Gate
B
A
C
D
OUT = D + A • (B + C)
A
D
B
C
Constructing a Complex Gate
VDD
VDD
C
F
SN4
F
SN1
A
SN3
D
B
C
B
SN2
A
D
A
B
D
C
F
(a) pull-down network
(b) Deriving the pull-up network
hierarchically by identifying
sub-nets
A
D
B
C
(c) complete gate
Elmore Delay
• ON transistors look like resistors
• Pullup or pulldown network modeled as RC
ladder
• Elmore delay of RC ladder
R1
t pd 
R2
R3
C1
C2

nodes i
RN
C3
CN
Ri to sourceCi
 R1C1   R1  R2  C2  ...   R1  R2  ...  RN  CN
Example: 2-input NAND
• Estimate rising and falling propagation delays
of a 2-input NAND driving h identical gates.
2
2
A
2
B
2x
6C
Y
4hC
2C
h copies
R
Y
(6+4h)C
t pdr 
Example: 2-input NAND
• Estimate rising and falling propagation delays
of a 2-input NAND driving h identical gates.
2
2
A
2
B
2x
R
Y
(6+4h)C
6C
Y
4hC
2C
t pdr  6  4h  RC
h copies
Estimate the worst case falling propagation delays of
a 2-input NAND driving h identical gates
The worst case occurs when the node x is already
charged up to nearly Vdd through the top nMOS
2
2
A
2
B
2x
6C
2C
Y
4hC
Suppose A = 1, B = 0, then
Y = 1, node X is nearly VDD
Now change inputs to A=B=1
both node Y and node X need
to discharge
Example: 2-input NAND
• Estimate rising and falling propagation delays
of a 2-input NAND driving h identical gates.
2
2
A
2
B
2x
x
R/2
R/2
2C
Y
(6+4h)C
Y
4hC
6C
2C
t pdf 
h copies
Example: 2-input NAND
• Estimate rising and falling propagation delays
of a 2-input NAND driving h identical gates.
2
2
A
2
B
2x
x
R/2
R/2
2C
Y
(6+4h)C
6C
Y
4hC
2C
h copies
t pdf   2C   R2    6  4h  C   R2  R2 
  7  4h  RC
Delay Components
• Delay has two parts
– Parasitic delay, gate driving its own internal
diffusion capacitance
• 6 or 7 RC
• Independent of load
– Effort delay, depends on the ration of external load
capacitance to input capacitance,
– Effort delay changes with transistor width
• Proportional to load capacitance
• Logical effort and Electrical effort
Contamination Delay
• Best-case (contamination) delay can be
substantially less than propagation delay.
• Ex: If both inputs fall simultaneously, the
output should be pulled up in half the time
2
2
A
2
B
2x
6C
2C
Y
4hC
tcdr = (R/2)(6+4h)C
tcdr   3  2h  RC
R R
Y
(6+4h)C
CIRCUIT FAMILIES
•
•
•
•
•
Static CMOS
Ratioed Circuits
Cascode Voltage Switch Logic (CVSL)
Dynamic Circuits
Pass-transistor Circuits
Static CMOS Circuits
Static CMOS
Circuits
 In Static CMOS circuits with n inputs, 2n transistors are
needed.
 nMOS block is a dual of the pMOS block.
 What ever is in series in nMOS, appears in parallel in
pMOS and vice versa.
 CMOS gates consume power only during the transition of
inputs.
Static complementary gate
structure
Pull-up and pull-down networks
VDD
pull-up
network
out
inputs
Pull-down
network
VSS
Pull-up/pull-down network
design
 Pull-up and pull-down networks are duals.
 To design one gate, first design one network, then compute
dual to get other network.
Inverter
CMOS Logic Style Construction
Example Gate: NAND
BUBBLE PUSHING
Compound Gates - AOI/OAI
gates
 AOI = and/or/invert; OAI = or/and/invert.
 Implement larger functions.
 Pull-up and pull-down networks are compact: smaller
area, higher speed than NAND/NOR network equivalents.
AOI
example
invert
or
and
AOI CMOS Gate
• AOI complex CMOS gate can be used to directly implement
a sum-of-products Boolean function
• The pull-down N-tree can be implemented as follows:
– Product terms yield series-connected NMOS transistors
– Sums are denoted by parallel-connected legs
– The complete function must be an inverted
representation
• The pull-up P-tree is derived as the dual of the N-tree
OAI CMOS Gate
• An Or-And-Invert (OAI) CMOS gate is similar to the AOI gate except that it is an
implementation of product-of-sums realization of a function
• The N-tree is implemented as follows:
– Each product term is a set of parallel transistors for each input in the term
– All product terms (parallel groups) are put in series
– The complete function is again assumed to be an inverted representation
• The P-tree can be implemented as the dual of the N-tree
• Note: AO and OA gates (non-inverted function representation) can be
implemented directly on the P-tree if inverted inputs are available
Properties of CMOS Gates
High noise margins:
VOH and VOL are at VDD and GND, respectively.
No static power consumption:
There never exists a direct path between VDD and
VSS (GND) in steady-state mode.
Comparable rise and fall times:
(under the appropriate scaling conditions)
Ratioed Circuits
 Pseudo-nMOS Circuits
 Ganged CMOS
 Source-Follower Pull-up Logic (SFPL)
Pseudo-nMOS Circuits
• Adding a single pFET to otherwise nFET-only
circuit produces a logic family that is called
pseudo-nMOS
– Less transistor than CMOS
– For N inputs, only requires (N+1) FETs
– Pull-up device: pFET is biased active since
the grounded gate gives VSGp = VDD
Figure 1 General structure of
– Pull-down device: nFET logic array acts as a a pseudo-nMOS logic gate
large switch between the output f and
ground
– However, since the pFET is always biased
on, VOL can never achieve the ideal value
of 0 V
• A simple inverter using pseudo-nMOS as
Figure 2
Figure 2 Pseudo-nMOS inverter
Ganged CMOS (Symmetric Circuits)
A
B
C
Z


Inverters ganged together to perform a function.
NOR gate ; Z = A+B+C
Source-Follower Pull-up Logic (SFPL)
•
SFPL is a variation on pseudo-NMOS
whereby the load device is an N pulldown transistor and N source-follower
pull-ups are used on the inputs.
– N pull-up transistors can be small
limiting input capacitance
– N transistors are also duplicated as pulldown devices in order to improve the
fall time
– Rise time is determined by the P1
inverter pull-up transistor when all
inputs are low
•
SFPL is useful for high fan-in NOR logic
gates
R. W. Knepper
SC571, page 5-25
Cascode Voltage Switch Logic (CVSL)
• Differential type of logic circuit where both true and
complement inputs are required.
• N pull down tree are the dual of each other.
• P pull-up devices are cross-coupled to latch output..
• Both true and complement outputs are obtained.
Basic Structure of CVSL
Q
a
b
Q
Q
Q
a
...
...
b
a
c
b
c
Dynamic CMOS Logic
 Logic function is implemented by the PDN only
No. of transistors is N+2
Smaller in area than static CMOS
 Full swing outputs (VOL = gnd and VOH = VDD)
 Non-ratioed
 Faster switching speed
 Power dissipation should be better
 Needs precharge clock.
Dual-Rail Domino
• Domino only performs noninverting functions:
– AND, OR but not NAND, NOR, or XOR
• Dual-rail domino solves this problem
– Takes true and complementary inputs
– Produces true and complementary outputs
sig_h
sig_l
Meaning
0
0
Precharged
0
1
‘0’
1
0
‘1’
1
1
invalid

Y_l
inputs
f

Y_h
f
Example: AND/NAND
• Given A_h, A_l, B_h, B_l
• Compute Y_h = A * B, Y_l = ~(A * B)
Example: AND/NAND
• Given A_h, A_l, B_h, B_l
• Compute Y_h = A * B, Y_l = ~(A * B)
• Pulldown networks are conduction complements

Y_l
A_h
= A*B
A_l
B_l
B_h

Y_h
= A*B
Example: XOR/XNOR
• Sometimes possible to share transistors

Y_l
= A xnor B
A_h
Y_h
A_l
A_l
B_l
B_h

A_h
= A xor B
TRANSMISSION GATES
• NMOS pass transistor passes a strong 0 and a weak 1.
• PMOS pass transistor passes a strong 1 and a weak 0.
• Combine the two to make a CMOS pass gate which will
pass a strong 0 and a strong 1.
TRANSMISSION GATE
PROBLEMS WITH TRANSMISSION GATES
 No isolation between the input and output.
 Output progressively deteriorates as it passes through various
stages.
However designs get simplified.
Multiplexer
XOR gate
Transmission Gates
•
N-Channel MOS Transistors pass a 0 better than a 1
•
P-Channel MOS Transistors pass a 1 better than a 0
•
This is the reason that N-Channel transistors are used in the pull-down
network and P-Channel in the pull-up network of a CMOS gate.
Otherwise the noise margin would be significantly reduced.
Transmission Gates
• Pass transistors produce degraded outputs
• Transmission gates pass both 0 and 1 well
Input
g
a
b
gb
a
b
gb
g = 0, gb = 1
a
b
g = 1, gb = 0
0
strong 0
g = 1, gb = 0
a
b
g = 1, gb = 0
strong 1
1
g
g
a
g
b
gb
Output
a
b
gb
symbols
Transmission Gates
•
Implementing XOR gates
– With NAND gates and inverters:
– With transmission gates:
•
Why would one of these circuits be preferable to the other?
Transmission Gates
•
Implementing a multiplexer with transmission gates:
– When S = 0, input X1 is connected to the output Y
– When S = 1, input X2 is connected to the output Y
Pass Transistors
• Transistors can be used as switches
g=0
g
s
d
s
d
Input g = 1 Output
0
strong 0
g=1
s
d
g=0
g
s
s
g=1
Input
d
d
g=1
s
1
d
degraded 1
g=0
0
Output
degraded 0
g=0
strong 1
Pass Transistor
• Pass-transistor circuits are formed by dropping the PMOS
transistors and using only NMOS pass transistors
• In this case, CMOS inverters (or other means) must be used
periodically to recover the full VDD level since the NMOS
pass transistors will provide a VOH of VDD – VTn in some
cases
• The pass transistor circuit requires complementary inputs
and generates complementary outputs to pass on to the next
stage
Pass Transistor
• This figure shows a simple
XNOR implementation
using pass transistors:
• If A is high, B is passed
through the gate to the
output
• If A is low, -B is passed
through the gate to the
output
Pass Transistor
• At right,
– (a) is a 2-input NAND
pass transistor circuit
– (b) is a 2-input NOR pass
transistor circuit
• Each circuit requires 8
transistors, double that
required using conventional
CMOS realizations
Pass Transistor
• Pass-transistor logic gate can implement Boolean functions
NOR, XOR, NAND, AND, and OR depending upon the P1-P4
inputs, as shown below.
–
–
–
–
–
P1,P2,P3,P4 = 0,0,0,1 gives F(A,B) = NOR
P1,P2,P3,P4 = 0,1,1,0 gives F(A,B) = XOR
P1,P2,P3,P4 = 0,1,1,1 gives F(A,B) = NAND
P1,P2,P3,P4 = 1,0,0,0 gives F(A,B) = AND
P1,P2,P3,P4 = 1,1,1,0 gives F(A,B) = OR
Circuit can be
operated with
clocked P pull-up
device or inverterbased latch
Pass Transistor Logic
Families
 Complementary Pass Transistor Logic
 Double Pass Transistor Logic
Complementary Pass-Transistor Logic (CPL)
Pass Variables
Inputs
Control
Variables
f
f
F
F
Basic logic functions in CPL
A
B
B
A
A B
A
B
B
B
B
A
A
B
B
A
A C B C
B
C
B
C
A
A
B
B
A
A
A B
A B
CPL Logic
A
A
A
A
B
n1
n2
B
B
n3
n4
B
C
Q
C
Qb
S
S
XOR gate
(a)
(b)
S
S
Sum circuit
CPL provides an efficient implementation of XOR function
Full Adder Design III
• Complementary Pass Transistor Logic (CPL)
– Slightly faster, but more area
B
B
B
C
B
C
B
C
B
C
A
S
B
C
B
C
B
C
B
C
Cout
A
A
S
A
B
B
Cout
Double Pass-Transistor Logic (DPL):
VDD
B
B
A
AND/NAND
A
A B
B
B
A
A
O
A
O
B
A
B
A
B
A
XOR/XNOR
B
B
A
A
B
B
A
A
B
O
O
A B
Double Pass-Transistor Logic (DPL):
A
A
A
A
B
n1
n1
p2
B
p2
B
p1
n2
p1
n2
C
B
Q
C
Qb
O
O
S
(a) XOR
S
(b)
One bit full-adder:
Sum circuit
Double Pass-Transistor Logic (DPL):
AND/NAND
DPL Full Adder
Vcc
A
A
C
C
Vcc
B
B
S
Vcc
A
S
A
Multiplexer
B
B
Buffer
The critical path traverses two transistors only
(not counting the buffer)
OR/NOR
Dynamic CMOS
• In static circuits at every point in time (except when
switching) the output is connected to either GND or
VDD via a low resistance path.
– fan-in of n requires 2n (n N-type + n P-type)
devices
• Dynamic circuits rely on the temporary storage of
signal values on the capacitance of high impedance
nodes.
– requires on n + 2 (n+1 N-type + 1 P-type)
transistors
Dynamic Gate
Clk
Clk
Mp
off
Mp on
Out
In1
In2
In3
CL
PDN
A
C
B
Clk
Me
Clk
Two phase operation
Precharge (Clk = 0)
Evaluate (Clk = 1)
1
Out
((AB)+C)
off
Me on
Conditions on Output
• Once the output of a dynamic gate is discharged, it
cannot be charged again until the next precharge
operation.
• Inputs to the gate can make at most one transition
during evaluation.
• Output can be in the high impedance state during
and after evaluation (PDN off), state is stored on CL
Properties of Dynamic Gates
• Logic function is implemented by the PDN only
– number of transistors is N + 2 (versus 2N for static complementary CMOS)
• Full swing outputs (VOL = GND and VOH = VDD)
• Non-ratioed - sizing of the devices does not affect the
logic levels
• Faster switching speeds
– reduced load capacitance due to lower input capacitance
(Cin)
– reduced load capacitance due to smaller output loading (Cout)
– no Isc, so all the current provided by PDN goes into
discharging CL
Properties of Dynamic Gates
• Overall power dissipation usually higher than static
CMOS
– no static current path ever exists between VDD and
GND (including Psc)
– no glitching
– higher transition probabilities
– extra load on Clk
• PDN starts to work as soon as the input signals exceed
VTn, so VM, VIH and VIL equal to VTn
– low noise margin (NML)
• Needs a precharge/evaluate clock
Dynamic Logic
• Dynamic gates uses a clocked pMOS pullup
• Two modes: precharge and evaluate
2
A

2/3
Y
1
Y
1
A
Static
4/3
Pseudo-nMOS

Y
Precharge
Y
A
1
Dynamic
Evaluate
Precharge
The Foot
• What if pulldown network is ON during
precharge?
• Use series evaluation transistor to prevent
fight.
precharge transistor

Y


Y
inputs
A
Y
inputs
f
f
foot
footed
unfooted
Logical Effort
Inverter

unfooted
NAND2
1
gd
pd
footed
2
2
2
B
2
gd
pd
= 2/3
= 3/3

1
1
B
Y
gd
pd
= 2/3
= 3/3
A
1
gd
pd
= 1/3
= 3/3
1
Y
1
Y
A
A
= 1/3
= 2/3


1
Y
1
Y
A

NOR2
A
3
B
3
3

1
Y
gd
pd
= 3/3
= 4/3
A
2
B
2
2
gd
pd
= 2/3
= 5/3
Issues in Dynamic Design 1: Charge Leakage
CLK
Clk
Mp
Out
CL
A
Clk
Me
Evaluate
VOut
Precharge
Leakage sources
Dominant component is subthreshold current
Solution to Charge Leakage
Keeper
Clk
Mp
A
Mkp
CL
Out
B
Clk
Me
Same approach as level restorer for pass-transistor logic
Issues in Dynamic Design 2: Charge Sharing
Clk
Mp
Out
A
CL
B=0
Clk
CA
Me
CB
Charge stored originally on CL
is redistributed (shared) over
CL and CA leading to reduced
robustness
Charge Sharing Example
Clk
Ca=15fF
B
Cc=15fF
A
A
B
B
C
C
Clk
Out
CL=50fF
!B
Cb=15fF
Cd=10fF
Charge Sharing
V DD
case 1) if V out < VTn
VDD
Clk

Mp
Mp
Out
Out
CL
A
A
=
BB
00
Clk 
CL
Ma
Ma
M
Mb
b
Mee
M
XX
CCa a
CCb b
C V
= C V
t + C V
– V V 
L DD
L out  
a DD
Tn X
or
Ca
V out = Vout  t  – V DD = – --------  V DD – V Tn  V X  
CL
case 2) if V out > VTn
 Ca 
Vout = –V DD  ---------------------- 
 Ca + CL 
Solution to Charge Redistribution
Clk
Mp
Mkp
Clk
Out
A
B
Clk
Me
Precharge internal nodes using a clock-driven transistor (at the cost of
increased area and power)
Issues in Dynamic Design 3: Backgate Coupling
Clk
Mp
A=0
Out1 =1
CL1
Out2 =0
CL2
B=0
Clk
Me
Dynamic NAND
Static NAND
In
Backgate Coupling Effect
3
2
Out1
1
Clk
0
In
Out2
-1
0
2
Time, ns
4
6
Issues in Dynamic Design 4: Clock Feedthrough
Clk
Mp
A
CL
B
Clk
Out
Me
Coupling between Out and Clk
input of the precharge device
due to the gate to drain
capacitance.
So voltage of Out can rise
above VDD. The fast rising (and
falling edges) of the clock
couple to Out.
Clock Feedthrough
Clock feedthrough
Clk
Out
2.5
In1
In2
1.5
In3
In &
Clk
0.5
In4
Clk
Out
-0.5
0
0.5
Time, ns
1
Clock feedthrough
Other Effects
•
•
•
•
Capacitive coupling
Substrate coupling
Minority charge injection
Supply noise (ground bounce)
Cascading Dynamic Gates
V
Clk
Mp
Clk
Mp
Out1
Me
Clk
Out2
In
In
Clk
Clk
Me
Out1
VTn
V
Out2
t
Only 0  1 transitions allowed at inputs!
Monotonicity
• Dynamic gates require monotonically rising
inputs during evaluation 
– 0 -> 0
– 0 -> 1
– 1 -> 1
– But not 1 -> 0
A
violates monotonicity
during evaluation
A

Precharge
Evaluate
Precharge
Y
Output should rise but does not
Monotonicity Woes
• But dynamic gates produce
monotonically falling
outputs during evaluation
• Illegal for one dynamic gate
to drive another!
A
A == 11


A
A
Y
X
X
Y


Precharge
Precharge
Evaluate
Evaluate
Precharge
Precharge
X
X
X monotonically falls during evaluation
Y
Y
Y should rise but cannot
Domino Logic
Clk
In1
In2
In3
Clk
Mp
11
10
PDN
Me
Out1
Clk
Mp Mkp
00
01
In4
In5
Clk
PDN
Me
Out2
Domino Gates
• Follow dynamic stage with inverting static gate
– Dynamic / static pair is called domino gate
– Produces monotonic outputs
domino AND
W

X
Y
Z
Precharge
Evaluate
Precharge
W
A
B
C

X
Y
dynamic static
NAND inverter
Z

A
B


W
X
H
C
Y
H
Z
=
A
B

X
C
Z
Domino Optimizations
• Each domino gate triggers next one, like a string of dominos
toppling over
• Gates evaluate sequentially but precharge in parallel
• Thus evaluation is more critical than precharge
• HI-skewed static stages can perform logic

S0
S1
S2
S3
D0
D1
D2
D3
H

S4
S5
S6
S7
D4
D5
D6
D7
Y
Dual-Rail Domino
• Domino only performs noninverting functions:
– AND, OR but not NAND, NOR, or XOR
• Dual-rail domino solves this problem
– Takes true and complementary inputs
– Produces
complementary outputs
sig_h
sig_ltrue and
Meaning
0
0
Precharged
0
1
‘0’
1
0
‘1’
1
1
invalid

Y_l
inputs
f

Y_h
f
Example: AND/NAND
• Given A_h, A_l, B_h, B_l
• Compute Y_h = AB, Y_l = AB
• Pulldown networks are conduction
complements

Y_l
A_h
= A*B
A_l
B_l
B_h

Y_h
= A*B
Example: XOR/XNOR
• Sometimes possible to share transistors

Y_l
= A xnor B
A_h
Y_h
A_l
A_l
B_l
B_h

A_h
= A xor B
np-CMOS
NORA Logic
NP Domino
Zipper CMOS
• The NP-Domino or NORA logic is very
susceptible to noise and leakage.
• Zipper Domino has the same structure, but
the precharge transistors are left slightly ON
during evaluation.
Leakage
• Dynamic node floats high during evaluation
– Transistors are leaky (IOFF  0)
– Dynamic value will leak away over time
– Formerly miliseconds, now nanoseconds
• Use keeper to hold dynamic node
weak keeper
– Must be weakenough
1 k not to fight evaluation
X
A
2
2
H
Y
Charge Sharing
• Dynamic gates suffer from charge sharing


A
Y
CY
x
A
Y
B=0
Cx
Charge sharing noise
x
CY
Vx  VY 
VDD
C x  CY
Secondary Precharge
• Solution: add secondary precharge transistors
– Typically need to precharge every other node
• Big load capacitance CY helps as well

Y
A
B
x
secondary
precharge
transistor
Noise Sensitivity
• Dynamic gates are very sensitive to noise
– Inputs: VIH  Vtn
– Outputs: floating output susceptible noise
• Noise sources
– Capacitive crosstalk
– Charge sharing
– Power supply noise
– Feedthrough noise
– And more!
Power
• Domino gates have high activity factors
– Output evaluates and precharges
• If output probability = 0.5, a = 0.5
– Output rises and falls on half the cycles
– Clocked transistors have a = 1
– For a 4 input NAND, aCMOS = 3/16, aDynamic = 1/4
• Leads to very high power consumption
• However, glitching does not occur in dynamic
logic.
• The load capacitances are lower.
MODL
• It is often necessary to compute multiple
functions where one is a subfunction of the
other or shares a subfunction.
• One very typical example is the carry in
addition:
c1  g1  p1c 0
c 2  g2  p2 g1  p1c 0 


c 3  g3  p3 g2  p2 g1  p1c 0 



c 4  g4  p4 g3  p3 g2  p2 g1  p1c 0 
MODL Carry Chains
MODL
• Beware of sneak paths.
• Certain inputs must be mutually exclusive.
Domino Summary
• Domino logic is attractive for high-speed circuits
– 1.3 – 2x faster than static CMOS
– But many challenges:
• Monotonicity, leakage, charge sharing, noise
• Widely used in high-performance
microprocessors in 1990s when speed was king
• Largely displaced by static CMOS now that power
is the limiter
• Still used in memories for area efficiency
POWER DISSIPATION
Power is drawn from a voltage source attached to
the VDD pin(s) of a chip.
Instantaneous Power:
Energy:
Average Power:
P(t )  iDD (t )VDD
T
T
0
0
E   P(t )dt   iDD (t )VDDdt
Pavg
E 1 T
   iDD (t )VDD dt
T T 0
Overview of Power Dissipation
 Ptotal = Pdynamic+Pstatic
 Power Consumption (Pdynamic)
Dynamic power Consumption Pdynamic = Pswitching + Pshortcircuit
Switching load capacitances
Short-circuit current
– Charging and discharging capacitors
 Short Circuit Power Consumption (Pshort-circuit)
– Short circuit path between supply rails during switching
Power Dissipation Sources
Static power: Pstatic = (Isub + Igate + Ijunct + Icontention)VDD
Subthreshold leakage
Gate leakage
Junction leakage
Contention current
Dynamic Power
 Dynamic power is required to charge and discharge load
capacitances when transistors switch.
 One cycle involves a rising and falling output.
 On rising output, charge Q = CVDD is required
 On falling output, charge is dumped to GND
Vdd
 This repeats Tfsw times
over an interval of T
Vin
Vout
CL
fsw
Dynamic Power
T
Pdynamic
1
  iDD (t )VDD dt
T 0
T
VDD

iDD (t )dt

T 0
VDD
iDD(t)
VDD

TfswCVDD 
T
 CVDD 2 f sw
fsw
C
Dynamic Power
 Suppose the system clock frequency = f
 Let fsw = af, where a = activity factor
 If the signal is a clock, a = 1
 If the signal switches once per cycle, a = ½
 Dynamic gates:
 Switch either 0 or 2 times per cycle, a = ½
 Static gates:
 Depends on design, but typically a = 0.1
 Dynamic power:
Pdynamic  aCVDD 2 f
Dynamic Power
 Pdynamic = Energy/per-transition  Transition rate
= CLVDD2 f0→1
= CL VDD2 P0→1 f
= Ceff VDD2 f
 Ceff = effective capacitance = CL P0→1
 Power dissipation is data dependent
– Function of Switching Activity
 Activity Factor (P0→1)
– Clock signal: P0→1(clk) = 1
– Data signal: P0→1(data) < 0.5
Short Circuit Current
 When transistors switch, both nMOS and pMOS networks
may be momentarily ON at once
Vdd
 Leads to a blip of “short circuit” current.
 ~ 15% of dynamic power
Vin
Vout
– ~85% to charge capacitance CL
CL
 NMOS and PMOS on
– Both transistors in saturation
 Long rise / fall times
– Slow input transition
– Increase short circuit current
Make input signal transitions fast to save power!
VDD
Short Circuit Current
ISC≈0
Vout
CL
Vin
Large capacitive load
VDD
ISC≈IMAX
Vin
Vout
CL
Small capacitive load
Because of finite slope of input signal, there is a
period when both PMOS and NMOS device are “on”
and create a path from supply to ground
E / E
8
7
6
5
4
3
2
1
0
W/L|P = 7.2 mm/1.2mm
W/L|N = 2.4 mm/1.2mm
VDD = 5 V
VDD = 3.3 V
0
1
2
3
4
5
r
The power dissipation due to short circuit
currents is minimized by matching the rise/fall
times of the input and output signals.
Dynamic Power Reduction

Pswitching  a CVDD f
2
 Try to minimize:
– Activity factor
– Capacitance
– Supply voltage
– Frequency
Voltage Scaling
Dual voltage supply

Internal voltage
– Reduced internal voltage 1.2V
• For low power operation
 External voltage
– Compatible IO voltage 3.3V
• To interface other ICs
Capacitance Minimization
– Gate capacitance
– Fewer stages of logic
– Small gate sizes
 Wire capacitance
– Good floorplanning to keep communicating blocks close
to each other
– Drive long wires with inverters or buffers rather than
complex gates
Clock Gating
 The best way to reduce the activity is to turn off the clock
to registers in unused blocks
– Saves clock activity (a = 1)
– Eliminates all switching activity in the block
– Requires determining if block will be used
Voltage / Frequency
 Run each block at the lowest possible voltage and frequency
that meets performance requirements
 Voltage Domains
– Provide separate supplies to different blocks
– Level converters required when crossing
from low to high VDD domains
 Dynamic Voltage Scaling
– Adjust VDD and f according to
workload
Static power Dissipation
Power dissipation occurring when device is in standby mode
As technology scales this becomes significant
Leakage power dissipation
Components:
Reverse biased p-n junction
Sub threshold leakage
DIBL leakage
Channel punch through
GIDL Leakage
Narrow width effect
Oxide leakage
Hot carrier tunneling effect
Source of Leakage Current
Leakage
 Sub-threshold current
– Transistor conducts below Vt
– For sub-micron relevant
• VDD / Vt ratio smaller
• Can dominate power consumption!
• Especially in idle mode.
Charge nodes fully to VDD!
Discharge nodes completely to GND!
 Drain leakage current
– Reverse biased junction diodes
Vdd
Vout
Drain
junction
leakage
Subthreshold
current
Static Power
 Static power is consumed even when chip is quiescent.
– Ratioed circuits burn power in fight between ON
transistors
– Leakage draws power from nominally OFF devices
Vgs Vt
I ds  I ds 0e
nvT
Vt  Vt 0  Vds  


1  e


s  Vsb 
Vds
vT




s

Subthreshold current

Sub-threshold current increases exponentially
Subthreshold current can be reduced by increasing Vt
Selective application of multiple threshold
(low-Vt transistors on critical paths, high Vt transistors on
other paths)
Control Vt through the body voltage
Sub-threshold current decreases in long channel
transistors and increases in short channel
Sub-threshold Leakage
Component
Gate Leakage
 Extremely strong function of tox and Vgs
– Negligible for older processes
– Approaches subthreshold leakage at 65 nm and below
in some processes
 An order of magnitude less for pMOS than nMOS
 Control leakage in the process using tox > 10.5 Å
– High-k gate dielectrics help
– Some processes provide multiple tox
• e.g. thicker oxide for 3.3 V I/O transistors
 Control leakage in circuits by limiting VDD
Junction Leakage
 From reverse-biased p-n junctions
– Between diffusion and substrate or well
 Ordinary diode leakage is negligible
 Band-to-band tunneling (BTBT) can be significant
– Especially in high-Vt transistors where other leakage is
small
– Worst at Vdb = VDD
 Gate-induced drain leakage (GIDL) exacerbates
– Worst for Vgd = -VDD (or more negative)
RATIOED CIRCUIT
 Pseudo-NMOS logic style PMOS as resistor
– PDN as static CMOS logic
 Static current
– When output low
 Power consumption
– Even without switching activity
Static power Reduction
Reduce static power
•Selectively use ratioed circuits
•Selectively use low Vt devices
•Leakage reduction:
stacked devices, body bias, low temperature