MAX12554 14-Bit, 80Msps, 3.3V ADC General Description Features
... from baseband to input frequencies of 175MHz and beyond, making the MAX12554 ideal for intermediatefrequency (IF) sampling applications. Powered from a single 3.3V supply, the MAX12554 consumes only 429mW while delivering a typical 70.9dB signal-to-noise ratio (SNR) performance at a 175MHz input fre ...
... from baseband to input frequencies of 175MHz and beyond, making the MAX12554 ideal for intermediatefrequency (IF) sampling applications. Powered from a single 3.3V supply, the MAX12554 consumes only 429mW while delivering a typical 70.9dB signal-to-noise ratio (SNR) performance at a 175MHz input fre ...
Digital Panel Meters Modular Indicator and Controller Type UDM35
... Up to 4 independent alarm set-points (optional) 20mA/10VDC analog output (optional) Serial port RS485 or RS232 (optional) MODBUS, JBUS communication protocol ...
... Up to 4 independent alarm set-points (optional) 20mA/10VDC analog output (optional) Serial port RS485 or RS232 (optional) MODBUS, JBUS communication protocol ...
Evaluates: MAX1889 MAX1889 Evaluation Kit General Description Features
... As configured, the negative charge pump uses one of the three charge-pump stages to generate approximately -7.6V and can provide greater than 10mA. The output is post-regulated to -7V using a linear-regulator controller and an external bipolar pass transistor. The negative linear regulator’s output ...
... As configured, the negative charge pump uses one of the three charge-pump stages to generate approximately -7.6V and can provide greater than 10mA. The output is post-regulated to -7V using a linear-regulator controller and an external bipolar pass transistor. The negative linear regulator’s output ...
MAX3291/MAX3292 RS-485/RS-422 Transceivers with Preemphasis for High-Speed, Long-Distance Communication ________________General Description
... becomes 10% or more of the baud period. ISI is caused by the effect of the cable’s RC time constant on different bit patterns. If a series of ones is transmitted, followed by a zero, the transmission-line voltage rises to a high value at the end of the string of ones (signal 1 in Figure 12). As the ...
... becomes 10% or more of the baud period. ISI is caused by the effect of the cable’s RC time constant on different bit patterns. If a series of ones is transmitted, followed by a zero, the transmission-line voltage rises to a high value at the end of the string of ones (signal 1 in Figure 12). As the ...
DS10BR150 1.0 Gbps LVDS Buffer / Repeater
... Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain t ...
... Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain t ...
See datasheet - Texas Instruments
... Four compensation points are made available to allow slight variations in the gain (slope) of the two individual 15-dB stages of input A2 and B2. By slightly changing the voltage on any of the compensation pins from its quiescent value, the gain of that particular 15-dB stage can be adjusted to matc ...
... Four compensation points are made available to allow slight variations in the gain (slope) of the two individual 15-dB stages of input A2 and B2. By slightly changing the voltage on any of the compensation pins from its quiescent value, the gain of that particular 15-dB stage can be adjusted to matc ...
MAX12555 14-Bit, 95Msps, 3.3V ADC General Description Features
... size. Excellent dynamic performance is maintained from baseband to input frequencies of 175MHz and beyond, making the MAX12555 ideal for intermediatefrequency (IF) sampling applications. Powered from a single 3.3V supply, the MAX12555 consumes only 497mW while delivering a typical 72dB signal-to-noi ...
... size. Excellent dynamic performance is maintained from baseband to input frequencies of 175MHz and beyond, making the MAX12555 ideal for intermediatefrequency (IF) sampling applications. Powered from a single 3.3V supply, the MAX12555 consumes only 497mW while delivering a typical 72dB signal-to-noi ...
Lab 1
... It can be seen from the truth table that the XOR gate is similar to the OR gate with the exception of the state in which both inputs are high. This feature makes the gate useful for binary adders, parity generators, etc. You have now illustrated the function of each type of gate in actual operation, ...
... It can be seen from the truth table that the XOR gate is similar to the OR gate with the exception of the state in which both inputs are high. This feature makes the gate useful for binary adders, parity generators, etc. You have now illustrated the function of each type of gate in actual operation, ...
ELEG2111 Lab 5
... using voltage divider biasing will be developed. The Q-point used for the previous lab’s design can be used for this lab’s design. B. Determining the amplifier input current. Generally an input signal to an amplifier is define as a voltage; however, a transistor’s input and output are defined by the ...
... using voltage divider biasing will be developed. The Q-point used for the previous lab’s design can be used for this lab’s design. B. Determining the amplifier input current. Generally an input signal to an amplifier is define as a voltage; however, a transistor’s input and output are defined by the ...
as a PDF
... Fig. 3 (a) is a schematic diagram of the proposed input-isolated comparator. It compares an input voltage (In) and the reference voltage (Vref) at the moment when the Clk signal changes from high to low. Fig. 3 (b) shows the simplified circuits of the comparator. When Clk is high, both the input and ...
... Fig. 3 (a) is a schematic diagram of the proposed input-isolated comparator. It compares an input voltage (In) and the reference voltage (Vref) at the moment when the Clk signal changes from high to low. Fig. 3 (b) shows the simplified circuits of the comparator. When Clk is high, both the input and ...
UNIVERSAL RS-232/422/485 CONVERTER FA-UNICON
... The five unassigned pins may carry nonstandard signals required by any individual system. Each signal is transmitted as a positive or negative electric current between 3 and 15 volts (usually 12 volts). The signal assigned to each pin flows in one direction only. Signals output, for example, from a ...
... The five unassigned pins may carry nonstandard signals required by any individual system. Each signal is transmitted as a positive or negative electric current between 3 and 15 volts (usually 12 volts). The signal assigned to each pin flows in one direction only. Signals output, for example, from a ...
NCN49597 - Power Line Communication Modem
... CENELEC. EN 50065−1−compliant system; for further information refer to the referenced design manual. This design is not galvanically isolated; safety must be considered when interfacing to a microcontroller or a PC. For synchronization the mains is coupled in via a 1 MW resistor; the Schottky diode ...
... CENELEC. EN 50065−1−compliant system; for further information refer to the referenced design manual. This design is not galvanically isolated; safety must be considered when interfacing to a microcontroller or a PC. For synchronization the mains is coupled in via a 1 MW resistor; the Schottky diode ...
INA114 数据资料 dataSheet 下载
... common-mode range of both input amplifiers. Since both input amplifiers are saturated to nearly the same output voltage limit, the difference voltage measured by the output amplifier will be near zero. The output of the INA114 will be near 0V even though both inputs are overloaded. INPUT PROTECTION ...
... common-mode range of both input amplifiers. Since both input amplifiers are saturated to nearly the same output voltage limit, the difference voltage measured by the output amplifier will be near zero. The output of the INA114 will be near 0V even though both inputs are overloaded. INPUT PROTECTION ...
ADS1251 数据资料 dataSheet 下载
... The digital filter of the ADS1251, referred to as a Sinc5 filter, computes the digital result based on the most recent outputs from the delta-sigma modulator. At the most basic level, the digital filter can be thought of as averaging the modulator results in a weighted form and presenting this avera ...
... The digital filter of the ADS1251, referred to as a Sinc5 filter, computes the digital result based on the most recent outputs from the delta-sigma modulator. At the most basic level, the digital filter can be thought of as averaging the modulator results in a weighted form and presenting this avera ...
MAX7322 I2C Port Expander with 4 Push
... On initial power-up, the MAX7322 cannot decode the address inputs AD2 and AD0 fully until the first I2C transmission. AD0 and AD2 initially appear to be connected to V+ or GND. This is important because the address selection determines the power-up logic state, and whether pullups are enabled. Howev ...
... On initial power-up, the MAX7322 cannot decode the address inputs AD2 and AD0 fully until the first I2C transmission. AD0 and AD2 initially appear to be connected to V+ or GND. This is important because the address selection determines the power-up logic state, and whether pullups are enabled. Howev ...
Page 43, Foundation Electronics, Kemp
... For each of the specifications below draw out the Karnaugh map and produce a circuit using NAND gates only to satisfy requirements. 30. The shuttle has a voting system whereby 3 computers vote on what to do. The final decision always goes with the majority so that if one computer goes down the other ...
... For each of the specifications below draw out the Karnaugh map and produce a circuit using NAND gates only to satisfy requirements. 30. The shuttle has a voting system whereby 3 computers vote on what to do. The final decision always goes with the majority so that if one computer goes down the other ...
CN-0123 利用自动校准技术将16通道、16位DAC AD5360的失调电压降至1 mV以下
... The circuit described here allows for the offset error of the main DACs to be measured and calibrated out under those conditions. The circuit relies on a general-purpose I/O pin and an on-chip monitor multiplexer. The GPIO (general-purpose I/O) pin is set as an input, and by reading the GPIO interna ...
... The circuit described here allows for the offset error of the main DACs to be measured and calibrated out under those conditions. The circuit relies on a general-purpose I/O pin and an on-chip monitor multiplexer. The GPIO (general-purpose I/O) pin is set as an input, and by reading the GPIO interna ...
Current Mode Interconnect - Department of Electrical Engineering
... Because of these problems with voltage mode signaling, we propose that 1’s and 0’s be signaled by the presence or absence of a current and not by a high or a low voltage. This has several advantages: • Current rise time is limited by inductance rather than capacitance. Typically, inductive effects a ...
... Because of these problems with voltage mode signaling, we propose that 1’s and 0’s be signaled by the presence or absence of a current and not by a high or a low voltage. This has several advantages: • Current rise time is limited by inductance rather than capacitance. Typically, inductive effects a ...
Flip-flop (electronics)
In electronics, a flip-flop or latch is a circuit that has two stable states and can be used to store state information. A flip-flop is a bistable multivibrator. The circuit can be made to change state by signals applied to one or more control inputs and will have one or two outputs. It is the basic storage element in sequential logic. Flip-flops and latches are a fundamental building block of digital electronics systems used in computers, communications, and many other types of systems.Flip-flops and latches are used as data storage elements. A flip-flop stores a single bit (binary digit) of data; one of its two states represents a ""one"" and the other represents a ""zero"". Such data storage can be used for storage of state, and such a circuit is described as sequential logic. When used in a finite-state machine, the output and next state depend not only on its current input, but also on its current state (and hence, previous inputs). It can also be used for counting of pulses, and for synchronizing variably-timed input signals to some reference timing signal.Flip-flops can be either simple (transparent or opaque) or clocked (synchronous or edge-triggered). Although the term flip-flop has historically referred generically to both simple and clocked circuits, in modern usage it is common to reserve the term flip-flop exclusively for discussing clocked circuits; the simple ones are commonly called latches.Using this terminology, a latch is level-sensitive, whereas a flip-flop is edge-sensitive. That is, when a latch is enabled it becomes transparent, while a flip flop's output only changes on a single type (positive going or negative going) of clock edge.