MAX9310 1:5 Clock Driver with Selectable LVPECL Inputs and LVDS Outputs General Description
... LVPECL Inputs and LVDS Outputs The MAX9310 is a fast, low-skew 1:5 differential driver with selectable LVPECL/HSTL inputs and LVDS outputs, designed for clock distribution applications. This device features an ultra-low propagation delay of 345ps with 45.5mA of supply current. The MAX9310 operates f ...
... LVPECL Inputs and LVDS Outputs The MAX9310 is a fast, low-skew 1:5 differential driver with selectable LVPECL/HSTL inputs and LVDS outputs, designed for clock distribution applications. This device features an ultra-low propagation delay of 345ps with 45.5mA of supply current. The MAX9310 operates f ...
UCC2808A-1Q1 数据资料 dataSheet 下载
... The output stages switch at half the oscillator frequency, in a push-pull configuration. When the voltage on the RC pin is rising, one of the two outputs is high, but during fall time, both outputs are off. This dead time between the two outputs, along with a slower output rise time than fall time, ...
... The output stages switch at half the oscillator frequency, in a push-pull configuration. When the voltage on the RC pin is rising, one of the two outputs is high, but during fall time, both outputs are off. This dead time between the two outputs, along with a slower output rise time than fall time, ...
NIM article 2009 - MC-PAD
... already at the lowest fluence and then stays constant. This is a hint of a surface effect which usually saturates at low doses. The saturation of the voltage at DAC values above 10 is due to the fact that the supply voltage of 2.5 V cannot be exceeded. Another parameter, which might be prone to radia ...
... already at the lowest fluence and then stays constant. This is a hint of a surface effect which usually saturates at low doses. The saturation of the voltage at DAC values above 10 is due to the fact that the supply voltage of 2.5 V cannot be exceeded. Another parameter, which might be prone to radia ...
AD9883A 110 MSPS/140 MSPS Analog Interface for Flat Panel
... This input is provided to assist with processing signals with embedded sync, typically on the Green channel. The pin is connected to a high speed comparator with an internally generated threshold. The threshold level can be programmed in 10 mV steps to any voltage between 10 mV and 330 mV above the ...
... This input is provided to assist with processing signals with embedded sync, typically on the Green channel. The pin is connected to a high speed comparator with an internally generated threshold. The threshold level can be programmed in 10 mV steps to any voltage between 10 mV and 330 mV above the ...
MAX13253 1A, Spread-Spectrum, Push-Pull, Transformer Driver for Isolated Power Supplies General Description
... 2A. When the 2A limit is exceeded, internal protection circuitry is immediately enabled, reducing the output current and regulating it to the 1.4A (typ) current-limit threshold. The MAX13253 monitors the driver current on a cycle-bycycle basis, and the driver output current is regulated to the curre ...
... 2A. When the 2A limit is exceeded, internal protection circuitry is immediately enabled, reducing the output current and regulating it to the 1.4A (typ) current-limit threshold. The MAX13253 monitors the driver current on a cycle-bycycle basis, and the driver output current is regulated to the curre ...
UC3825 数据资料 dataSheet 下载
... The ramp generator components, RT and CR are chosen so that the ramp at Pin 9 crosses the 1V threshold at the same time the desired maximum volt-second product is reached. The delay through the functional nor block must be such that the ramp capacitor can be completely discharged during the minimum ...
... The ramp generator components, RT and CR are chosen so that the ramp at Pin 9 crosses the 1V threshold at the same time the desired maximum volt-second product is reached. The delay through the functional nor block must be such that the ramp capacitor can be completely discharged during the minimum ...
Konstantin Stefanov`s talk at the ILC Vertex workshop at Ringberg
... Conversion to voltage and readout in the 200 ms-long quiet period after the train, RF pickup is avoided; 1 MHz column-parallel readout is sufficient; Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory ...
... Conversion to voltage and readout in the 200 ms-long quiet period after the train, RF pickup is avoided; 1 MHz column-parallel readout is sufficient; Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory ...
Comparison of Electromagnetic Interference
... Fundamental Structure of Periodic Signals Digital data transmission ideally is based on square-wave signals. However, in practice, signals have a limited slope because a certain time is required for the transition from one logic state to another. Therefore, it is realistic to study trapezoidal signa ...
... Fundamental Structure of Periodic Signals Digital data transmission ideally is based on square-wave signals. However, in practice, signals have a limited slope because a certain time is required for the transition from one logic state to another. Therefore, it is realistic to study trapezoidal signa ...
Flip-Flop
... Fig. (1-b) shows the meaning of Set and Reset states in terms of binary voltage levels. To see how F-F operates, refer to Fig. (1-a), Assume that the initial state is the (Set) state (L1 ON and L2 OFF), and that both the Set and Reset lines are low (0). The Set and Reset lines are both stable when ...
... Fig. (1-b) shows the meaning of Set and Reset states in terms of binary voltage levels. To see how F-F operates, refer to Fig. (1-a), Assume that the initial state is the (Set) state (L1 ON and L2 OFF), and that both the Set and Reset lines are low (0). The Set and Reset lines are both stable when ...
TPL5110 Nano-power System Timer for Power
... 50ms), the DRV signal will be high for the last 50ms of the time interval in order to turn off the MOSFET before the next cycle starts. The default value (after resistance reading) is HIGH. The signal is sent out from the TPL5110 when the programmed time interval starts. When the DRV is LOW, the man ...
... 50ms), the DRV signal will be high for the last 50ms of the time interval in order to turn off the MOSFET before the next cycle starts. The default value (after resistance reading) is HIGH. The signal is sent out from the TPL5110 when the programmed time interval starts. When the DRV is LOW, the man ...
single-time-constant circuits
... formed of an inductance L and a resistance R has a time constant τ = L/R. The time constant τ of an STC circuit composed of a capacitance C and a resistance R is given by τ = CR. Although STC circuits are quite simple, they play an important role in the design and analysis of linear and digital circ ...
... formed of an inductance L and a resistance R has a time constant τ = L/R. The time constant τ of an STC circuit composed of a capacitance C and a resistance R is given by τ = CR. Although STC circuits are quite simple, they play an important role in the design and analysis of linear and digital circ ...
Powering Your Ideas. PMBus™ Implementers Forum
... Transmitter: The device which sends data to the bus Receiver: The device which receives data from the bus Master: The device which initiates a transfer, generates clock signals and terminates a transfer Slave: The device addressed by a master Multi-master: More than one master can attempt to control ...
... Transmitter: The device which sends data to the bus Receiver: The device which receives data from the bus Master: The device which initiates a transfer, generates clock signals and terminates a transfer Slave: The device addressed by a master Multi-master: More than one master can attempt to control ...
70 MHz AND 140 MHz IF TO IF FREQUENCY CONVERTERS
... Shock and vibration.......................................... Normal handling by commercial carriers ...
... Shock and vibration.......................................... Normal handling by commercial carriers ...
MCF5474 数据手册 DataSheet 下载
... recommends the use of θJA and power dissipation specifications in the system design to prevent device junction temperatures from exceeding the rated specification. System designers should be aware that device junction temperatures can be significantly influenced by board layout and surrounding devic ...
... recommends the use of θJA and power dissipation specifications in the system design to prevent device junction temperatures from exceeding the rated specification. System designers should be aware that device junction temperatures can be significantly influenced by board layout and surrounding devic ...
Time-to-digital converter
In electronic instrumentation and signal processing, a time to digital converter (abbreviated TDC) is a device for recognizing events and providing a digital representation of the time they occurred. For example, a TDC might output the time of arrival for each incoming pulse. Some applications wish to measure the time interval between two events rather than some notion of an absolute time.In electronics time-to-digital converters (TDCs) or time digitizers are devices commonly used to measure a time interval and convert it into digital (binary) output. In some cases interpolating TDCs are also called time counters (TCs).TDCs are used in many different applications, where the time interval between two signal pulses (start and stop pulse) should be determined. Measurement is started and stopped, when either the rising or the falling edge of a signal pulse crosses a set threshold. These requirements are fulfilled in many physical experiments, like time-of-flight and lifetime measurements in atomic and high energy physics, experiments that involve laser ranging and electronic research involving the testing of integrated circuits and high-speed data transfer.