Si4770/77-A20 - Silicon Labs
... 4.9. Digital ZIF I/Q Interface (Si4777 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.10. IBOC Blend Mode for HD Radio (Si4777 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.11. Stereo Audio Processing . . . . . . . . . . . . . . . . . . . . . . . ...
... 4.9. Digital ZIF I/Q Interface (Si4777 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.10. IBOC Blend Mode for HD Radio (Si4777 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.11. Stereo Audio Processing . . . . . . . . . . . . . . . . . . . . . . . ...
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Reference Manual
... Figure 3 shows the different options available for configuring the FPGA. An on-board “mode” jumper (JP1) and a media selection jumper (JP2) select between the programming modes. The FPGA configuration data is stored in files called bitstreams that have the .bit file extension. The ISE or Vivado soft ...
... Figure 3 shows the different options available for configuring the FPGA. An on-board “mode” jumper (JP1) and a media selection jumper (JP2) select between the programming modes. The FPGA configuration data is stored in files called bitstreams that have the .bit file extension. The ISE or Vivado soft ...
No. 3| EURAMET Technical Guide |Use of GPS Disciplined Oscillators
... also the conformity of the output one-pulse-per-second (1 PPS) epoch with an agreed international reference time scale, usually UTC or its national realisation UTC(k) in laboratory k. Such a calibration is performed by operating the GPSDO at an NMI, DI or other suitable accredited calibration labor ...
... also the conformity of the output one-pulse-per-second (1 PPS) epoch with an agreed international reference time scale, usually UTC or its national realisation UTC(k) in laboratory k. Such a calibration is performed by operating the GPSDO at an NMI, DI or other suitable accredited calibration labor ...
MC145193F - West Florida Components
... to the innovative BitGrabber Plus registers. Therefore, all bits in the stream are available to be data for the three registers. Random access of any register is provided (i.e., the registers may be accessed in any sequence). Data is retained in the registers over a supply range of 2.7 to 5.5 V. The ...
... to the innovative BitGrabber Plus registers. Therefore, all bits in the stream are available to be data for the three registers. Random access of any register is provided (i.e., the registers may be accessed in any sequence). Data is retained in the registers over a supply range of 2.7 to 5.5 V. The ...
Experimental Comparison of Four Different CMOS Pixel
... and schematic diagram of which can be observed in Fig. 1(a) [2], was fabricated in logic-standard 0.5µm 1P3M twin-well LOCOS CMOS technology. The n-well PD requires an additional pixel storage capacitor Cs=1pF where a voltage proportional to the charge photogenerated during the integration phase can ...
... and schematic diagram of which can be observed in Fig. 1(a) [2], was fabricated in logic-standard 0.5µm 1P3M twin-well LOCOS CMOS technology. The n-well PD requires an additional pixel storage capacitor Cs=1pF where a voltage proportional to the charge photogenerated during the integration phase can ...
Si4063/60 - Silicon Labs
... The Si406x devices are high-performance, low-current, wireless ISM transmitters that cover the sub-GHz bands. The wide operating voltage range of 1.8–3.6 V and low current consumption make the Si406x an ideal solution for battery powered applications. A single high precision local oscillator (LO) is ...
... The Si406x devices are high-performance, low-current, wireless ISM transmitters that cover the sub-GHz bands. The wide operating voltage range of 1.8–3.6 V and low current consumption make the Si406x an ideal solution for battery powered applications. A single high precision local oscillator (LO) is ...
Konstantin Stefanov`s talk on LCFI at LCWS 2006
... Conversion to voltage and readout in the 200 ms-long quiet period after the train, RF pickup is avoided; 1 MHz column-parallel readout is sufficient; Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory ...
... Conversion to voltage and readout in the 200 ms-long quiet period after the train, RF pickup is avoided; 1 MHz column-parallel readout is sufficient; Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory ...
MAX9310A 1:5 Clock Driver with Selectable LVPECL Inputs/Single-Ended Inputs and LVDS Outputs
... The MAX9310A is a fast, low-skew 1:5 differential driver with selectable LVPECL inputs and LVDS outputs, designed for clock distribution applications. This device features an ultra-low propagation delay of 340ps with 48mA of supply current. The MAX9310A operates from a 3V to 3.6V power supply for us ...
... The MAX9310A is a fast, low-skew 1:5 differential driver with selectable LVPECL inputs and LVDS outputs, designed for clock distribution applications. This device features an ultra-low propagation delay of 340ps with 48mA of supply current. The MAX9310A operates from a 3V to 3.6V power supply for us ...
AN75 - Circuitry for Signal Conditioning and Power Conversion
... EX input, C1A switches high (trace C), biasing Q3 to stop the C1A clock. C1A’s high state also cuts off Q5, shutting down the current source. Q5’s gate going high bleeds a sub-microampere current through the 20M–Q1 path, maintaining ramp charging, but at a greatly reduced rate (this action is not re ...
... EX input, C1A switches high (trace C), biasing Q3 to stop the C1A clock. C1A’s high state also cuts off Q5, shutting down the current source. Q5’s gate going high bleeds a sub-microampere current through the 20M–Q1 path, maintaining ramp charging, but at a greatly reduced rate (this action is not re ...
IOSR Journal of Electrical and Electronics Engineering (IOSR-JEEE)
... As the voltage stress on the switches is smaller by using a flying capacitor buck converter, it is mainly used in applications which requires high power. Advantages of using this topology are voltage stress on the switches are reduced by half ,size of the inductor is reduced and efficiency is increa ...
... As the voltage stress on the switches is smaller by using a flying capacitor buck converter, it is mainly used in applications which requires high power. Advantages of using this topology are voltage stress on the switches are reduced by half ,size of the inductor is reduced and efficiency is increa ...
AN10830 - NXP Semiconductors
... Date of release: 23 September 2010 Document identifier: AN10830 ...
... Date of release: 23 September 2010 Document identifier: AN10830 ...
Time-to-digital converter
In electronic instrumentation and signal processing, a time to digital converter (abbreviated TDC) is a device for recognizing events and providing a digital representation of the time they occurred. For example, a TDC might output the time of arrival for each incoming pulse. Some applications wish to measure the time interval between two events rather than some notion of an absolute time.In electronics time-to-digital converters (TDCs) or time digitizers are devices commonly used to measure a time interval and convert it into digital (binary) output. In some cases interpolating TDCs are also called time counters (TCs).TDCs are used in many different applications, where the time interval between two signal pulses (start and stop pulse) should be determined. Measurement is started and stopped, when either the rising or the falling edge of a signal pulse crosses a set threshold. These requirements are fulfilled in many physical experiments, like time-of-flight and lifetime measurements in atomic and high energy physics, experiments that involve laser ranging and electronic research involving the testing of integrated circuits and high-speed data transfer.