UM0243
... As soon as stand alone mode has been detected, the motor is turned on. The first interrupt request is the one coming from pin PB5, the zero-crossing mains voltage detection pin, the sensitivity has been set so that both rising and falling edges of the signal generate the interrupt request. As soon a ...
... As soon as stand alone mode has been detected, the motor is turned on. The first interrupt request is the one coming from pin PB5, the zero-crossing mains voltage detection pin, the sensitivity has been set so that both rising and falling edges of the signal generate the interrupt request. As soon a ...
LTC6603
... L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. ...
... L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. ...
MAX5550 Dual, 10-Bit, Programmable, 30mA High-Output-Current DAC General Description
... One data bit transfers during each SCL rising edge. The MAX5550 requires nine clock cycles to transfer data into or out of the DAC register. The data on SDA must remain stable during the high period of the SCL clock pulse. Changes in SDA while SCL is high are read as control signals (see the START a ...
... One data bit transfers during each SCL rising edge. The MAX5550 requires nine clock cycles to transfer data into or out of the DAC register. The data on SDA must remain stable during the high period of the SCL clock pulse. Changes in SDA while SCL is high are read as control signals (see the START a ...
A Low-Power High-Precision Comparator With Time-Domain Bulk-Tuned Offset Cancellation
... If the step size of each correction is set small to have a fine resolution, the adaptation will take longer time with large initial offset. The dynamic switching approach used in [18] uses multiphase clock to temporarily store the offset in a capacitor, and then subtract it from the input. Based on ...
... If the step size of each correction is set small to have a fine resolution, the adaptation will take longer time with large initial offset. The dynamic switching approach used in [18] uses multiphase clock to temporarily store the offset in a capacitor, and then subtract it from the input. Based on ...
TPS40057-Q1 数据资料 dataSheet 下载
... The TPS40054 operates in one quadrant and sources output current only, allowing for paralleling of converters and ensures that one converter does not sink current from another converter. This controller also emulates a standard buck converter at light loads where the inductor current goes discontinu ...
... The TPS40054 operates in one quadrant and sources output current only, allowing for paralleling of converters and ensures that one converter does not sink current from another converter. This controller also emulates a standard buck converter at light loads where the inductor current goes discontinu ...
ZK-S12-B User`s Manual
... SETTINGS” section of the board to select whether to use the RS232, LIN, or to free the microcontroller’s RX and TX lines. Two 9-pin, D-Sub female connectors are provided for each RS-232 channel. 9. The “LIN” section contains two LIN transceivers, each capable of a speed of up to 100 Kbps in fast mod ...
... SETTINGS” section of the board to select whether to use the RS232, LIN, or to free the microcontroller’s RX and TX lines. Two 9-pin, D-Sub female connectors are provided for each RS-232 channel. 9. The “LIN” section contains two LIN transceivers, each capable of a speed of up to 100 Kbps in fast mod ...
On-Chip Signaling Techniques for High-Speed SerDes Transceivers The American University in Cairo
... Table 4.2 The results summary of the design in this chapter in TSMC 65nm CMOS technology 45 Table 4.3 The area distribution of the different parts of the design ............................................ 60 Table 4.4 The post layout results summary of the design in UMC 0.13μm CMOS ................ ...
... Table 4.2 The results summary of the design in this chapter in TSMC 65nm CMOS technology 45 Table 4.3 The area distribution of the different parts of the design ............................................ 60 Table 4.4 The post layout results summary of the design in UMC 0.13μm CMOS ................ ...
ncp1651 - Single Stage Power Factor Controller
... are forcing equipment to utilize input stages with topologies other than a simple off−line front end which contains a bridge rectifier and capacitor. There are also system requirements that dictate the use of PFC. In order to obtain the maximum power from an existing circuit in a building, the power ...
... are forcing equipment to utilize input stages with topologies other than a simple off−line front end which contains a bridge rectifier and capacitor. There are also system requirements that dictate the use of PFC. In order to obtain the maximum power from an existing circuit in a building, the power ...
Manual Pulse-Oper-Man-118175-03-Ver-1-4-0 Manual
... recorded simultaneously into current motor data and history data. * Pulse monitor card revision 1.3.0 - records a plug event when there are 10 motor starts within any 10-second period of operation. Motor Trip Event - Motor Trip Event - A motor trip event will be recorded when the monitor card termin ...
... recorded simultaneously into current motor data and history data. * Pulse monitor card revision 1.3.0 - records a plug event when there are 10 motor starts within any 10-second period of operation. Motor Trip Event - Motor Trip Event - A motor trip event will be recorded when the monitor card termin ...
![Figure.1. 16-Transistor full adder circuit [2]](http://s1.studyres.com/store/data/001255487_1-858a4a45c9148a769c8279528fccbe9b-300x300.png)
AK1543 - Asahi Kasei Microdevices
... The AK1543 is a Delta-Sigma Fractional-N PLL (Phase Locked Loop) frequency synthesizer with a frequency switching function, covering a wide range of frequencies from 400 to 1300MHz. This product consists of an 18-bit Delta-Sigma modulator, a low-noise phase frequency comparator, a highly accurate ch ...
... The AK1543 is a Delta-Sigma Fractional-N PLL (Phase Locked Loop) frequency synthesizer with a frequency switching function, covering a wide range of frequencies from 400 to 1300MHz. This product consists of an 18-bit Delta-Sigma modulator, a low-noise phase frequency comparator, a highly accurate ch ...
IOSR Journal of VLSI and Signal Processing (IOSR-JVSP)
... turn on the power supply without affecting the longest delay and the functionality. It is calculated as ((yo-Dmax), yo) in which yo is the latest arrival of the output signal and Dmax is the maximum delay of the logic gate. In true sense there is no need to turn on the gate before all signals arrive ...
... turn on the power supply without affecting the longest delay and the functionality. It is calculated as ((yo-Dmax), yo) in which yo is the latest arrival of the output signal and Dmax is the maximum delay of the logic gate. In true sense there is no need to turn on the gate before all signals arrive ...
A zero charge-pump mismatch current tracking loop for reference
... ripple on VCO control voltage in this mode are 0.013 μA and 0.6 mV, and 3.68 μA and 5.9 mV with the mismatch current reduction loop enabled and disabled, respectively, as shown in Figs. 10 and 11. Fig. 12 shows the static phase error and reference spur levels simulated across the PLL output frequenc ...
... ripple on VCO control voltage in this mode are 0.013 μA and 0.6 mV, and 3.68 μA and 5.9 mV with the mismatch current reduction loop enabled and disabled, respectively, as shown in Figs. 10 and 11. Fig. 12 shows the static phase error and reference spur levels simulated across the PLL output frequenc ...
Time-to-digital converter
In electronic instrumentation and signal processing, a time to digital converter (abbreviated TDC) is a device for recognizing events and providing a digital representation of the time they occurred. For example, a TDC might output the time of arrival for each incoming pulse. Some applications wish to measure the time interval between two events rather than some notion of an absolute time.In electronics time-to-digital converters (TDCs) or time digitizers are devices commonly used to measure a time interval and convert it into digital (binary) output. In some cases interpolating TDCs are also called time counters (TCs).TDCs are used in many different applications, where the time interval between two signal pulses (start and stop pulse) should be determined. Measurement is started and stopped, when either the rising or the falling edge of a signal pulse crosses a set threshold. These requirements are fulfilled in many physical experiments, like time-of-flight and lifetime measurements in atomic and high energy physics, experiments that involve laser ranging and electronic research involving the testing of integrated circuits and high-speed data transfer.