LTC6993-1/LTC6993-2/LTC6993-3/LTC6993-4
... Note 6: The TRIG pin has hysteresis to accommodate slow rising or falling signals. The threshold voltages are proportional to V+. Typical values can be estimated at any supply voltage using: VTRIG(RISING) ≈ 0.55 • V+ + 185mV and VTRIG(FALLING) ≈ 0.48 • V+ – 155mV Note 7: To conform to the Logic IC ...
... Note 6: The TRIG pin has hysteresis to accommodate slow rising or falling signals. The threshold voltages are proportional to V+. Typical values can be estimated at any supply voltage using: VTRIG(RISING) ≈ 0.55 • V+ + 185mV and VTRIG(FALLING) ≈ 0.48 • V+ – 155mV Note 7: To conform to the Logic IC ...
Metric propositional neighborhood logics on natural numbers
... PNL and the consistency problem for Allen’s Interval Networks have been studied in [35].1 In general, the satisfiability problem for an expressive enough interval temporal logic is much harder than the problem of checking the consistency of a constraint network. The higher complexity of the former i ...
... PNL and the consistency problem for Allen’s Interval Networks have been studied in [35].1 In general, the satisfiability problem for an expressive enough interval temporal logic is much harder than the problem of checking the consistency of a constraint network. The higher complexity of the former i ...
4 Digital Signal Processing in Measurements
... the maximum and minimum values of the signal can be detected as it is illustrated in Figure 4.13b. This technique is known as dithering. Beside described earlier conversion of the analog signal into digital code exist also other method of A/D conversion – for example conversion to number of pulses i ...
... the maximum and minimum values of the signal can be detected as it is illustrated in Figure 4.13b. This technique is known as dithering. Beside described earlier conversion of the analog signal into digital code exist also other method of A/D conversion – for example conversion to number of pulses i ...
DS1720 Econo – Digital Thermometer and Thermostat
... number of clock cycles that an oscillator with a low temperature coefficient goes through during a gate period determined by a high temperature coefficient oscillator. The counter is preset with a base count that corresponds to –55°C. If the counter reaches zero before the gate period is over, the t ...
... number of clock cycles that an oscillator with a low temperature coefficient goes through during a gate period determined by a high temperature coefficient oscillator. The counter is preset with a base count that corresponds to –55°C. If the counter reaches zero before the gate period is over, the t ...
ch_04_Ph_L_Digital_T..
... •RZ encoding has 3 values to build up sync per each bit. •the signal changes between and during each bit •1 represented by positive to zero (in the 2nd part of the bit) •0 represented by negative to zero (in the 2nd part of the bit) so it occupies more bandwidth. It is the most effective so far. ...
... •RZ encoding has 3 values to build up sync per each bit. •the signal changes between and during each bit •1 represented by positive to zero (in the 2nd part of the bit) •0 represented by negative to zero (in the 2nd part of the bit) so it occupies more bandwidth. It is the most effective so far. ...
MAX847 1-Cell, Step-Up Two-Way Pager System IC ________________General Description
... Specifications to -40°C are guaranteed by design, not production tested. This is not a tested parameter, since the IC is powered from OUT, not BATT. The only limitation in the BATT range is the inability to generate more than 5 times, or less than 1.15 times the BATT voltage at OUT. This is due to P ...
... Specifications to -40°C are guaranteed by design, not production tested. This is not a tested parameter, since the IC is powered from OUT, not BATT. The only limitation in the BATT range is the inability to generate more than 5 times, or less than 1.15 times the BATT voltage at OUT. This is due to P ...
L43067578
... Due to the lack of such controller in single stage converter means that (1) the primary side of the dc bus voltage is vary with line and load condition become excessive under high input line and light output load condition. (2) the absence of second controller is available to shape the input current ...
... Due to the lack of such controller in single stage converter means that (1) the primary side of the dc bus voltage is vary with line and load condition become excessive under high input line and light output load condition. (2) the absence of second controller is available to shape the input current ...
Less Than One in a Quadrillion—A Test Method
... difference between two adjacent samples in time exceeds the threshold limit, counting that sample as a conversion error. The counter must keep a cumulative total of errors throughout the duration of the testing. To ensure that the system is working as expected, the magnitude of the error vs. ideal s ...
... difference between two adjacent samples in time exceeds the threshold limit, counting that sample as a conversion error. The counter must keep a cumulative total of errors throughout the duration of the testing. To ensure that the system is working as expected, the magnitude of the error vs. ideal s ...
xc167ci_ds.pdf
... Non-Maskable Interrupt Input. A high to low transition at this pin causes the CPU to vector to the NMI trap routine. When the PWRDN (power down) instruction is executed, the NMI pin must be low in order to force the XC167 into power down mode. If NMI is high, when PWRDN is executed, the part will co ...
... Non-Maskable Interrupt Input. A high to low transition at this pin causes the CPU to vector to the NMI trap routine. When the PWRDN (power down) instruction is executed, the NMI pin must be low in order to force the XC167 into power down mode. If NMI is high, when PWRDN is executed, the part will co ...
SIMULATION WITH THE SEPIC TOPOLOGY (SEPIC-Single Ended Primary Inductance Converter)
... Now implement the schematic shown above in Figure 4 in NL5. It should look like Figure 5 below when complete. Vg is a DC voltage source (VDC) from the source library. It needs to be set for 120 volts. L1 is an ideal inductor from the library. Set to 500 µH. RL1 is an ideal resistor from the library ...
... Now implement the schematic shown above in Figure 4 in NL5. It should look like Figure 5 below when complete. Vg is a DC voltage source (VDC) from the source library. It needs to be set for 120 volts. L1 is an ideal inductor from the library. Set to 500 µH. RL1 is an ideal resistor from the library ...
MAX11661–MAX11666 500ksps, Low-Power, Serial 12-/10-/8
... 500ksps, Low-Power, Serial 12-/10-/8-Bit ADCs ELECTRICAL CHARACTERISTICS (MAX11666) (continued) (VDD = 2.2V to 3.6V, VREF = VDD, VOVDD = VDD. fSCLK = 8MHz, 50% duty cycle, 500ksps. CDOUT = 10pF, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1) ...
... 500ksps, Low-Power, Serial 12-/10-/8-Bit ADCs ELECTRICAL CHARACTERISTICS (MAX11666) (continued) (VDD = 2.2V to 3.6V, VREF = VDD, VOVDD = VDD. fSCLK = 8MHz, 50% duty cycle, 500ksps. CDOUT = 10pF, TA = -40NC to +125NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 1) ...
AN1978
... An important feature of the voltage regulator is the short-circuit protection that warns the sequencer block (see Figure 1) if the output current grows more than the short circuit current limit (about 90mA). In this case a deactivation sequence starts to protect the card and the OFF pin falls down w ...
... An important feature of the voltage regulator is the short-circuit protection that warns the sequencer block (see Figure 1) if the output current grows more than the short circuit current limit (about 90mA). In this case a deactivation sequence starts to protect the card and the OFF pin falls down w ...
AN2009-06 MIPAQ™ sense
... Shunts do not show effects like offset, hysteresis or distortion after exceeding the rated current limits e.g. during short circuit Shunts as sensors do not inherently limit the bandwidth of the measurement. ...
... Shunts do not show effects like offset, hysteresis or distortion after exceeding the rated current limits e.g. during short circuit Shunts as sensors do not inherently limit the bandwidth of the measurement. ...
AN10658 Sending I C-bus signals via long communications cables
... 1.1 Typical speed performance that can be achieved The typical speed performance that can be achieved are: Example A: 2 × PCA9600 communicating at 800 kHz over 20 m of Cat5e cable and exchanging 800 kHz, 3 mA level, I2C-bus signals with an Fm+ capable slave. Example B: 2 × P82B96 communicating at 40 ...
... 1.1 Typical speed performance that can be achieved The typical speed performance that can be achieved are: Example A: 2 × PCA9600 communicating at 800 kHz over 20 m of Cat5e cable and exchanging 800 kHz, 3 mA level, I2C-bus signals with an Fm+ capable slave. Example B: 2 × P82B96 communicating at 40 ...
www.BDTIC.com/TI LF155,LF347,LF351,LF353,LF356,LF357, LM311,LM313,LM329,LM386,LM3900,LM394 Application Note 263 Sine Wave Generation Techniques
... this term (Figure 8b). The RC feedback values will depend upon the thermal time constants of the oven used. The values shown are typical. The temperature of the oven should be set so that it coincides with the crystal's zero temperature coefficient or “turning point” temperature which is manufacture ...
... this term (Figure 8b). The RC feedback values will depend upon the thermal time constants of the oven used. The values shown are typical. The temperature of the oven should be set so that it coincides with the crystal's zero temperature coefficient or “turning point” temperature which is manufacture ...
Time-to-digital converter
In electronic instrumentation and signal processing, a time to digital converter (abbreviated TDC) is a device for recognizing events and providing a digital representation of the time they occurred. For example, a TDC might output the time of arrival for each incoming pulse. Some applications wish to measure the time interval between two events rather than some notion of an absolute time.In electronics time-to-digital converters (TDCs) or time digitizers are devices commonly used to measure a time interval and convert it into digital (binary) output. In some cases interpolating TDCs are also called time counters (TCs).TDCs are used in many different applications, where the time interval between two signal pulses (start and stop pulse) should be determined. Measurement is started and stopped, when either the rising or the falling edge of a signal pulse crosses a set threshold. These requirements are fulfilled in many physical experiments, like time-of-flight and lifetime measurements in atomic and high energy physics, experiments that involve laser ranging and electronic research involving the testing of integrated circuits and high-speed data transfer.