MAX1124 1.8V, 10-Bit, 250Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications
... up to 250Msps while consuming only 477mW. At 250Msps and an input frequency of 100MHz, the MAX1124 achieves a spurious-free dynamic range (SFDR) of 71dBc. Its excellent signal-to-noise ratio (SNR) of 57.1dB at 10MHz remains flat (within 1dB) for input tones up to 500MHz. This makes the MAX1124 ideal ...
... up to 250Msps while consuming only 477mW. At 250Msps and an input frequency of 100MHz, the MAX1124 achieves a spurious-free dynamic range (SFDR) of 71dBc. Its excellent signal-to-noise ratio (SNR) of 57.1dB at 10MHz remains flat (within 1dB) for input tones up to 500MHz. This makes the MAX1124 ideal ...
D i g l
... interface for the FPGA and Platform Flash ROM, and allows user data transfers (see www.digilentinc.com for more information). The Basys2 board is designed to work with the free ISE WebPack CAD software from Xilinx. WebPack can be used to define circuits using schematics or HDLs, to simulate and synt ...
... interface for the FPGA and Platform Flash ROM, and allows user data transfers (see www.digilentinc.com for more information). The Basys2 board is designed to work with the free ISE WebPack CAD software from Xilinx. WebPack can be used to define circuits using schematics or HDLs, to simulate and synt ...
Digital pixel readout integrated circuit architectures for LWIR
... as integrated voltage is equivalent to reference voltage. The fundamental difference amongst these approaches is that Delta-Sigma relies on clocked comparator as opposed to clock-free comparator in PFM. Higher charge handling capacity is achieved fairly well in both types of DROICs resulting in high ...
... as integrated voltage is equivalent to reference voltage. The fundamental difference amongst these approaches is that Delta-Sigma relies on clocked comparator as opposed to clock-free comparator in PFM. Higher charge handling capacity is achieved fairly well in both types of DROICs resulting in high ...
ADS5410 数据资料 dataSheet 下载
... little or no difference in performance between the singleended and differential-input configurations. The common mode of the clock inputs is set internally to AVDD/2 using 5-kΩ resistors (Figure 20). The clock input should be either a sine wave or a square wave having a 50% duty cycle. When driven w ...
... little or no difference in performance between the singleended and differential-input configurations. The common mode of the clock inputs is set internally to AVDD/2 using 5-kΩ resistors (Figure 20). The clock input should be either a sine wave or a square wave having a 50% duty cycle. When driven w ...
Low Power Designs with CoolRunner-II CPLDs
... toggles the internal logic of the CPLD. Any logic that changes state within the CPLD will consume power. Therefore, it follows that disconnecting the CPLD from the data bus when the device is not addressed conserves power. DataGATE solves this issue by disconnecting external signal activity from the ...
... toggles the internal logic of the CPLD. Any logic that changes state within the CPLD will consume power. Therefore, it follows that disconnecting the CPLD from the data bus when the device is not addressed conserves power. DataGATE solves this issue by disconnecting external signal activity from the ...
7- to 13-Bit Variable Resolution Incremental ADC Datasheet
... The selection of the input is done after the analog PSoC block is placed. The eight switched capacitor blocks have differing input selections. Each can be connected to most of its neighbors, while some can be directly connected to external input pins. Placement of the analog block must be done with ...
... The selection of the input is done after the analog PSoC block is placed. The eight switched capacitor blocks have differing input selections. Each can be connected to most of its neighbors, while some can be directly connected to external input pins. Placement of the analog block must be done with ...
Word - University of California, Berkeley
... takes for the capacitor to charge up another 90%. Assuming the effective resistance of an ‘ON’ transistor is R, consider again the two-step charging technique used in Part (b). How long does it take to charge the capacitor from 0 to 0.9*(VDD/2)? From there (after applying the second step), how long ...
... takes for the capacitor to charge up another 90%. Assuming the effective resistance of an ‘ON’ transistor is R, consider again the two-step charging technique used in Part (b). How long does it take to charge the capacitor from 0 to 0.9*(VDD/2)? From there (after applying the second step), how long ...
OPERATING MANUAL FOR SIX-SCR GENERAL PURPOSE GATE
... The firing circuit uses a phase-locked loop (PLL) circuit locked to the single phase mains voltage. A series of counters divide the PLL’s oscillator output and a decoder section then generates two 180°-wide delayed logic signals. These logic signals are modulated by the PLL’s voltage controlled osci ...
... The firing circuit uses a phase-locked loop (PLL) circuit locked to the single phase mains voltage. A series of counters divide the PLL’s oscillator output and a decoder section then generates two 180°-wide delayed logic signals. These logic signals are modulated by the PLL’s voltage controlled osci ...
ICS252 - Integrated Device Technology
... device with short traces. The X1 and X2 traces should not be routed next to each other with minimum spaces, instead they should be separated and away from other traces. 3) To minimize EMI, the 33Ω series termination resistor (if needed) should be placed close to the clock output. 4) An optimum layou ...
... device with short traces. The X1 and X2 traces should not be routed next to each other with minimum spaces, instead they should be separated and away from other traces. 3) To minimize EMI, the 33Ω series termination resistor (if needed) should be placed close to the clock output. 4) An optimum layou ...
remote control of devices using cellphones
... The first section comprises of three blocks: RC Network, Ring Detector and Schmitt Trigger. The RC Network & Ring Detector detects the incoming ring tone signals, which is in AC form, reduces it and fed to Schmitt Trigger. The job of the Schmitt Trigger is to convert that AC signals into digital pul ...
... The first section comprises of three blocks: RC Network, Ring Detector and Schmitt Trigger. The RC Network & Ring Detector detects the incoming ring tone signals, which is in AC form, reduces it and fed to Schmitt Trigger. The job of the Schmitt Trigger is to convert that AC signals into digital pul ...
DN2.49x - 16 channel 16 bit digitizerNETBOX up to 60 MS/s
... known from oscilloscopes it’s also possible to define a window trigger. All trigger modes can be combined with the pulsewidth trigger. This makes it possible to trigger on signal errors like too long or too short pulses. In addition to this a re-arming mode (for accurate trigger recognition on noisy ...
... known from oscilloscopes it’s also possible to define a window trigger. All trigger modes can be combined with the pulsewidth trigger. This makes it possible to trigger on signal errors like too long or too short pulses. In addition to this a re-arming mode (for accurate trigger recognition on noisy ...
Analog to Digital Converter
... Input Type – Differential or Single Ended Resolution - Most Important Scaling - allows the user to divide or multiply the input voltage to more closely match the full scale range of the ADC Sample Rate - The sample rate must be at least twice the frequency the you are measuring, but 5 times is much ...
... Input Type – Differential or Single Ended Resolution - Most Important Scaling - allows the user to divide or multiply the input voltage to more closely match the full scale range of the ADC Sample Rate - The sample rate must be at least twice the frequency the you are measuring, but 5 times is much ...
MACH Power
... MACH® devices have been designed with the capability to reset during system power-up. Following power-up, all flip-flops will be reset to LOW. The output state will depend on the logic polarity. This feature provides extra flexibility to the designer and is especially valuable in simplifying state m ...
... MACH® devices have been designed with the capability to reset during system power-up. Following power-up, all flip-flops will be reset to LOW. The output state will depend on the logic polarity. This feature provides extra flexibility to the designer and is especially valuable in simplifying state m ...
MAX3693 +3.3V, 622Mbps, SDH/SONET 4:1 Serializer with Clock Synthesis and LVDS Inputs
... frequency-synthesizing PLL (consisting of a phase/ frequency detector, loop filter/amplifier, voltagecontrolled oscillator, and prescaler). This device converts 4-bit-wide, 155Mbps data to 622Mbps serial data (Figure 1). The PLL synthesizes an internal 622Mbps reference used to clock the output shif ...
... frequency-synthesizing PLL (consisting of a phase/ frequency detector, loop filter/amplifier, voltagecontrolled oscillator, and prescaler). This device converts 4-bit-wide, 155Mbps data to 622Mbps serial data (Figure 1). The PLL synthesizes an internal 622Mbps reference used to clock the output shif ...
Time-to-digital converter
In electronic instrumentation and signal processing, a time to digital converter (abbreviated TDC) is a device for recognizing events and providing a digital representation of the time they occurred. For example, a TDC might output the time of arrival for each incoming pulse. Some applications wish to measure the time interval between two events rather than some notion of an absolute time.In electronics time-to-digital converters (TDCs) or time digitizers are devices commonly used to measure a time interval and convert it into digital (binary) output. In some cases interpolating TDCs are also called time counters (TCs).TDCs are used in many different applications, where the time interval between two signal pulses (start and stop pulse) should be determined. Measurement is started and stopped, when either the rising or the falling edge of a signal pulse crosses a set threshold. These requirements are fulfilled in many physical experiments, like time-of-flight and lifetime measurements in atomic and high energy physics, experiments that involve laser ranging and electronic research involving the testing of integrated circuits and high-speed data transfer.