Download Lab 4

ECE 53: Fundamentals of Electrical Engineering
Laboratory Assignment #4:
MOS Logic Gates
General Guidelines:
- Record data and observations carefully for each lab measurement and experiment.
- You must obtain Lab. Assistant’s signature on each page of your lab data before
leaving the lab. Signed pages must be included in the report.
- Make sure you understand the experiment procedure before executing it. You must
obtain enough data to complete the various parts of the procedure.
- Request Lab Assistant’s help to verify your circuit before turning on the power
supplies and generators.
- Please operate the equipment in a reasonable manner. Avoid power supply short
circuits. Report failures to the Lab. Assistant.
Parts:
-Resistors as needed
-MOSFET integrated circuits (CD4007)
Equipment:
Breadboard
Digital Multimeter (DMM)
Signal Generator
Oscilloscope
Objective:
The objective of this session is to implement various logic gates using MOS Field-Effect Transistors.
Background:
SPICE models corresponding to the CD4007 chip:
NMOS: LEVEL=1, VTO=1.4, L=5e-6, W=124e-6, TOX=1080e-10, LAMBDA=0.01, KP=20e-6, PHI=0.6,
GAMMA=1.5
PMOS: LEVEL=1, VTO=-1.4, L=5e-6, W=480e-6, TOX=1080e-10, LAMBDA=0.02, KP=6e-6, PHI=0.6,
GAMMA=1.5
Laboratory Experiment & Procedure:
Part A – N-Channel MOS Inverter
Circuit Analysis:
1. Consider the NMOS inverter circuit above with VDD = 5V and RL = 2.2 kΩ, compute values for Vo
when Vi = 0 V, 2.5 V and 5V. (Assume K = 0.6 mA/V2.)
PSPICE Simulation:
2. Set up the NMOS inverter above using the appropriate SPICE model (see page 1).
3. Perform a DC sweep of the input voltage from 0V to 5V, at 0.25V increments.
4. Record the output values (Vo) when the input is 0V, 2.5V and 5V.
5. Using the plot functions, plot Vo (y-axis) vs. Vi (x-axis). Label the axes scales and units.
Identify when the MOS is in cutoff, linear, and saturation regions.
6. Using the output values Vo for Vi = 2.5V and 5V, solve for the parameter K in the MOS IDS =
f(VDS) equations for the linear and saturation regions. Use the equations appropriately!!!
Measurement Procedure:
For this experiment use the NMOS inverter that is attached to pins 6, 7, and 8. Assemble the
circuit on the prototype-board, using RL = 2.2 kΩ. Set up the function generator to produce a
triangular wave with peak-to-peak amplitude of 5V and a DC offset of 2.5V similar to
experiment 1. Attach scope channel A to the input and channel B to the output of the gate. Set
the scope display to XY mode. You should see the transfer characteristics of the inverter
circuit on the scope display.
7. Make a hard copy of the transfer function Vo (y-axis) vs. Vi (x-axis) and on the hard copy, draw
Vi and Vo axes and label and mark the voltage scales. Identify regions in which MOS is in cut-off,
linear, and saturation regions.
8. Measure Vo for Vi = 2:5 and 5 V. In each case, solve the MOS circuit and find the value of the
parameter K (in MOS IDS = f(VDS) equations).
Comparison/Discussion:
9. Compare experimental results to your circuit analysis and PSPICE. EXPLAIN ANY
DISCREPANCIES >10%.
a. When Vin = 0 V, does Vout match? Vin = 2.5, and Vin = 5V? (% difference)
b. Does the K parameter found in PSPICE and experimentally match? What’s the percent
difference? How does that compare to the assumption of K made in the circuit analysis?
Part B – CMOS Inverter
Circuit Analysis:
1. Consider the CMOS inverter circuit above with VDD = 5V, compute values for Vo when Vi = 0 V,
2.5 V and 5V. (Assume K = 0.6 mA/V2.)
2. Compute peak current ID when Vi = 2.5V.
PSPICE Simulation:
3. Set up the CMOS inverter above using the appropriate SPICE model (see page 1).
4. Perform a DC sweep of the input voltage from 0V to 5V, at 0.25V increments.
5. Record the output values (Vo) when the input is 0V, 2.5V and 5V.
6. Using the plot functions, plot Vo (y-axis) vs. Vi (x-axis). Label the axes scales and units.
Identify when the MOS is in cutoff, linear, and saturation regions.
7. Using the plot functions, plot ID (y-axis) vs. Vi (x-axis). Label the axes scales and units.
Measurement Procedure:
For this experiment use the CMOS inverter that is attached to pins 9 through 12. Assemble the
circuit on the prototype-board. As in
experiment 1, set up the function
generator to produce a triangular wave
with a peak-to-peak amplitude of 5 V
and a DC offset of 2.5 V. Apply this
signal to the input of the gate. Attach
scope channel A to the input and scope
channel B to the output. Set the scope
display to XY mode. You should see
the transfer characteristics of the
inverter circuit on the scope display.
8. Make a hard copy of the transfer
function Vo (y-axis) vs. Vi (x-axis) and
on the hard copy, draw Vi and Vo axes
and label and mark the voltage scales.
Identify regions in which NMOS and
PMOS are in cut-off, linear, and
saturation regions.
9. A major advantage of CMOS inverter is that it draws zero current when it is in high or low state.
However, the drain current is not zero when CMOS is transitioning between states. To see this,
attach a 100Ω resistor between pin 9 and ground. The voltage across this resistor will be
proportional to drain current. Apply the triangular wave above to the input of the gate. Attach
scope channel A to the input and scope channel B to the 100Ω resistor. Set the scope display to
XY mode. You should see a plot of ID vs Vi. Make a hard copy and on the hard copy, draw vi and
iD axis and label and mark the voltage and current scales. Compare the maximum values of iD
with your calculations.
Comparison/Discussion:
10. Compare experimental results to your circuit analysis and PSPICE. EXPLAIN ANY
DISCREPANCIES >10%.
a. When Vin = 0 V, does Vout match? Vin = 2.5, and Vin = 5V? (% difference)
b. Does the peak current ID when Vi = 2.5V found in PSPICE and experimentally match?
What’s the percent difference? How does that compare to peak current found in the circuit
analysis?
11. Comment on the advantages and disadvantages of the CMOS inverter over the NMOS
inverter.
Part C – CMOS NOR Gate
Circuit Analysis:
1. Show that the circuit above acts like a NOR gate. (You can do this by indicating the transistor
is on or off. If the transistor is on, it looks like short circuit. if it is off, it looks like an open. This is
not an exact answer, but a good approximation. Remember that when you make an assumption,
you will have to verify that before the problem is considered complete.)
PSPICE Simulation:
2. Perform a transient response simulation. You can demonstrate NOR operation but sending
two square waves. Send one square wave (using VPULSE) to Input A with period T. Send
another one to Input B with period 2*T. Based on the simulation results, show how the circuit
corresponds to the NOR operation using a truth table.
Measurement Procedure:
For this experiment use the CMOS inverter that is attached to pins 9 through 12 and MOS
transistors with the gate connected to pin 6. Draw the circuit diagram NOR gate in your lab
report and identify chip pins on the circuit diagram and explain which pins should be
connected together. Wire your chip to make a two-input NOR gate. Test your NOR gate with
attaching a 1 kHz square wave (0-5 V) to pin 6 and a DC voltage of either zero or 5 V to pin
10. In each case, attach the waveform to the lab report. Describe the output waveform in each
case and explain how it corresponds to the NOR of the two inputs, using a truth table format.
3. Draw the circuit diagram (provided above as an example). Identify and explain how you
connected the pins (you can do this by writing now the pin number next to the gate, source, and
drain of the FETs on the circuit diagram).
4. Wire your chip to make a two-input NOR gate.
5. Test your NOR gate with attaching a 1 kHz square wave (0-5 V) to pin 6 and a DC voltage of
case(a) 0V and case(b) 5 V to pin 10. In each case, attached the hardcopies of input and
output waveform to the lab report.
6. Describe how the output waveform corresponds to NOR gate operation, using a truth table.
Part D – CMOS NAND Gate
Circuit Analysis:
7. Show that the circuit above acts like a NAND gate. (You can do this by indicating the
transistor is on or off. If the transistor is on, it looks like short circuit. if it is off, it looks like an open.
This is not an exact answer, but a good approximation. Remember that when you make an
assumption, you will have to verify that before the problem is considered complete.)
PSPICE Simulation:
8. Perform a transient response simulation. You can demonstrate NAND operation but sending
two square waves. Send one square wave (using VPULSE) to Input A with period T. Send
another one to Input B with period 2*T. Based on the simulation results, show how the circuit
corresponds to the NAND operation using a truth table.
Measurement Procedure:
For this experiment use the CMOS inverter that is attached to pins 9 through 12 and MOS
transistors with the gate connected to pin 6. Draw the circuit diagram NAND gate in your lab
report and identify chip pins on the circuit diagram and explain which pins should be
connected together. Wire your chip to make a two-input NAND gate. Test your NAND gate
with attaching a 1 kHz square wave (0-5 V) to pin 6 and a DC voltage of either zero or 5 V to
pin 10. In each case, attach the waveform to the lab report. Describe the output waveform in
each case and explain how it corresponds to the NAND of the two inputs, using a truth table
format.
9. Draw the circuit diagram (no figure provided – for the student to figure out). Identify and explain
how you connected the pins (you can do this by writing now the pin number next to the gate,
source, and drain of the FETs on the circuit diagram).
10. Wire your chip to make a two-input NAND gate.
11. Test your NAND gate with attaching a 1 kHz square wave (0-5 V) to pin 6 and a DC voltage of
case(a) 0V and case(b) 5 V to pin 10. In each case, attached the hardcopies of input and
output waveform to the lab report.
12. Describe how the output waveform corresponds to NAND gate operation, using a truth table.
Supplemental Material: