Download Low Power VLSI Design

Low Power VLSI Design
3EC1241
Course Learning Outcome:
• To understand the issues related with the power dissipation in VLSI
• To Design High Speed VLSI from power point of view
• Understand the different techniques of designing low power VLSI
circuits for high density VLSI
Books:
• Gary K. Yeap, Practical Low Power Digital VLSI
Design, Kluwer Academic Publishers
• Rabaey,
Pedram,
Low
power
design
methodologies, Kluwer Academic Publishers
• Kaushik Roy, Sharat Prasad, Low-Power CMOS
VLSI Circuit Design, John Wiley & Sons
• Kint-Seng & Kaushik Roy, Low Voltage Power
VLSI Subsystems, TataMcGraw-Hill
• Anantha Chandrakasan, Low Power CMOS
Design, IEEE Press
Component Weightage
Class Test
Sessional Examination
Special Assignment
Credit
0.3
0.4
1=0.3
3
Outline
• Why low power
• Power Vs Energy
• Sources of power dissipation
• Why leakage power is important
• Course outline
Changing Trend
• Until recently performance has been synonymous with circuit speed
or processing i.e MIPS or MFLOPS
• Implementation involve area-time trade off
• Performance(Speed) and chip area(circuit density/cost)
• Power consumption were secondary concern
Changing Trend
• Power dissipation was neglected due to
- Low device density
- -low operating frequency
Changing Trend
• In nanometre technology power has become the most important
issue because of
- Transistor counts
- Higher speed of operation
- Need of portable consumer electronics
- Greater device leakage currents
- Concerns on environments and energy sources
• Increased process parameters variability due to aggressive scaling has
created problems in yield, reliability, and testing
Packaging and cooling cost
• Contemporary high performance processors consume heavy power
• Cost associated with packaging and cooling such devices is prohibitive
Why low power?
• Increasing power density of VLSI chips
Why low power?
Portable systems:
• Increased customer demand for hand held ,battery operated devices
• Cell phones with limitless power supply and limitless functionality
• Growth rate of these portable equipment is very high
• For these devices, battery life is so important
• Commercial success of these products depends on size, weight, cost,
computing power and battery life
• Need lower power methodology
Why low power?
• Reliability
Thermal runaway
Gate dielectric
Junction diffusion
Electro migration diffusion
Electric parameters shift
Package related failure
Silicon interconnect
Every 10◦C rise in temperature roughly doubles failure rate
Why low power?
Environment:
• According to an estimate of the U.S. environment protection energy,
80% power consumption by office equipment
• Heating to environment
• Power management standards for laptops and desktops
• Drive towards green PC
Power Vs Energy
• Types of power:
- Peak power
- Average power
- Power and energy
Energy and Power Power is height of curve
Watts
Approach 1
Approach 2
time
Energy is area under curve
Watts
Approach 1
Approach 2
time
Energy = Power * time for calculation = Power * Delay
15
CMOS: the Technology of choice
Advantages:
• Ease of fabrication
• Good noise margin
• Robust
• Lower switching activity
• Good input/output decoupling
• No charge sharing problem
• Availability of matured logic
• Synthesis tool and techniques
CMOS: the Technology of choice
Disadvantages:
• Larger number of transistors
• Weak output current driving capacity
• Large number of standard cell
• Glitching power dissipation
• Short circuit power dissipation
Sources of power dissipations
Dynamic power
• Switching power
• Short circuit power
• Glitching power
Static power
• Diode leakage current
• Subthreshold leakage current
• Gate leakage current
Switching power
Short circuit power
Glitching power
A
B
X
Z
C
ABC
101
000
X
Z
Unit Delay
21
Static power Dissipation
• When device is in standby mode
• Significant for lower technology
• Components
-Reversed biased pn junction
-Sub threshold leakage
-DIBL leakage
-Channel punch through
-GIDL leakage
-Oxide leakage
-Hot carrier tunnelling effect
Why leakage power is an issue?
• In stand by applications, leakage components becomes a significant %
of total power
• Leakage current increases at a faster rate than dynamic power in
technology generations
Why leakage power is an issue?
• REDUCTION OF RUNTIME LEAKAGE POWER IS IMPORTANT
Low Power Design Methodology
• Low power design methodologies are to be applied throughout the
design process from system level to layout level, gradually refining or
detailing the abstract specification or model of the design
• System specification>system level design
• Behavioural description>High level synthesis
• Structural RTL description>logic synthesis
• Logic level netlist>layout synthesis=layout
Levels of Optimization
Speed
> 70 %
Seconds
> 50 %
40-70 %
Minute
25-50 %
25-40 %
Minutes
15-30 %
Gate
15-25 %
Hour
10-20 %
Transistor
10-15 %
Hours
5-10 %
MEM
System
ALU
MP3
Algorithm
Architecture
MEM
Savings
T1
T
T
S
+
Error
nach Massoud Pedram
26
Degree of Freedom
• Degrees of freedom inherent in the low power design space
Supply voltage
Physical capacitance
Switching activity
Threshold voltage
• Categorization of basic approaches
Supply voltage scaling
Minimizing switched capacitance
Minimizing leakage power
6
10
5
8
4
Pdyn
td
3
6
4
2
1
2
0
0
0.8
1
1.2
1.4
1.6
1.8
2
2.2
Relative Pdyn
Relative Delay td
VDD versus Delay and Power
2.4
Supply voltage (VDD)
• Delay (td) and dynamic power consumption (Pdyn) are functions
of VDD
28
Multiple VDD
• Main ideas:
• Use of different supply voltages within the same design
• High VDD for critical parts (high performance needed)
• Low VDD for non-critical parts (only low performance demands)
• At design phase:
• Determine critical path(s)
• High VDD for gates on those paths
• Lower VDD on the other gates
• For low VDD: prefer gates that drive large capacitances (yields the largest energy benefits)
• Usually two different VDD
29
summary
• Power dissipation is already a prime design constraint
• Low power design requires operation at lower possible voltage and
clock speed
• Power dissipation is unavoidable especially as technology scales down
• Techniques must be devised to reduce power dissipation
• Techniques must be devised to accurately estimate the power
dissipation
• Estimation and modelling of the sources of power dissipation for
simulation purposes
Course Outline
Need for low power VLSI chips
Simulation of Power analysis
Probabilistic power analysis
Low Power Design, Circuit level
Low power digital cells library Logic level
Low power Architecture & Systems
Low power Clock Distribution
Algorithm & architectural level methodologies