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COEN451 Week 7 POWER CONSUMPTION IN CMOS CIRCUITS Recent technology has shown that power is the bottle neck of designing larger chips or running them faster or putting more functions. Large chips consume from say 50W to 150 W with a Vdd=1 volt.. That means that the supply current is in the order of 100Amps, keeping the temp down and steady is the problem. Two Components contribute to the power dissipation: Static Power Dissipation – Leakage current – Sub-threshold current Dynamic Power Dissipation – Short circuit power dissipation – Charging and discharging power dissipation Static Power Dissipation Leakage Current: The cross section of the CMOS inverter shown below indicates that the leakage current is mainly due to P-N junction reverse biased currents. Typical values: 0.1nA to 0.5nA @room temp. Page 1 of 14 Lecture#6 Overview The leakage current IL for each diode is obtained by: q. v I L I S ( e kT 1) , I S is obtained from the process manual. It is possible to estimate leakage current for a gate or for the circuit. n Ps leakage current * supply vol tage 1 Sub-threshold Current • Relatively high in low threshold device Sub-threshold current is prominent in short devices. Current starts to flow in small quantities when Vin is approaching Vt. Page 2 of 14 Lecture#6 Overview DYNAMIC POWER DISSIPATION Short circuit current: A. B. C. D. Input VTC Current flow Current flow when load is increased The input ramp is exaggerated to show the effect of the ramp. As can be seen during transition due to input signal whenever the pMOS and nMOS are both are on, then a direct path exists between Vdd and Vss. For tr=tf = trf VTN=|VTP| The short circuit power dissipation: I (Vdd 2Vt ) 3 ( tr , f ) 12 tp Heavier loads also contribute. The model above indicates the short circuit current without load condition. So it mainly depends, on device geometries, Vdd and rise time and fall time of the input signal. Page 3 of 14 Lecture#6 Overview Dynamic power This component of power dissipation is due to charging and discharging of the load capacitance and is the major contributor component of power dissipation. During each clock cycle the load capacitor charges and discharges tp 1 P tp 2 1 0 inVdd dt t p tp i p (Vdd Vo ) dt tp 2 i CL dVds dt tp tp 1 2 1 P CLVout dVout CL (Vdd Vo )d (Vdd Vo ) tp 0 tp tp 2 P f .CL .V 2 dd , where f is frequency of operation, Vdd is the voltage supply and CL is the load capacitance. Total power = Pleakage + Psub-threshold +Pdynamic + Pshort-circuit Page 4 of 14 Lecture#6 Overview How Power is split among different Chip Components. Page 5 of 14 Lecture#6 Overview ARCHITECTURAL DESIGN TECHNIQUES TO REDUCE POWER CONSUMPTION Methods to reduce power consumption are many. Architectural design is one. In the following set of examples we reduce Vdd, yet compensate for the reduction in speed and throughput with, pipelining and parallelism. A computational structure Pipelined computational structure to increase frequency of operation Parallelising the structure to increase throughput Page 6 of 14 Lecture#6 Overview Parallelising and pipelining to increase speed and throughput Assuming constant delay, ARCHITECTURE Basic Pipelined Parallel Parallel and Pipelined VOLTAGE (V) 5.0 2.9 2.9 2.0 AREA (cm2) 1.0 1.3 3.4 3.7 POWER (W) 1.00 0.39 0.36 0.20 Power is obtained by P f .CL .V 2 dd . Page 7 of 14 Lecture#6 Overview METHODOLOGIES FOR REDUCING POWER DISSIPATION THROUGH ACTIVITY REDUCTION Usually not all subsystems are operating and active at the same time, thus the above model can be changed to take care of the activity. A more refined model is P a. f .C L .V 2 dd where ‘a’ is the activity factor. Page 8 of 14 Lecture#6 Overview ACTIVITY OF A GATE Yet another method of power reduction is to reduce the switching activity or the transitions experienced by a capacitive load. To be able to do this we have to have an intimate knowledge of the circuit and the input signals in terms of their probability of being at state ‘1” or “0”. Let P0 and P1 be the probability of having a logic “0” or “1” at the output of a gate. Then P0 = (1-P1) and switching P0 → 1 = P0. P1. Consider a 2-input AND gate, if we assume that the probability of input A of being at logic ‘1’ is the same as the probability of input B, which is 50%. A B 0 0 1 1 0 1 0 1 3 4 1 P1 4 P0 Y 0 0 0 1 3 3 9 * 4 4 16 3 1 3 P01 * 4 4 16 1 3 3 P10 * 4 4 16 1 1 1 P11 * 4 4 16 P00 EXAMPLE OF ACTIVITY REDUCTION PB 0.8 PA 0.4 PC 0.1 If PB>PA>PC, k will switch many times more unnecessarily, in the first case, rearranging the inputs: Initial Circuit A better arrangement CONCLUSION: Always attempt to place the signal with the highest probability of switching nearer to the output or the end of the circuit. Page 9 of 14 Lecture#6 Overview Interconnects Wire inter connects are used to connect, transistors, gates, modules, supply power, clock signal, etc. The metal interconnects layers found in silicon chips are usually laid out in horizontal and vertical directions and being thicker at the top. They are arranged according to specific hierarchy which depend on the type of connection provided (near or far locality). They exist as local, semi-global and global interconnects. Examples of global interconnects include VDD, VSS and clock lines. Via Vias are Contact Cuts used to connect two metal layers together. The connection could be of the upper layer type or Tungsten. Electromigration Electromigration is the forced movement of metal ions due to the application of an electric field. It can deform the conductor or lead to a complete failure. It depends primarily on current density in the conductor as well as temperature and crystal structure. To determine the conductor size we have to use a safe current density. Fabrication process data sheet usually provide the safe current density (Jm), which is usually around 1→2mA/µm2 for aluminum. Most wires nowadays are made from alloy of aluminum and copper or copper. These wires have a higher current density tolerance, up to 10mA/µm2 Incubation Period With time, due to electromigration, the resistance of metal connector change. The incubation period of a metal is the amount of time observed for a metal to change its resistance characteristics. The resistance depends on: Type of metal Structure of metal Electromigration threshold value Dimension Temperature Page 10 of 14 Lecture#6 Overview To determine the conductor quality, we usually use the Mean Time To Failure (MTTF) measure. As current density increases, the MTTF decreases (more subjective to failure). This parameter is different for AC and DC current. Example: AC clock distribution network will have different MTTF to a DC power line. For a DC interconnect, the MTTF is defined as: E , where A is the area, Jm is the current density, E is 0.5eV, K kT is the Boltzsman constant, and T is the absolute temperature. MTTFDC AJm 2 exp For AC interconnect, the MTTF is defined as: E kT , where J m is the average current density, J m is the MTTFDC 2 AC Jm Jm k Jm DC AC average absolute current density and is a constant. DC A exp Example What is the maximum current that a 5um wide metal 2 can carry? (assume Jm = 1mA/um2 and a 1µm thick aluminum) Imax = Jm * Area 1 * (5 * 1) 5mA Page 11 of 14 Lecture#6 Overview Example How many contacts of 1 um * 1um is required for metal-1 carrying 10mA in order to connect to metal-2? Assume each contact of 1um * 1um can carry 0.5mA safely or 0.1mA/um of periphery. Ans: 20 Design tips: Do not design one big contact due to current crowding. Sometimes it is necessary to increase the number of contacts to have higher periphery contact so as to reduce the current crowding. See the process manual for more information. Resistive drop. For long wires the resistive drop could be substantial. We should rout essential wires and size them to reduce potential drop. Example Assume a chip of 0.5cm by 0.5cm fed by one Vdd pad. The chip consumes 1A at 3.3Volts. The layout is given below. Determine the voltages on points marked X, Y and Z. Are these values Acceptable? If not what can you do about it? (assume Jm = 1mA/um2 and a 1µm thick aluminum) Page 12 of 14 Lecture#6 Overview Ans: You will realize that although this width satisfies the current density threshold, they are unrealistic as they consume large portion of the chip area. Assume J=1mA/um2, we have a symmetrical drawing about B. Distance from B to X = 2500 + 2500 + 1500 = 6500 um Assume R = 0.06 / from process manual 2500 µ 500µ 1500µ 200µ 2500µ Number of squares= 4+ 2/3 +1+ 2/3 + 10 =16.5 (5 + 4/3 carrying 500mA and 10 carrying 200mA) Voltage drop = 0.06 * 6.1/ 3* 500mA + 0.06 * 10 * 200mA = 310mV V 310mV or 0.31V which is around 10% of Vdd. (This is an approximation aimed at showing the effect of DC voltage drop) Other voltages can be determined the same way. That means that Voltage at point Z will be much lower than X. Assume a 3.3V voltage supply, V=3.3-0.31=3.02V, which is not acceptable. In today’s technologies One solution is to increase the wire width. But that will eat into the limited amount of metal interconnect available for the design. Alternatively, you can increase the number of voltage supply pads on the chip ( as well as widening the supply lines). Page 13 of 14 Lecture#6 Overview For example if we use 4 Vdd pads instead of one then the width of the power distribution can be reduced, The length of each segment is also reduced and overall contributing to less area loss. Example: Assume a moderate size chip consuming 20 watts at 1V. This is 20Amp to be distributed around the chip. Assuming each pad handles 200mA, then we would require 100 +100 Power supply pads. Current ASIC and FPGA can have hundreds of Vdd and Vss pads. Power Buses have to be sized according to the maximum current that they carry to avoid electromigration. Each metal line has a defined thickness and an electromigration limit given in mA/µm.(for that given thickness). Higher levels metals have greater current carrying capability. Always check your process technology parameters for design. An example : JA (mA) t ( µm ) R (mΏ) Met 1 1mA 0.75 100 Met 3 2 1.2 50 So far, we have only considered DC analysis and only resistive drops! AC analysis due to di/dt and dv/dt of inductive and capacitive loads has to be taken into account. These are called Vdd and Ground bounce. Page 14 of 14 Lecture#6 Overview