Download Designing A Very High Output Resistance Current Source

Proceedings of the 13th WSEAS International Conference on CIRCUITS
Designing A Very High Output Resistance Current Source
K. Hayatleh, N. Terzopoulos, B. Hart
School of Technology, Oxford Brookes University
Oxford, OX33 1HX,
UNITED KINGDOM
[email protected]
Abstract— A new technique is proposed in this paper in order to design a current source in bipolar technology
with very high output resistance while minimising output capacitance. Such techniques are useful in Electrical
Impedance Tomography applications. First of all, D.C. relationships are established. Then, an expression based
on the analysis of a simplified equivalent circuit, is formulated for the output resistance and tested against
simulation results for both ideal and practical biasing circuits.
The effect of circuit capacitances, and in particular the role of the collector-base capacitance of the output
transistor, in determining the output impedance as a function of frequency is considered. Finally, some new
circuits with output impedances much greater than that of the basic Baxandall & Swallow (B&S) configuration are
proposed and simulated results presented.
Keywords: Analogue Signal Processing, Current Sources, Electrical Impedance Tomography, High Output
Impedance Current Generators
1 Introduction
Electrical Impedance Tomography (EIT) [1] is used to
generate images of the internal structure of sections of
the body and has advantages in terms of cost, speed
and suitability for continuous patient monitoring over
traditional Magnetic Resonance Imaging (MRI) and
Computerized Tomography (CT) techniques.
In an EIT system a known current is typically
applied and a voltage or set of voltages measured from
which an image can be reconstructed. However,
currents are applied through electrodes whose skin
contact impedance can vary widely and rapidly. Thus,
the current source should exhibit output impedance
much greater than that of its load impedance in order
to ensure the current field is stable during
measurements and hence minimize errors in the
reconstructed image. The design of such a current
source is described in the following sections.
+VCC
I0
I2
Q1
VBE1

I 
(1-α P )  I 2 - 0 
β
n

VEB2
Q2
VE
I1
2 DC Operation
Fig. 1 illustrates a basic Baxandall and Swallow
(B&S) current source [2] and, for an initial evaluation
of circuit operation, I1 and I2 are assumed to be
supplied by ideal current generators.
To find I0 we equate the current flowing out of the
dotted line to the current flowing in. The current
leaving the base of Q2 is, by inspection,
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-VEE
Fig. 1: The B&S configuration [2]
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Proceedings of the 13th WSEAS International Conference on CIRCUITS

I 
(1-α p )  I 2 - 0 
 βn 
i0
(i0-iµ)
Thus for the practical case β n (β p + 1) >>1, I0 can be
ix
given as:
I0 =I1 -α p I2
v
iµ = 0
rµ
r
(1)
β ni x
rπ
(2)
ron
(i0-iµ)
v0
I0 is not significantly dependent on the current gain of
Q1 because the base current that is lost from Q1 is recycled through Q2. Equation (2) is valid providing the
collector-base junction of Q2 is reverse –biased in
order to operate in the active region.
i.e. if
VE (= VEB2 − VBE1 ) < 0 .
αp(ix+iµ)
R
Fig. 2: A simplified low frequency equivalent of Fig 1
The applicability of this circuit is tested by comparing

the value for Ro  =
3 Temperature Performance

The ‘feedback’ action of Q2 ensures that temperature
coefficient of the output current stays both fixed and
at low levels. The temperature coefficient of the
output current I0 can be calculated by differentiating
(2) while maintaining constant values of I1 and I2, :
dα p
dI0
= −I2
dT
dT
v0 
 obtained for it by hand
i0 
calculations with the value obtained from simulation
measurements.
The analysis of Fig 2 although straight-forward it is
rather tedious. The result and variations in the way it
can be expressed are as follows [1,3]
(3)
 i 
rπ
1
1 1
1 
= g0  = 0  =
 +
+
R0
v
(
β
+
1)
r
β
r
β
r

0 
P
n on 
n on R

 µ
(4)
Assuming β p >50 and has a temperature coefficient
less than 10000 ppm per 0C [3] and k/q=86µV/ 0C and
we find that for the range 100>T(oC)>-40 the
temperature coefficient of I0 is some -7 ppm /0C.[1]
Expressed is terms of the common-base output
resistance rob, of Q1 and its common-base input
resistance rib,
r
1
1
=
+ ib
R 0 (βp + 1)rob ron R
4 Incremental Output Resistance using
Ideal Current Bias
The expression for the output resistance, R0, is useful
in clarifying the operation of the circuit. However,
from a design point of view before moving into a
more accurate relationship that shows the dependence
of R0 on BJT parameters a simplified small-signal
low-frequency equivalent circuit in which R=rop//RE is
shown in Fig 2: the common-base parameters rep, rbp,
rop, αp refer to Q2, RE is the incremental output
resistance of the current source I1. The remaining
parameters are for the hybrid-π equivalent circuit of
Q1.
The justification for the simplification is the
magnitude of rµ in relation to rbp, rep, rbn.
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(5)
Where rib ≈
βp VAP
rπ
. For the case R E = ∞ , R = rop ≈
.
βn
I2
Since ron =
VAN
V
and rib = T it follows that
I0
I0
rib
1  VT  I 2 
=



ron R βp  VAN   VAP 
(6)
For I1=1.1mA and I2=0.1mA, corresponding to
I0=1mA, the simulated values of βp,βn are 53.11 and
46 respectively. Output resistance R0 is 196,960MΩ
The simulation result is 201.167 MΩ as shown in
Fig 3. The agreement between the calculated and the
simulated results is very close. All that need to be
noted at this stage is that above 10KHz and until
several hundred MHz, there is a 20dB/decade fall off
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Proceedings of the 13th WSEAS International Conference on CIRCUITS
300M
Ζ0
201.167M
200M
100M
0
1.0Hz
10Hz
V2(Vc1) / I(Vc1)
100Hz
1.0KHz
10KHz
100KHz
1.0MHz
10MHz
100MHz
1.0GHz
10GHz
Frequency
Fig. 3: Showing the output the magnitude of the impedance of the basic B&S configuration versus frequency
in Z0 with frequency. To test, further, the operating
theory presented in [4], two cases were considered. A
resistor, labeled RJ is connected between the collector
and base of Q1 and then between the collector and
earth.
According to the theory presented in [4] is true then,
for the first case RJ should appear as (βp+1)RJ in
parallel with 201.167 MΩ. Substituting βp=53.11 we
obtain ZOa =197.5MΩ in almost exact agreement
To obtain a useful design equation we neglect rµ
compared with βn ron . In that case the requirement is,
β n ron (R E //rop ) >> β n (β p + 1)ron rπ
or, since rπ =
(9)
RE, must be therefore the output of some type of
current generator, so two cases were considered. In
the first case I1 , I2 were supplied by the outputs of a
Modified Wilson Current Mirrors (MWCM) as shown
in Fig.4
The second case of practical current biasing (See Fig.
5) involves the use of the 6-pack mirror [6].
The ‘6-pack’ bias arrangement produces (for the case
I1=1.1mA, I2=0.1mA) a value of R0, which is equal to
193.148MΩ (See Fig 6) closer to that obtained with
the ideal current biasing than the MWCM, because of
its higher output impedance. For that reason and
because it was more flexible, in being able to offer
multiple outputs, it was used in subsequent designs.
For ideal current bias R E = ∞ (where RE is the
equivalent output resistance of the current sink), R has
its maximum value, rop .For practical bias R E ≠ ∞ then
the condition that RE has little effect on R0, in terms of
conductance, is given by consideration of equation (4)
. It is necessary that,
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VT
Io
For the (unrealistic) case β p=β n=200 at I0=1mA this
requires ( RE // rop ) >> 1ΜΩ
5 Incremental Output Resistance using
Practical Current Bias
1
rπ
1
1 
 +
 >>
(β p + 1)  rµ β n ron 
β n ron (R E //rop )
βn VT
I0
(R E //rop ) >> (β p + 1)β n
with the value of 197.520MΩ obtained from
simulation [1].
For the second case were resistor RJ is connected
between the collector and ground, the simulation gave
100.542MΩ compared with an expected value of
201.167MΩ//200ΜΩ=100.5ΜΩ
(8)
(7)
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Proceedings of the 13th WSEAS International Conference on CIRCUITS
+VCC
+VCC
Q1
Q2
Q2
Q1
R0
Q3
R0
Q3
Q4
Q4
Q5
Q6
Q5
0.1m
R1
Q6
Q7
Q8
R2
1.1m
Q9
Q10
Q12
Q8
Q7
Q11
Q9
Q1
Q13
Q14
-VEE
-VEE
Fig. 5: The B&S configuration were I1 and I2
Fig. 4: The B&S configuration with I1 and I2
supplied by Modified Wilson Current Mirrors (MWCM)
supplied by 6-pack current mirror
Z0
200M
193.148
M
150M
100M
50M
0
1.0Hz
VC(Q7)
/
10Hz
IC(Q7)
100Hz
1.0KHz
10KHz
100KHz
1.0MHz
10MHz
100MHz
1.0GHz
Frequency
Fig. 6: The magnitude of the impedance with 6-pack current biasing for the case I1=1.1mA, I2=0.1mA
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Proceedings of the 13th WSEAS International Conference on CIRCUITS
emitter junction capacitance of Q1, Cce is the collectoremitter capacitance of Q1, Cµp is the collector-base
capacitance of Q2.
The procedure is as follows. The frequency
dependence of β n,βp can be neglected in determining
the bandwidth of Ζ 0 . This is because the fT for both
5 Incremental Output Characteristics
Up to this point we have only considered the
incremental output resistance, which is the magnitude
Ζ 0 of the incremental output impedance over that
(low) range of frequencies for which Ζ0 is constant,
i.e. when device inner-electrode capacitances have no
noticeable effect. This section examines the reasons
for the fall off in Ζ0  with frequency. The starting
point is again equation (4) for R0, we can write a
similar equation for (1/Z0) by replacing each term
which its equivalent in frequency domain but by
making all these substitutions into equation (4) leads
to a formula for (1/Z0) that is far too complex for
simple physical understanding of circuit operation, so
an alternative approach is adopted, here, based on
theoretical reasoning and an examination, by
simulation, of the effect of increasing, in turn, each of
the capacitances Cµp ,Cce,Cµ . Where, Cµn is the
collector-base capacitance of Q1, Cπn is the base-
Q1 and Q2 is in the region of 4GHz while their β’s are
about 50, so the beta cut-off frequencies are in the
order of 80MHz, well above the bandwidth
( ≈ 10KHz ) of Ζ0 . For the same reason Cπn may be
neglected in the replacement term for rib.
The result of the simulation tests suggests that Z0 is
given by the following approximate equation
1 1
1  jωCµn
1
=
 +
+
Z0 (βP + 1)  rµ βn ron  (βP + 1)
(10)
Ζ 0 in dB
200
150
(b)
100
(c)
50
0
1.0Hz
10Hz
DB(V2(Vc1)/ I(Vc1))
100Hz
1.0KHz
10KHz
100KHz
1.0MHz
10MHz
100MHz
1.0GHz
10GHz
Frequency
Figure 7: Showing Ζ 0 vs f
Curve (a) shows the response with no added capacitances
Curve (b) shows the response with Cj (=1pF) added between the collector and base of Q1
Curve (c) shows the response with CL (=1pF) added between the collector of Q1 and earth
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Since tests have already shown that
The effective capacitance of Cj(e) of Cj from simulation
is
1
≪ jωCµ
rµ
we can simplify equation (10) further and write,
C j(e) =

1
1  1
=
+ jωCµn 

Z0 (βP + 1)  βn ron

The theory regarding Cj reduction is correct if,
C j(e) =
(βP + 1)βn ron
Therefore, Cj(e)=0.018pF and Cj/(β p+1)=0.0184pF, So
the extra capacitance of 1pF has been reduced by a
factor of (BP+1).
Small differences between the two figures are to be
expected because of rounding-up errors in the
measurement of the cut-off frequencies fΒ(a), fΒ(b) .
Curve (c) in Fig. 7 shows the effect of a load
capacitance CL (=1pF) connected between the
collector of Q1 and earth.
1
2πCµ βn ron
If equation (10) is valid any added Cµ should appear,
like gµ, reduced by a factor ( βp + 1) ; Simulation tests
were set up using the configuration of Fig. 1 in order
to test this hypothesis. Consider first the case of
added capacitance, which is best, understood by
reference to Fig. 7 and Table 1.
Curve (a) of Fig. 7 refers to the response of the
configuration to added capacitance.
C(a) + CL ≈
fΒ(a)=26.552
fΒ(b)=16.551
fΒ(c)=0.791
6 Design for High and Very High Ζ0
Equation (4) provides a clue to the design of circuits
having an incremental output impedance exceeding
that possible with the basic B&S configuration. It is
necessary, by some means, to increase the magnitudes
of β n or βP or preferably both.
Fig. 8 shows one method of increasing both β n and β P
while at the same time observing the DC requirements
transistor Q1 of the basic B&S configuration is
replaced by the Darlington connection of Q1|A and Q1B,
but Q2 is replaced by a complimentary Darlington
stage [5], consisting of Q2A and Q2B , because its
output resistance seen at the emitter of Q2B is higher
than that obtained with a normal Darlington stage ,
(that , in turn, is because the Early voltage of an NPN
BJT exceeds that of a PNP).
Table 1
From the value of fβ(a) in table 1
C(a) =
1
2πR 0 fβ(a )
(13)
Curve (b) shows the response with added capacitance
Cj (=1pF) connected between the collector and base of
the output transistor Q1 .
From knowledge of fβ(b) in table 1 ,
C(b) =
1
2πR 0 fβ(b)
(14)
But C(b)= Cj(e)+ C(a)
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1
2πR 0 fβ(c)
The approximation in this equation is valid since
CL>>C(a)
In fact, simulation gave (Ca+CL)=1.0015pF compared
with an expected value of 1.029pF. This shows that
for CL>1pF the external capacitance loading
determines fΒ(χ) .
Bandwidth fΒ (kHz)
Curve (a)
Curve (b)
Curve (c)
CJ
(βp + 1)
(12)
1 + jωCµβn ron 
The bandwidth fB for Ζ 0 is this f B =
 1
1 
−


 fβ(b) fβ(a) 
(11)
Hence,
Z0 =
1
2πR 0
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Proceedings of the 13th WSEAS International Conference on CIRCUITS
Fig.
9
shows
Ζ 0 versus
frequency
for
When the ideal current bias I1 of Fig 8 was replaced
by the ‘6-pack’ current mirror the output impedance
fell dramatically being limited by the output resistance
of the current sink supplying I1.
Accordingly, and purely in the spirit of scientific
enquiry, the circuit of Fig 10, was developed. It
contains four lettered sub-circuits. Two of these, A
and B, are identical versions of the core circuit of Fig
8 but with I1 replaced by a real current mirror. Subcircuits C and D are dual-output current–mirrors
developments of the B&S configuration supplying
currents I 1 , I 2 ( < I 1 ) : D, not shown in full, has a
configuration complementary to that of C. The
incremental resistance, R OC , seen looking into the
output of C at point X is increased by unit B to a level,
R OB , at point Y, that is sufficiently high for unit A to
provide an output resistance, R OA , comparable with
the maximum achievable for the condition R OB = ∞ .
I 2 = 0.1 mA,
With I1 = 1.1 mA,
and
at
a
measurement frequency of 1Hz, simulation results at
an ambient temperature of 27 0 C were:
R OC = 3.7MΩ; R OB = 2.41GΩ; R OA = 201GΩ (Fig
11)
To demonstrate the efficiency of the ‘feedback’
mechanism, a 100MΩ resistor was connected between
the output point Z and the emitter terminal of the PNP
transistor in unit A: the resulting R OA was
this
configuration and it is evident that Ζ0 is significantly
greater than that in the basic B&S configuration.
+VCC
R0
I2
Core
Circuit
Q1A
Q1B
Q2A
Q2B
I1
Fig. 8: The B&S configuration with the NPN -VEE
transistor replaced by a Darlington stage
and the PNP by a complementary Darlington stage
Ζ0
2 8 0 G
2 4 0 G
2 0 0 G
1 6 0 G
1 2 0 G
8 0 G
4 0 G
0
1 . 0 H z
V 2 ( V c 1 ) /
1 0 H z
I ( V c 1 )
1 0 0 H z
1 . 0 K H z
1 0 K H z
1 0 0 K H z
1 . 0 M H z
1 0 M H z
1 0 0 M H z
1 . 0 G H z
1 0 G H z
F r e q u e n c y
Fig. 9: The magnitude of output impedance of Fig. 11 versus frequency at the collector of Q1A
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Proceedings of the 13th WSEAS International Conference on CIRCUITS
+Vcc
PNP CURRENT MIRROR
D
I2
I2
I2
I0
R OA
Z
Y
R OB
A
B
I1
X.
R OC
≅ I1
C
-Vee
Fig. 10: A very high output impedance current sink configuration
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Ζ0
Fig. 11: The magnitude of the output impedance of Fig. 10 versus frequency
reduced but still high, at 126GΩ [1]. All these results
were obtained with transistors (Analog Devices) with
parameters characteristic of a high frequency
(fT ~ 4GHz) complementary process technology.
References
[1] Terzopoulos N., ‘High Output Resistance Current
Drive Circuits for Medical Applications’,
PhD Thesis, Oxford Brookes University, 2006.
[2] P. Baxandall, E. Shallow ’Constant Current
Source with unusually High Internal Resistance
and good temperature stability’, Electronics
Letters Vol. 2 No. 9, 1966, pp351-35.
[3] Gray R. Paul, Hurst J. Paul, Lewis H. Stephen,
Meyer G. Robert, ‘Analysis and Design of
Analog Integrated Circuits’, John Wiley and
Sons, 2001, pp24
[4] N Terzopoulos, K Hayatleh, B Hart, F J Lidgey
’The Collector-Base Resistance of a BJT’,
Published in European Conference on Circuit
Theory and Design, ECCTD’05, Cork, Ireland
[5] US Patent #2762870, G. C. Sziklai, “Push-Pull
Complementary-Type Transistor Amplifier,”
09/11/1956.
[6] N Terzopoulos, K Hayatleh, B Hart, F J Lidgey,’
A very high Output Resistance Current Source’,
Published in Analogue Signal Processing
Conference proceedings (ASP2004), Oxford
Brookes University, Nov 2004
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