Download Institutionen för systemteknik Department of Electrical Engineering Precision Amplifier for Applications in

Institutionen för systemteknik
Department of Electrical Engineering
Examensarbete
Precision Amplifier for Applications in
Electrical Metrology
Examensarbete utfört i Elektroniksystem
vid Tekniska högskolan i Linköping
av
Stefan Johansson
LiTH-ISY-EX--09/4205--SE
Linköping 2009
Department of Electrical Engineering
Linköpings universitet
SE-581 83 Linköping, Sweden
Linköpings tekniska högskola
Linköpings universitet
581 83 Linköping
Precision Amplifier for Applications in
Electrical Metrology
Examensarbete utfört i Elektroniksystem
vid Tekniska högskolan i Linköping
av
Stefan Johansson
LiTH-ISY-EX--09/4205--SE
Handledare:
Valter Tarasso
SP, Sveriges Tekniska Forsknings Institut
Karl-Erik Rydler
SP, Sveriges Tekniska Forsknings Institut
Examinator:
Per Löwenborg
isy, Linköpings universitet
Linköping, 13 February, 2009
Avdelning, Institution
Division, Department
Datum
Date
Division of Electronics Systems
Department of Electrical Engineering
Linköpings universitet
SE-581 83 Linköping, Sweden
Språk
Language
Rapporttyp
Report category
ISBN
Svenska/Swedish
Licentiatavhandling
ISRN
Engelska/English
Examensarbete
C-uppsats
D-uppsats
Övrig rapport
2009-02-13
—
LiTH-ISY-EX--09/4205--SE
Serietitel och serienummer ISSN
Title of series, numbering
—
URL för elektronisk version
http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-16896
Titel
Title
Precisionsförstärkare för tillämpning inom elektrisk metrologi
Precision Amplifier for Applications in
Electrical Metrology
Författare Stefan Johansson
Author
Sammanfattning
Abstract
This master’s thesis addresses two main problems. The first is how to suppress a
common mode voltage that appears for current shunts, and the second how to let
a voltage divider work under an unloaded condition to prevent loading errors and
thereby a decreased measurement accuracy. Both these problems occurs during
calibration of power meters, and verification of current shunts and voltage dividers.
To the first problem three alternative solutions are presented; prototype a proposed instrumentation amplifier circuit, evaluate the commercial available instrumentation amplifier Analog Devices AD8130 or let the voltage measuring device
suppress the common mode voltage. It is up to the researchers at SP to choose a
solution.
To address the second problem, a prototype buffer amplifier is built and verified. Measurements of the buffer amplifier show that it performs very well. At
100 kHz, the amplitude error is less than 20 µV/V, the phase error is less than
20 µrad, and the input Rp is over 10 MΩ. This is performance in line with the
required to make accurate measurements possible at 100 kHz and over that.
Nyckelord
Keywords
Electrical, Metrology, Precision, Buffer, Amplifier, CMRR
Abstract
This master’s thesis addresses two main problems. The first is how to suppress a
common mode voltage that appears for current shunts, and the second how to let
a voltage divider work under an unloaded condition to prevent loading errors and
thereby a decreased measurement accuracy. Both these problems occurs during
calibration of power meters, and verification of current shunts and voltage dividers.
To the first problem three alternative solutions are presented; prototype a proposed instrumentation amplifier circuit, evaluate the commercial available instrumentation amplifier Analog Devices AD8130 or let the voltage measuring device
suppress the common mode voltage. It is up to the researchers at SP to choose a
solution.
To address the second problem, a prototype buffer amplifier is built and verified. Measurements of the buffer amplifier show that it performs very well. At
100 kHz, the amplitude error is less than 20 µV/V, the phase error is less than
20 µrad, and the input Rp is over 10 MΩ. This is performance in line with the
required to make accurate measurements possible at 100 kHz and over that.
Sammanfattning
Denna examensarbetesrapport behandlar två huvudsakliga problem. Det första
är hur en common mode spänning som uppstår i strömshuntar ska undertryckas
och det andra hur spänningsdelare ska förmås att arbeta olastat för att undvika
belastningsfel och därmed minskad mätnoggrannhet. Båda dessa problem uppstår
vid kalibrering av effektmätare och verifiering av spänningdelare och strömshuntar.
Till det förstnämnda problemet föreslås tre alternativa lösningar; tillverka en
prototyp till en anslagen kretslösning, evaluera den kommersiellt tillgängliga instrument förstärkaren Analog Devices AD8130 eller låt det spänningsmätande
instrumentet undertrycka common mode spänningen. Det är upp till forskarna på
SP att välja en lösning.
För att lösa problem nummer två, byggs och verifieras en buffertförstärkarprototyp. Mätningar på den visar ett amplitudfel på mindre än 20 µV/V, ett fasfel
på mindre än 20 µrad, och ett ingångs Rp på över 10 MΩ vid 100 kHz. Detta är
prestanda i linje med kraven för att möjliggöra precisa mätningar vid 100 kHz och
däröver.
v
Acknowledgments
First I would like to thank SP, Technical research institute of Sweden for giving me
the opportunity to write this thesis, especially my supervisors Valter Tarasso and
Karl-Erik Rydler. I would also like to thank many other employees at SP for giving
me support and advices during this work, Ilya Budowsky at National Measurement
Insitute Australia, NMIA, for the correspondence on the buffer amplifier and at
last my examiner at Linköpings universitet Per Löwenborg.
I would also like to thank my near and beloved for their constant support.
vii
Contents
1 Introduction
1.1 Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
3
3
4
2 Background
2.1 Current Shunts . . . . . . . . . . . . .
2.2 Voltage Dividers . . . . . . . . . . . .
2.3 Why Amplifiers? . . . . . . . . . . . .
2.3.1 Calibration of Power Meters . .
2.3.2 Verification of Current Shunts .
2.3.3 Verification of Voltage Dividers
2.4 Performance Goals . . . . . . . . . . .
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5
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5
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6
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3 Theory
3.1 Properties of Amplifiers . . . . . . . . .
3.1.1 Amplifier Model . . . . . . . . .
3.1.2 Input and Output Impedances .
3.1.3 Offset Voltage and Bias Current
3.1.4 Bandwidth . . . . . . . . . . . .
3.1.5 Slew Rate . . . . . . . . . . . . .
3.1.6 THD and SINAD . . . . . . . . .
3.1.7 Differential and Single-Ended . .
3.1.8 Common Mode Voltage . . . . .
3.1.9 Differential Mode Voltage . . . .
3.1.10 Common Mode Rejection Ratio .
3.2 Operational Amplifier . . . . . . . . . .
3.2.1 Operation of Ideal Op-Amps . .
3.2.2 Feedback Circuits with Op-Amps
3.3 Amplifier Circuits . . . . . . . . . . . .
3.3.1 Inverting Amplifier . . . . . . . .
3.3.2 Non-Inverting Amplifier . . . . .
3.3.3 Differential Amplifier . . . . . . .
3.3.4 Instrumentation Amplifier . . . .
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11
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15
15
15
16
17
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18
19
ix
x
Contents
4 Differential Amplifier
4.1 Required Performance, Differential Amplifier . . . . . . . . . .
4.1.1 Common Mode Voltage Suppression . . . . . . . . . . .
4.1.2 Input Impedance . . . . . . . . . . . . . . . . . . . . . .
4.1.3 Slew Rate Calculation . . . . . . . . . . . . . . . . . . .
4.1.4 Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.5 Table of Performance . . . . . . . . . . . . . . . . . . .
4.2 Commercially Available Amplifiers . . . . . . . . . . . . . . . .
4.2.1 AD8221 . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.2 AD8130 . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3 Custom Design . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3.1 Bootstrapped Three Op-Amp Instrumentation Amplifier
4.3.2 Instrumentation Amplifier Using CCCII . . . . . . . . .
4.4 Digitizer in Differential Mode . . . . . . . . . . . . . . . . . . .
4.4.1 Digital Instrumentation Amplifier . . . . . . . . . . . .
4.5 Comparasion Between Different Options . . . . . . . . . . . . .
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21
21
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24
24
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25
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27
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29
29
5 Single-Ended Amplifier
5.1 Required Performance, Single-Ended Amplifier
5.1.1 Input Impedance . . . . . . . . . . . . .
5.1.2 Table of Performance . . . . . . . . . .
5.2 Commercially Available Buffer Amplifiers . . .
5.3 Custom Design . . . . . . . . . . . . . . . . . .
5.3.1 Simulation Results . . . . . . . . . . . .
5.4 Comparasion Between Different Options . . . .
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31
31
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36
6 Design of Buffer Amplifier
6.1 Component Selection . . . . . .
6.1.1 Op-amp Used in Version
6.1.2 Remaining Components
6.2 Power Supply Circuit . . . . . .
6.3 PCB Design . . . . . . . . . . .
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37
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. .
1.0
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7 Verification of Buffer Amplifier
7.1 Amplitude and Phase Measurement System . . . .
7.1.1 Alternative Phase Error Calculation . . . .
7.1.2 Alternative Amplitude Error Measurement
7.2 Input Impedance Measurements . . . . . . . . . . .
7.3 Measurement Results Version 1.0 . . . . . . . . . .
7.3.1 Conclusions . . . . . . . . . . . . . . . . . .
7.4 New Op-Amps, Buffer Amplifier 1.1 . . . . . . . .
7.4.1 Simulation Results . . . . . . . . . . . . . .
7.5 Measurement Results Version 1.1 . . . . . . . . . .
7.5.1 Amplitude and Phase . . . . . . . . . . . .
7.5.2 Input Impedance . . . . . . . . . . . . . . .
7.5.3 THD and SINAD . . . . . . . . . . . . . . .
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Contents
7.5.4
7.5.5
7.5.6
7.5.7
xi
Power Supply Voltage Dependency
Ambient Temperature Dependency
Warm-Up Time . . . . . . . . . . .
Conclusions . . . . . . . . . . . . .
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50
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8 Discussion and Conclusions
8.1 Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.2 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
57
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Bibliography
59
A Schematics
63
B Plots
67
List of Figures
2.1
2.2
2.5
2.6
Present configuration for calibration of power meters at SP. . . . .
Calibration of power meter using a digitizer. The two marked nodes
will have the same potential. . . . . . . . . . . . . . . . . . . . . .
Calibration of power meter using a digitizer and amplifiers. . . . .
Verification of current shunts. The two marked nodes will have the
same potential. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Verification of current shunts with differential amplifiers. . . . . . .
Verification of voltage dividers with buffer amplifiers. . . . . . . . .
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
Amplifier model, [15]. . . . . . . . . . . . .
Definition of bandwidth, [15]. . . . . . . . .
Differential amplifier. . . . . . . . . . . . . .
Operational amplifier symbol. . . . . . . . .
Inverting amplifier. . . . . . . . . . . . . . .
Non-inverting amplifier. . . . . . . . . . . .
Differential amplifier with a single op-amp.
Three op-amp instrumentation amplifier . .
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11
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19
20
4.1
4.2
4.3
4.4
Model used when calculating input impedance. . . . . . . .
Compensation stage of the instrumentation amplifier. . . .
IA with three CCCIIs. . . . . . . . . . . . . . . . . . . . . .
Specified CMRR for the PXI-5922 in differential mode, [9].
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22
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29
5.1
5.2
5.3
5.4
5.5
Input impedance model. . . . . . . . .
Sketch of the buffer amplifier. . . . . .
Input stage of the buffer amplifier. . .
Vector diagram of correction principle.
Output stage of buffer amplifier. . . .
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32
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36
6.1
6.2
Power supply of the buffer amplifier prototype. . . . . . . . . . . .
PCB layout of the buffer amplifier prototype. . . . . . . . . . . . .
38
39
2.3
2.4
7.1
7.2
7.3
7.4
7.5
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The assembled buffer amplifier prototype. . . . . . . . . . . . . . .
Principle of frequency sweep in Signal Express. . . . . . . . . . . .
Amplitude and phase error measuring setup with digitizer. . . . . .
Amplitude error of the buffer amplifier in version 1.0. . . . . . . .
Amplitude error of the buffer amplifier in version 1.0 measured with
AC-DC transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.6 Phase error of the buffer amplifier in version 1.0. . . . . . . . . . .
7.7 The upper line shows the phase error of the buffer amplifier in version 1.0 - from RMS. . . . . . . . . . . . . . . . . . . . . . . . . . .
7.8 Input impedance of buffer amplifier version 1.0. . . . . . . . . . . .
7.9 Amplitude and phase error average of the buffer amplifier in version
1.1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.10 Standard deviation of three amplitude and phase error measurements.
6
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7
8
8
9
41
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43
45
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46
47
49
50
2
Contents
7.11
7.12
7.13
7.14
7.15
7.16
7.17
Input Rp of the buffer amplifier in version 1.1. . . . . . . . . . . .
Input Cp of the buffer amplifier in version 1.1. . . . . . . . . . . . .
SINAD and THD of the buffer amplifier in version 1.1. . . . . . . .
Standard deviation with three different power supply voltages. . .
Ambient temperature dependency test setup. . . . . . . . . . . . .
Difference in amplitude and phase error from 23 to 15 and 25 ℃. .
Amplitude and phase error the first 10 min after startup at 113 kHz.
51
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52
53
54
54
55
A.1 Three op-amp instrumentation amplifier with compensation. . . . .
A.2 IA with three CCCII. . . . . . . . . . . . . . . . . . . . . . . . . .
A.3 Buffer amplifier version 1.1. . . . . . . . . . . . . . . . . . . . . . .
64
65
66
B.1
B.2
B.3
B.4
B.5
B.6
B.7
B.8
68
69
70
71
71
72
72
73
CMRR of three op-amp IA with compensation. . . . . . . . . . .
Amplitude and Phase of buffer amplifier with AD817. . . . . . .
Input Rp of buffer amplifier version 1.0. . . . . . . . . . . . . . .
Amplitude and phase error measurement with disturbances. . . .
Spectrum of the measurement environment. . . . . . . . . . . . .
Amplitude and phase error buffer amplifier version 1.1. . . . . . .
Difference in amplitude and phase error from 23 to 20 and 30 ℃.
DC-offset change the first 15 min after startup. . . . . . . . . . .
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List of Tables
2.1
Performance goals at 100 kHz for current shunts with 5 A input and
0.8 V voltage drop. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Performance goals at 100 kHz for voltage dividers with 240 V input
and 0.8 V output. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9
4.1
4.2
Required performance of the differential amplifier at 100 kHz. . . .
Measured CMRR of PXI-5922 in differential mode. . . . . . . . . .
24
28
5.1
Required performance of the single ended amplifier at 100 kHz. . .
32
7.1
Input resistance, Rp , in MΩ of the buffer amplifier in version 1.1
measured by AC-DC transfer standards. . . . . . . . . . . . . . . .
50
2.2
9
Chapter 1
Introduction
This final year master’s thesis in Applied Physics and Electrical Engineering was
carried out at SP, Technical Research Institute of Sweden.
1.1
Structure
After this introduction the background and theory chapters will give the reader a
foundation needed to understand the contents of this thesis. Some of the expressions used in the background chapter are not explained until the theory chapter,
so for some readers it might be a good idea to start with the latter. After this,
the two problems occupy one chapter each and the design of a prototype and verification of it occupies the two last chapters before the discussion and conclusions
chapter.
References to sections, tables and figures within this report are written as
plain numbers. The first digit represents the number of the chapter (or letter
if appendix) and the second is a serial digit. Equations are referred to within
common brackets ( ) and references to printed books, articles or websites that
were used during research are written within square brackets [ ].
Large schematics and plots have been moved to appendix to not disturb the
outline of this report.
1.2
Method
The first step in this project was to translate the accuracy of the measurement
parameters stated in Section 2.4 into properties of amplifiers. After that the
market was scanned for amplifiers meeting the requirements. Some examples of
amplifiers with performance at least somewhat close to the desired are described
in Section 4.2 and Section 5.2. When no amplifier with good enough performance
was found development of new designs were started.
3
4
1.3
Introduction
Resources
The main sources for this work have been scientific articles. Most of them have
been PDF-files downloaded from databases e.g. IEEE Xplore. Documentation of
existing amplifiers and components used in the design have been downloaded from
web pages of hardware manufacturers. PSPICE models for components have also
been downloaded from manufacturers web pages. There are a lot of books and
articles on the topic of interest but since the performance needed is extraordinary,
the amount of interesting literature is reduced substantially.
The simulation tool PSPICE and circuit layout application OrCAD Capture
was widely used to evaluate performance of different amplifier topologies and
monolithic integrated amplifiers. Later on when it was decided to build a prototype EDWin XP, was used to layout the printed circuit board (PCB). EDWin
XP is a very powerful tool but has a quite complicated user interface. To measure
the performance of the built prototype available measurement apparatus at SP
was used and all data processing was performed in MathWorks MATLAB.
Chapter 2
Background
The Technical Research Institute of Sweden, SP, section of electrical measurements, manufactures and sells current shunts and voltage dividers designed for
accurate measurements in the power frequency range. Today the current shunts
and voltage dividers are specified from DC up to a few kHz but there is a demand
to specify them for higher frequencies. Limitations in the measurement system
used at SP makes verification for higher frequencies impossible and as a step in
the development of the measurement system there is a need for precision amplifiers.
2.1
Current Shunts
A current shunt is basically a resistor in which a certain current flows that corresponds to a specified voltage drop. This is a way to convert a current into a voltage
which is easier to measure. The current shunts developed at SP consist of several
high quality resistors mounted in a way that minimizes the effect of parasitics, the
design is described in [19].
2.2
Voltage Dividers
Voltage dividers are used at SP to convert a high voltage to a lower one. It
implements a common resistive voltage divider with several series resistors to share
the power dissipation and a few features to improve the performance. Capacitive
compensation of the phase angle due to capacitive loading of the output, together
with a capacitive guard divider to minimize the effect of stray capacitances are
examples of this. More information about the voltage dividers can be found in
[18].
2.3
Why Amplifiers?
To be able to verify current shunts and voltage dividers, and calibrate power
meters up to 100 kHz with high accuracy, equipment with very good performance
5
6
Background
is needed. In the following sections the problems that occur for high frequency
signals are described and possible solutions are briefly introduced.
2.3.1
Calibration of Power Meters
The configuration in Figure 2.1 is the present configuration used for calibration of
power meters at SP. This system is described in more detail in [23]. DVM is an
abbreviation for Digital Volt Meter.
Figure 2.1. Present configuration for calibration of power meters at SP.
This configuration is limited to 20 kHz due to the sample frequency of the
DVMs. Another voltmeter is needed and for this purpose a two channel digitizer
that can measure voltage up to 250 kHz with 24 bits resolution is available, see
specifications in [7]. The new measurement configuration can be seen in Figure
2.2.
The problem with this configuration is that the two low terminals of the two
channel digitizer are internally connected – the high terminal of the current part
of the power meter and the low terminal of the voltage input will have the same
potential. If the voltage source and current source are grounded, the current shunt
is short-circuited. In other words, the two inputs of the digitizer must be separated.
One way to do this is to use an instrumentation amplifier, see Section 3.3.4, and
input the differential voltage to the high input of the digitizer, as viewed in Figure
2.3. To propose solutions to this problem is the first topic of this thesis.
The second topic of this thesis is how to make the voltage divider work under an
unloaded condition. The relatively high output impedance of the voltage divider
means that a very high input impedance load is needed to prevent loading errors
making accurate measurements possible.
2.3 Why Amplifiers?
7
Figure 2.2. Calibration of power meter using a digitizer. The two marked nodes will
have the same potential.
Figure 2.3. Calibration of power meter using a digitizer and amplifiers.
2.3.2
Verification of Current Shunts
A similar problem as described in Section 2.3.1 occurs when the amplitude and
phase of current shunts is to be verified. Two shunts must lead the same current
and are therefore connected in series. The upper of the two has known phaseand amplitude characteristics and acts as a reference while the lower is verified,
8
Background
see Figure 2.4. When the digitizer is used, instead of two DVMs, to measure the
voltage over the two current shunts, the potential on the low side of the current
shunts will be the same, making the verification impossible.
Figure 2.4. Verification of current shunts. The two marked nodes will have the same
potential.
To solve the problem an instrumentation amplifier can be used to input the
differential voltage to the digitizer and suppress the common mode voltage that
appears for the upper shunt. Figure 2.5 shows how this can be done.
Figure 2.5. Verification of current shunts with differential amplifiers.
2.3.3
Verification of Voltage Dividers
To verify the phase- and amplitude characteristics of voltage dividers, two voltage
dividers are connected in parallel. This configuration will not give any problems
with a common mode voltage since the voltage dividers share the reference point.
The issue in this case is instead to let the voltage divider work under an unloaded
condition and thereby prevent loading errors. This is achieved by adding a high
input impedance amplifier between the current shunt and digitizer, see Figure 2.6.
2.4 Performance Goals
9
Figure 2.6. Verification of voltage dividers with buffer amplifiers.
2.4
Performance Goals
The goal is to design or find amplifiers making verification with an accuracy according to Tables 2.1 and 2.2 possible at 100 kHz.
Table 2.1. Performance goals at 100 kHz for current shunts with 5 A input and 0.8 V
voltage drop.
Amplitude
Phase
≤ 10 µV/V
≤ 100 µrad
Table 2.2. Performance goals at 100 kHz for voltage dividers with 240 V input and
0.8 V output.
Amplitude
Phase
≤ 20 µV/V
≤ 200 µrad
Chapter 3
Theory
This chapter will give the reader a good foundation of theory needed to understand
the contents of this thesis. The reader is assumed to have basic knowledge in
electrical science.
3.1
Properties of Amplifiers
There are some important amplifier properties and relations that must be well
known by the reader. This section will present some of the most important properties for this work.
3.1.1
Amplifier Model
A simple but still very useful model of an amplifier is shown in Figure 3.1. It
is characterised by the input impedance, Rin , voltage amplification, Av , and the
output impedance, Rut . If a load resistance, RL , is connected in parallel with the
output, the transfer function of the amplifier can be derived using voltage division,
see Equation (3.1), [15].
Figure 3.1. Amplifier model, [15].
11
12
Theory
Uout
RL
= Av ·
Uin
RL + Rout
3.1.2
⇒
Uout
Rin
RL
=
· Av ·
Ug
Rin + Rg
RL + Rout
(3.1)
Input and Output Impedances
When a load is connected to an amplifier the output impedance becomes important. The amplifier must be able to provide enough current without a change in
output voltage. The maximum output current is of course limited in all amplifiers.
The output impedance of the amplifier in Figure 3.1 is equal to Rout .
To prevent loading errors the input, impedance must be sufficiently high. This
is especially important in measurement technology to get accurate measurements.
For the amplifier model in Figure 3.1 the input impedance is easily calculated.
Ohm’s law directly gives Equation (3.2).
Uin
(3.2)
Iin
The input impedance of an amplifier can be modelled as a resitor, Rp , in parallel
with a capacitor, Cp . Due to the simple model Rp is often frequency dependent,
Rp (f ). Equation (3.4) and (3.5) show how Rp (f ) and Cp are calculated when Uin
and Iin are measured. See [16] for the equations in (3.3).

1
Z = Y = G + jB 






Uin

Zin = Iin

⇒
(3.3)


G = R1p







B = 2πf Cp
Zin =
1
1
1
1
=
=
=
G
Re(Y )
Re( Z1 )
Re( UIin
)
in
(3.4)
Im( UIin
)
Im( Z1 )
B
Im(Y )
in
=
=
=
2πf
2πf
2πf
2πf
(3.5)
Rp (f ) =
Cp =
3.1.3
Offset Voltage and Bias Current
When an amplifier is fed with zero volts, the output should ideally be zero volts.
Due to imbalances in the input stage, the output voltage can be slightly shifted
from zero. The voltage that must be applied to give zero volts at the output is
called offset voltage.
The ideal operational amplifier, see Section 3.2.1, has no input currents, but
there are in reality small input currents, called input bias currents, that must be
there to drive the amplifier. To minimize the effect of the input bias currents the
input DC resistance should be kept the same for both inputs of the amplifier, [15].
3.1 Properties of Amplifiers
3.1.4
13
Bandwidth
The bandwidth of an amplifier is usually defined as the frequency where the output
voltage has dropped with a factor √12 , which corresponds to a drop of 3 dB, see
Figure 3.2. This definition is inappropriate for an amplifier with high performance
and accuracy but gives a good hint of the performance when comparing different
amplifiers, [15].
Figure 3.2. Definition of bandwidth, [15].
3.1.5
Slew Rate
Slew rate describes how fast an amplifier is. In other words, how big voltage swing
it can provide under a certain time. When working with high frequencies and large
voltage swings an amplifier with high slew rate is a must, [15].
dU (t) slew rate = (3.6)
dt max
3.1.6
THD and SINAD
THD is an abbreviation for Total Harmonic Distortion and can be defined in
several different ways. Here it is defined as a percentage of how large the power
of the harmonics is relative the power of the fundamental frequency, see Equation
(3.7).
n
X
THD =
Pi
i=2
P1
(3.7)
Signal-to-noise-and-distortion ratio, SINAD, is the ratio of the root-meansquare (RMS) value of the fundamental frequency to the mean value of the rootsum-square (RSS) of all other spectral components excluding DC, and is given
in dB. SINAD is a good metrics of the dynamic performance of an amplifier just
because it includes both noise and harmonics. Equation (3.8) defines SINAD.
14
Theory
Under the same circumstances SINAD is equal to THD + N (Total Harmonic
Distortion + Noise), with the difference that THD + N often is given as a percentage, [10].
SINAD = 20 log
3.1.7
Psignal
Pnoise + Pdistortion
(3.8)
Differential and Single-Ended
The amplifier in Figure 3.1 is a single-ended amplifier. An amplifier with two inputs
is called differential amplifier. It amplifies the difference between the two input
signals, see Figure 3.3. A differential amplifier can have either one or two outputs,
if there are two outputs the amplifier is called fully differential. Amplifiers with a
differential input and a single-ended output are more common and very useful in
many applications. The output voltage of such an amplifier can, for the ideal case,
be expressed as in Equation (3.9). Where Av denotes the voltage amplification
and U1 and U2 the two voltage inputs, [15].
Figure 3.3. Differential amplifier.
Uout = Av · (U1 − U2 )
3.1.8
(3.9)
Common Mode Voltage
The part of the input voltage that is the same of the two inputs of an differential
amplifier is called common mode voltage (UCM ) and is equal to the mean of the
inputs, see Equation (3.1.8), [15].
UCM =
3.1.9
U1 + U2
2
(3.10)
Differential Mode Voltage
The difference between the input signals is called differential mode voltage (UDM ),
see Equation (3.1.9), [15].
UDM = U1 − U2
(3.11)
3.2 Operational Amplifier
3.1.10
15
Common Mode Rejection Ratio
As expressed earlier, an ideal differential amplifier only amplifies the differential
voltage. But since an amplifier with zero common mode amplification does not
exist, Equation (3.9) must be rewritten to Equation (3.12). Here AvDM is the
differential mode gain and AvCM is the common mode gain.
Uout = AvDM · UDM + AvCM · UCM
(3.12)
The ability of a differential amplifier to reject common mode voltages is called
common mode rejection ratio, CMRR, and is defined by Equation (3.13).
CM RR =
AvDM
AvCM
(3.13)
CMRR is usually given in dB according to Equation (3.14).
AvDM
CM RRdB = 20 log
AvCM
(3.14)
The common mode gain of a differential amplifier is normally an unknown
parameter, this calls for a rewriting of Equation (3.14). When a common mode
signal is applied to the differential amplifier the second part of Equation (3.12) is
zero which gives Equation (3.15). Combining that and Equation (3.14) yields an
easier way to calculate and measure CMRR, see Equation (3.16), [6].
Uout = AvCM · UCM
CM RRdB = 20 log
3.2
⇒
AvCM =
AvDM · UCM
Uout
Uout
UCM
(3.15)
(3.16)
Operational Amplifier
The operational amplifier (op-amp) is a common and very important building
block in analogue electronics. It was introduced in the end of 1940’s, in other
words about the same time as the transistor. The first op-amps were built from
electron tubes. A monolithic integrated circuit op-amp using transistors was first
designed by Bob Widlar at Fairchild semiconductors 1964. In the following years
he designed many well known op-amps, one of them, the µA741 might be one of
the most used op-amps ever, [13].
3.2.1
Operation of Ideal Op-Amps
The symbol of an op-amp is shown in Figure 3.4. It consists of a differential input
pair, one inverting and one non-inverting input, and a single-ended output. Vcc
and Vee is the positive and negative power supply connections respectively. The
ideal op-amp have infinite input impedance, no offset voltage and zero output
impedance. The bandwidth of the ideal op-amp is infinite and so is the open-loop
16
Theory
Figure 3.4. Operational amplifier symbol.
gain. The ideal op-amp is far from reality, but it makes calculations of op-amp
circuits easy and is often a sufficient model. The behaviour of an ideal op-amp is
described by Equations (3.17) and (3.18).
Uout = Vcc
for
Uin+ > Uin−
(3.17)
Uout = Vee
for
Uin+ < Uin−
(3.18)
This behaviour makes the op-amp very suitable for comparator circuits, but might
seem to be a strange behaviour of an amplifier. To get a proper amplifier function
from an op-amp there is a need of feedback. The feedback circuit forces the op-amp
to work in the active area between the two extreme values Vcc and Vee , [6].
3.2.2
Feedback Circuits with Op-Amps
Op-amps are almost always used in feedback circuits. The principle is that a
part of the output signal is coupled back to the input to cancel parts of it. This
makes it possible to get a predictable gain of op-amp circuits. Feedback has many
other benefits as well, for example increased linearity, which also leads to reduced
distortion, [6]. Equation (3.19) shows the transfer function of a feedback circuit.
Where Avo denotes the open loop gain of the amplifier and β the feedback factor.
Avo
Uout
=
Uin
1 + βAvo
(3.19)
When Avo is large, or infinite, as for the ideal op-amp Equation (3.19) gives Equation (3.20).
Uout
Avo
1
= lim
=
Avo →∞ 1 + βAvo
Uin
β
(3.20)
This means that the total gain of the amplifier circuit is independent of the amplifier gain, as long as the open loop gain is high enough to satisfy Equation (3.20).
The β network is usually resistors and or capacitors.
When analysing feedback circuits with op-amps, two rules are applied. Since
the input impedance is infinite, there will be no current flowing into the op-amp,
and due to zero offset voltage and infinite gain there will not be any voltage
3.3 Amplifier Circuits
17
difference between the two inputs. This is expressed in Equations (3.21) and
(3.22), [15].
I+ = 0,
I− = 0
U+ = U−
3.3
(3.21)
(3.22)
Amplifier Circuits
In this section a few amplifier circuits with op-amps are presented. Some of the
circuits, or versions of them, are used later in the thesis.
3.3.1
Inverting Amplifier
Consider the circuit in Figure 3.5. It is an op-amp with feedback resistor R2 and
an input resistor R1 . This is a common inverting amplifier.
Figure 3.5. Inverting amplifier.
If the op-amp is seen as ideal the analysis of the circuit in Figure 3.5 is simple.
Using Equation (3.22) yields that the voltage over R1 is Uin and Uout over R2 .
The current through R1 and R2 is the same, according to Equation (3.21), and
Equation (3.23) can be stated using Ohm’s law to calculate the current thrugh the
two resistors.
Uin
Uout
=−
R1
R2
⇒
Uout
R2
=−
Uin
R1
(3.23)
The input impedance of the inverting amplifier is equal to R1 since the noninverting input of the op-amp is at zero volts. This makes it impossible to combine
high gain and high input impedance, which is the main disadvantage of the inverting amplifier.
18
3.3.2
Theory
Non-Inverting Amplifier
Figure 3.6 shows a non-inverting amplifier. The transfer function of this topology
can be derived using the same rules as for the inverting amplifier, but the voltage
at the input terminals comes from a voltage division between R2 and R1 , see
Equation (3.24).
Uin =
R1
· Uout
R1 + R2
Uout
R1 + R2
=
Uin
R1
⇒
(3.24)
The non-inverting amplifier has ideally infinite input impedance. In reality it
is equal to the input impedance of the used op-amp.
If R2 is replaced by a short circuit and R1 is removed, an amplifier with unity
gain is created. This special version of the non-inverting amplifier is called voltage
follower or buffer amplifier.
Figure 3.6. Non-inverting amplifier.
3.3.3
Differential Amplifier
Differential amplifiers are, as discussed in Section 3.1.7, used to amplify the difference between two signals. A common differential amplifier using one op-amp
is shown in Figure 3.7. The transfer function of this circuit, Equation (3.25), is
derived below using Equations (3.17), (3.18), Ohm’s law and voltage division.
Uin+ = U1 ·
R2
R1 +R2
Uin+ = Uin−
U2 −Uin−
R1
U2 − U1 ·
R1
R2
R1 +R2
=
=
Uin− −Uout
R2
U1 ·
R2
R1 +R2
R2






⇒





− Uout
⇒
3.3 Amplifier Circuits
19
Figure 3.7. Differential amplifier with a single op-amp.
R2
· (U1 − U2 )
(3.25)
R1
To get a high CMRR there is a need for matching between the two resistors
called R1 and the two called R2 . Even a small deviation between the resistors will
give a large decrease in CMRR. The CMRR of single op-amp differential amplifiers
is carefully analysed in [17] where it is found that with 0.1 % tolerance resistors
and unity gain a typical CMRR for this circuit is only 54 dB.
Uout =
3.3.4
Instrumentation Amplifier
To get higher input impedance (and the same for both inputs) in the single op-amp
differential amplifier, there is a need to implement input buffers. This can be done
by just adding two voltage followers, one at each input. But a more clever solution
is shown in Figure 3.8. The circuit is often called instrumentation amplifier (IA)
because it is often used as a measurement amplifier. An instrumentation amplifier
is characterized by high gain, high input impedance, and relatively high CMRR.
In this circuit the differential gain of the total amplifier can be adjusted with
a single resistor (R1 ). The common mode gain is unity for the first stage, and
suppressed by the last op-amp. This circuit is not as sensitive as the single opamp differential amplifier regarding resistor matching. The transfer function for a
three op-amp is derived below, where I denotes the current through R1 .

1
I = U2R−U


1



⇒
U3 = U1 − R2 I





U4 = U2 + R2 I
U3 − U4 = U1 − U2 − 2R2 I = U1 − U2 − 2R2
R2
= (U1 − U2 ) 1 + 2
R1
U2 − U1
=
R1
(3.26)
20
Theory
Figure 3.8. Three op-amp instrumentation amplifier
Combining the expression for the output voltage of a differential amplifier, Equation (3.25), and the expression for U3 − U4 gives Equation (3.27).
R4
R4
R2
(U3 − U4 ) =
Uout =
1+2
(U1 − U2 )
(3.27)
R3
R3
R1
R4
= 1) in
High differential gain in the first stage together with unity gain ( R
3
the differential stage will give a relatively high CMRR, [6]. Matching between the
two input op-amps is nevertheless critical to achieve a really good CMRR. Also
this circuits CMRR has been analysed in [17] where a CMRR of about 90 dB was
reached for low frequencies.
Chapter 4
Differential Amplifier
This chapter deals with the first problem of this thesis, described in Sections 2.3.1
and 2.3.2, how to suppress the common mode voltage that appears for current
shunts during calibration of power meters and verification of current shunts.
4.1
Required Performance, Differential Amplifier
The first step towards a solution of this problem was to translate the measurement
accuracy goals given in Table 2.1 into properties of a differential amplifier.
4.1.1
Common Mode Voltage Suppression
The common mode voltage that appears for the upper current shunt in Figure 2.4
must be suppressed. This can, as earlier described, be done by a differential amplifier with a single-ended output. To get an amplitude error as small as 10 µV/V
the CMRR must be very high. The common mode voltage, UCM , of the current
shunt is determined in accordance with Equation (3.10),
UCM =
U1 + U2
1.6 + 0.8
=
= 1.2 V
2
2
(4.1)
Desired differential gain, AvDM , is unity and the output voltage
Uout = 0.8V ± 10 µV/V of 0.8 V. The output of a differential amplifier is according
to Equation (3.12),
Uout = 1 · 0.8 + AvCM · 1.2
⇒
21
AvCM ≤
0.8 · 10 · 10−6
1.2
(4.2)
22
Differential Amplifier
This gives a CMRR of,
AvDM
≥
AvCM
1.2
≥ 20 log
≈ 103.5 dB
0.8 · 10 · 10−6
CM RRdB = 20 log
(4.3)
(4.4)
Over 100 dB CMRR at 100 kHz is not easily achieved and will require a lot of
effort.
4.1.2
Input Impedance
There are many versions of current shunts that SP is manufacturing. For example
a 5 A shunt has resistance of 0.16 Ω, which corresponds to a voltage drop of 0.8 V.
The minimum input impedance to get an amplitude error less than 10 µV/V and
phase error less than 100 µrad at 100 kHz is calculated here. Figure 4.1 shows
the model used for calculations, this model was discussed in Section 3.1.2. The
transfer function from I to U is shown in Equation (4.5).
Figure 4.1. Model used when calculating input impedance.
Z=
Rshunt · Rp
U
1
=
·
I
Rshunt + Rp 1 + jω · Rshunt Rp Cp
Rshunt +Rp
(4.5)
Equation (4.6) is an approximation of the magnitude of the transfer function
from I to U. It is a Maclaurin series of the first order of the magnitude of Equation
(4.5). Rs has been factored out since it is the original impedance without an
amplifier. The term after 1 in the parentheses is the loading error caused by the
amplifier.
U 1
Rshunt
R2
2
|Z| = ≈ Rshunt 1 −
2
+ shunt
+
(ωC
R
)
(4.6)
p shunt
I
2
Rp
Rp2
R2
2
is signaficantly larger than shunt
and (ωCp Rshunt ) whereby they can be
2
Rp
neglected and the minimum Rp can be calculated as below.
Rshunt
Rp
µV
Rshunt
≤ 10
Rp
V
⇒
Rp ≥
Rshunt
0.16
=
= 16 kΩ
−6
10 · 10
10 · 10−6
(4.7)
4.1 Required Performance, Differential Amplifier
23
The phase lag of Equation (4.5) is,
Rshunt Rp Cp
⇒
Φ = arctan ω ·
Rshunt + Rp
Cp =
tan Φ(Rshunt + Rp )
ωRshunt Rp
(4.8)
Equation (4.8) gives a maximum Cp of about 1 nF for Rp = 100 kΩ and Φ = 100 µrad.
This shows that the input impedance is not really a problem in this case since
Rp ≥ 16 kΩ and Cp ≤ 1 nF is easily achieved, even for high frequencies.
4.1.3
Slew Rate Calculation
The gain of the amplifier does not need to be high. Since the purpose is to take
the difference between two signals and not really amplify them. This leads to the
use of a unity gain amplifier. The input voltage to the amplifier is not very high
either, what can cause a problem is high frequencies. The slew rate needed is
calculated according to Equation (4.9), which is derived from Equation (3.6) when
a sinusoidal signal is applied.
Slew rate
⇒
Slew rate = 2πfmax Û
(4.9)
2π Û
If fmax is given in MHz, slew rate is in V /µs. To have some margin a voltage swing of URM S =1 V which gives Û ≈ 1.41 V at 100 kHz was used in the
calculation. This leads to a required slew rate of approximately 0.9 V/µs.
Since many high performance op-amps on the market have a significantly higher
slew rate than needed this will not be a big problem. However, the extreme
requirements of linearity in phase and amplitude will lead to the requirement of a
fast amplifier.
fmax =
4.1.4
Bandwidth
The requirement of constant phase up to 100 kHz calls for a very high bandwidth of
the amplifier. If no compensation is added and a first order (6 dB/octave) transfer
function, A, is assumed, an amplifier with -3 dB point at 1 GHz is required. See
the calculations below.
A=
1
1 + j ωω1
⇒
|A| = r
1
2
1 + ωω1
Equation (4.10) shows the phase lag of A.
ω
ΦA = arctan
≤ 100 µrad at 100 kHz ⇒
ω1
2π100 kHz
ω1 =
≈ 1 GHz
tan(100 µrad)
(4.10)
(4.11)
24
Differential Amplifier
Standard voltage feedback op-amps usually have a -3 dB bandwidth of about 1
MHz. There are amplifiers with much higher bandwidth, but to find one with as
high bandwidth as 1 GHz is not possible. Some kind of compensation network must
be implemented to keep the phase and amplitude more constant with frequency.
4.1.5
Table of Performance
Performance parameters of a differential amplifier that makes verification of current shunts and calibration of power meters according to Table 2.1 possible are
listed in Table 4.1.
Table 4.1. Required performance of the differential amplifier at 100 kHz.
Parameter
CMRR
Amplitude error
Phase error
Slew Rate
Rp
Gain
4.2
Value
≥ 103.5 dB
≤ 10 µV/V
≤ 100 µrad
≥ 0.9 V/µs
≥ 16 kΩ
Unity
Commercially Available Amplifiers
The next step of this project was to scan the market for existing amplifiers that
fulfilled the requirements. It was found to be a hard task. Below are some examples
of amplifiers which performances have been tested in simulation using PSPICE.
4.2.1
AD8221
Analog Devices AD8221 is a high performance instrumentation amplifier which
gain is set by an external resistor. The CMRR for this amplifier is high, over 110
dB, but only for quite low frequencies, and starts to fall at about 1 kHz. At 100
kHz the CMRR has fallen to about 75 dB. The phase start to fall at about 1 kHz
and deviates several degreases from zero at 100 kHz and should in other words
need a lot of compensation to fit in the thought application.
This amplifier is too far from the requirements to motivate further investigation.
4.2.2
AD8130
Analog Devices AD8130 is a differential receiver amplifier generally used as a high
speed differential line driver, but is also used as a high speed instrumentation
amplifier. The AD8130 is typically specified, [5], to have a CMRR of 100 dB at
least up to 300 kHz but when the minimum specification is considered the value
4.3 Custom Design
25
falls to 88 dB. The simulation model, which according to Analog Devices models
the minimum performance, shows a CMRR that stays at about 94 dB up to 10
kHz where it starts to fall. The bandwidth of this amplifier is very good, it has
-3 dB bandwidth of 250 MHz minimum, [5]. The phase response is, according
to simulation, very linear and deviates 1.99 mrad at 100 kHz. But this value is
not good enough for this application and some kind of compensation is required,
described in Section 4.3.1. Not in the same range as for the AD8221 though.
AD8130 has very good performance and no real competitors have been found
from other manufacturers. If the CMRR is somewhat better then the minimum
specification and the phase is compensated, this amplifier would be a simple and
cheap solution to the common mode problem.
Further investigation of this amplifier is motivated.
4.3
Custom Design
Since no amplifier was found on the market that could assure performance that
would fulfil the specifications in Table 2.1 development of a new design was started
to see how far such would reach.
4.3.1
Bootstrapped Three Op-Amp Instrumentation Amplifier
The CMRR of a regular three op-amp instrumentation amplifier is not good enough
for this application, see Sections 2.4 and 3.3.4. However, this is a good circuit
to start with but some modifications are required. Many different circuits were
considered during the development work and the best alternative is presented in
[6], see Figure A.1. It is a standard three op-amp instrumentation amplifier where
the two input op-amps have bootstrapped power supplies. The common mode
voltage is buffered by a fourth op-amp and fed to a small floating split supply
to the two input op-amps. This circuit removes the input common mode signal
from the input op-amps because they do not see any voltage swing due to common
mode signals at their input relative their power supply. The CMRR of this circuit
was simulated to as much as 130 dB at 100 kHz and considerably higher for low
frequencies, see Figure B.1. But this is with ideal resistors without any matching
errors and no parasitic capacitances that will appear when a printed circuit board
is designed. The choice of op-amp is critical in this circuit. It must have high
speed, high bandwidth, and high CMRR to reach the required performance. The
two input op-amps must also be well matched to not degrade the CMRR. MAX477,
[14], by Maxim is well suited for this task. It is a voltage feedback op-amp with
very high bandwidth and low gain and phase errors.
The amplitude and phase response of this circuit was not good enough from
the beginning and some kind of compensation was required. An op-amp with a
capacitor in the feedback network was added after the instrumentation amplifier
to bend the phase back towards zero and the gain towards one. The value of this
capacitor was tried out with repeated simulations. The compensation part of the
26
Differential Amplifier
amplifier can be seen in Figure 4.2. This is a non-inverting amplifier with an added
Figure 4.2. Compensation stage of the instrumentation amplifier.
capacitor. There are also two resistors in parallel at the non-inverting for both
inputs to have the same DC input resistance. This reduces the effect of the input
bias currents, see Section 3.1.3 for more details. The ideal transfer function of this
circuit is derived below.
1
R29 // jωC
Uout
R29 + R28 + jωC9 R29 R28
9
=
=
Uin
R29 + R28
R29
(4.12)
When there is a big difference between R29 and R28 , equations for the ideal opamp does no longer apply and it is possible to achieve a gain lower than unity for
the non-inverting amplifier. The amplifier stage in Figure 4.2 has a gain of 0.99990
to compensate the gain of 1.0001 in the instrumentation amplifier. There are no
reasons to trim the resistance values further in simulation since more trimming is
a must when the circuit is built anyway, due to resistor matching and parasitics.
As mentioned above, the performance of the three op-amp instrumentation
amplifier with bootstrapping is good in simulation with ideal components. The
simulated CMRR can be seen in Figure B.1 and satisfies to the requirement. The
amplitude and phase response also stays within the requirement but not with a
very large margin. The phase deviates 95 µrad from zero and the amplitude shows
an error of 8 µV/V at 100 kHz.
The biggest problem with this circuit is that it is very sensitive to unbalanced
parasitic capacitances at the input of the differential stage, as little as 0.1 pF
degrades the CMRR with as much as 57 dB. Matching of the resistors in the
differential stage must also be kept at µV/V level to reach the goals. The influence
of parasitics can be lowered by keeping the resistance values low giving a smaller
4.3 Custom Design
27
RC product and thus higher pole frequency. But too low resistance values tend
to lower the overall CMRR, the reason for this has not been found.
The reasons mentioned above are what make this amplifier hard to implement,
but an experienced engineer has overlooked the design and thinks that it is possible
to keep the parasitics low enough to meet the performance requirements. Careful
symmetric PCB layout and precise component matching is a must.
4.3.2
Instrumentation Amplifier Using CCCII
CCCII is short for the second generation of current controlled conveyors. A current
conveyor is a analogue building block with very high bandwidth since it is not
limited by feedback as op-amps, [24]. The transfer function of CCCIIs is shown
below, [12].
 
iy
0
 Vx  =  1
iz
0

0
Rx
p


0
Vy
0   ix 
1
Vz
(4.13)
CCCIIs are available in two versions, one with a Z+ output and one with a
Z- output, p in Equation (4.13) indicates witch one the relation apply to. The
interesting thing about current conveyors is that they can implement an amplifier
without the use of any resistors. The gain is instead set by the bias current Io
which controls the intrinsic resistance, Rx , of port x. This makes it possible to
build an amplifier with transistors only and thereby avoid all resistor matching
problems.
In [11] an instrumentation amplifier using CCCIIs is presented. Since there
are no discrete CCCIIs available (only Texas instruments OPA861 that can work
as a CCCII+ are known by the author, Texas Instrument was contacted but they
do not market any CCCII-) on the market the circuit must be build from scratch.
So was done in OrCAD Capture using transistor models and schematics for the
CCCIIs presented in [12]. The schematic of this circuit can be seen in Figure A.2
and a block schematic in Figure 4.3. Equtaion (4.14) shows the transfer function
of this instrumentation amplifier.
Vo =
2Rx3
(V1 − V2 )
Rx1 + Rx2
(4.14)
This circuit has very high CMRR, 140 dB for low frequencies and still above 100
dB up to almost 200 kHz. Neither the phase nor the amplitude response are within
the requirements, but a compensation circuit as described in Section 4.3.1 can
solve that problem. The high CMRR and no influence of mismatched resistances
make this circuit very interesting. The problem is that a custom integrated circuit
layout is probably needed. The schematic includes at least 30 transistors (some
optimization of the circuit showed can be done) and a discrete layout with that
high numbers of components will cause a lot of parasitics and the performance will
be heavily degraded. A custom IC layout is out of range for this work and is also
way to expensive.
28
Differential Amplifier
Figure 4.3. IA with three CCCIIs.
4.4
Digitizer in Differential Mode
It was found that the digitizer, National Instruments PXI-5922, that is to measure the voltage after the amplifier, see Section 2.3.1, can be used with the two
channels coupled as one differential. According to the first version of the detailed
specification of the PXI-5922, [7], the CMRR should typically stay over 90 dB up
to 200 kHz. With this in mind measurements was carried out at the PXI-5922.
The results from these measurements are presented in Table 4.2.
Table 4.2. Measured CMRR of PXI-5922 in differential mode.
Frequency [kHz]
1
100
CMRR [dB]
94.5
76.1
Nom. input imp., fs
1 MΩ, 1 MHz
1 MΩ, 5 MHz
The results was not as good as expected, some deviation can be accepted
since the CMRR specification shows the typical performance and these tend to be
a bit optimistic. But over 15 dB difference is more than acceptable. After some
investigation it was found that National Instruments has changed the specifications
of the PXI-5922, see [9]. The updated CMRR specification is shown in Figure 4.4,
which corresponds much better to the measurements.
The phase and amplitude properties of this solution would be very good since
no additional error from an amplifier is added to the measurement. This solution
does however require that an additional digitizer is bought.
4.5 Comparasion Between Different Options
29
Figure 4.4. Specified CMRR for the PXI-5922 in differential mode, [9].
4.4.1
Digital Instrumentation Amplifier
One option that not has been discussed earlier would be to convert the analogue
signals to digital and implement an instrumentation amplifier in the digital domain. This would also require a digital to analogue conversion after the amplifier
to be able to input the signal to the digitizer. This, if it is not possible to tweak
the digitizer and make it possible to input digital signals. The number of ADCs
and DACs must be kept at as low level as possible to maximize the performance.
Each conversion will add errors to the signals.
Another option to reach the CMRR requirement would be to improve the
common mode suppression ability of the digitizer by optimizing the hardware.
These two options have not been fully investigated why the performance of
them is not known and hard to predict.
4.5
Comparasion Between Different Options
It is very hard to tell in advance how good an amplifier like the one presented in
Section 4.3.1 will perform when built. One solution for SP would be to use two
digitizers, the CMRR performance is not as good as wanted and this will give an
amplitude error. But since no additional amplifier is added in the measurement
chain it will be possible to perform phase measurements on current shunts with
very high accuracy since the CMRR does not affect the phase of the signals that
is to be measured.
A less expensive solution would be to implement the purposed circuit in Section
4.3.1 or to try Analog Devices AD8130. But both these solution will increase the
phase and amplitude error which will result in decreased measurement accuracy.
It is up to the researchers at SP to choose the solution they prefer.
Chapter 5
Single-Ended Amplifier
This chapter deals with the second problem of this thesis, described in Sections
2.3.1 and 2.3.3. The voltage dividers in the power meter calibration and verification
of voltage dividers circuit must work under an unloaded condition to prevent
loading errors and thereby decreased measurement accuracy. This can, as shown
in the same sections, be done by adding a buffer amplifier (i.e. gain = 1) between
the voltage divider and the digitizer. The buffer amplifier must be as transparent
as possible to affect the measurement in an as small range as possible. Very high
input impedance is a must to provide an unloaded condition and prevent loading
errors or large amplitude inaccuracy will be a fact in the measurement.
5.1
Required Performance, Single-Ended Amplifier
The goals in measurement accuracy that is desired by SP were listed in Table
2.2. These parameters can be translated into performance requirements of the
amplifiers in a similar way as for the differential amplifier. Slew rate and bandwidth
are calculated in the same way as for the differential amplifier so these are left
out here. See Sections 4.1.3 and 4.1.4. The output impedance, DC-errors and
temperature dependency should be kept to a minimum, so should the THD and
noise.
5.1.1
Input Impedance
The input impedance required to get an amplitude error less than 20 µV/V and
phase error less than 200 µrad at 100 kHz is calculated here. A similar model as
for the differential amplifier is used, see Figure 5.1.
In Section 4.1.2 an approximation of the magnitude of the transfer function
was calculated and it is shown again in Equation (5.1) with the difference that the
parameters are according to Figure 5.1.
31
32
Single-Ended Amplifier
Figure 5.1. Input impedance model.
U 1
Rdiv
R2
2
+
(ωC
R
)
2
|Z| = ≈ Rdiv 1 −
+ div
p
div
I
2
Rp
Rp2
(5.1)
The higher output impedance of the voltage divider (200 Ω compared to 0.16 Ω)
gives a smaller difference between the error terms. But Rshunt
is still significantly
Rp
R2
2
larger than shunt
and (ωCp Rshunt ) whereby they can be neglected also here.
2
Rp
The minimum Rp can thereby be calculated as below.
µV
Rdiv
≤ 20
Rp
V
⇒
Rp ≥
Rdiv
200
=
= 10 MΩ
20 · 10−6
20 · 10−6
(5.2)
Cp is also calculated in the same manner as in Section 4.1.2, see Equation (5.3).
Cp =
tan(Φ)(Rdiv + Rp )
ωRdiv Rp
(5.3)
The significantly higher output impedance, Rdiv , gives a maximum Cp of less than
2 pF, which is impossible to achieve. But since the voltage dividers are designed
to compensate for the capacitive load this will not be problem and a Cp of about
10 pF is acceptable, see [18].
5.1.2
Table of Performance
The performance parameters of the single ended buffer amplifier are listed in Table
5.1.
Table 5.1. Required performance of the single ended amplifier at 100 kHz.
Parameter
Rp
Slew Rate
Amplitude error
Phase error
Gain
Value
≥ 10 MΩ
≥ 0.9 V/µs
≤ 20 µV/V
≤ 200 µrad
Unity
5.2 Commercially Available Buffer Amplifiers
5.2
33
Commercially Available Buffer Amplifiers
There is of coarse also a market of buffer amplifiers. But to fulfil the performance
needed in this application is not trivial. Some of the best buffer amplifiers are
specified to have a gain flatness of 0.1 dB and a phase error of 0.02 degrees at
100 kHz, which is about 350 µrad. Together with these two requirements the
input resistance must be kept high enough and the DC-errors and temperature
dependency as low as possible.
Simulations of Analog Devices AD8079, which is one of the better buffer amplifiers on the market, [2], shows a gain error of 0.37 % at 100 kHz which is a bit less
than the specification of 0.1 dB but much larger than the requirement of this application. The phase response has, according to the simulation, dropped 530 µrad
at 100 kHz, which is a bit more than the 350 µrad specified by the manufacturer.
Analog Devices AD8079 is too far from the requirements to motivate further
investigation.
5.3
Custom Design
A buffer amplifier design that has very good performance was published in [1].
A somewhat updated schematic of this amplifier can be seen in Figure A.3. It
implements a form of bootstrapping, in a similar manner as the bootstrapped
instrumentation amplifier in Section 4.3.1. The bootstrapping corrects the amplitude and phase error of the op-amps. The amplifier can be considered as three
different stages that are explained step by step in the following paragraphs, see
Figure 5.2.
Figure 5.2. Sketch of the buffer amplifier.
The input stage makes sure that the input resistance and capacitance are kept
at high and low level respectively, due to the FET transistors. Figure 5.3 shows
the input stage. The FET input stage is a source follower that has a gain slightly
below unity, [6]. The op-amp circuit directly after is there to correct the gain
error of the FET stage and provide the bootstrap voltage to the first correction
stage. This circuit has a transfer function equal to Equation (4.12) but with a
gain, Av , of 1.02 and a pole frequency, fpole , of 81.2 MHz to compensate some of
34
Single-Ended Amplifier
Figure 5.3. Input stage of the buffer amplifier.
the bandwidth limitations in the op-amp.
After the input stage there are two compensation stages that correct most of the
amplitude and phase error of the input stage. They are regular voltage followers
but with bootstrapped power supplies. The output of the input stage serves as
bootstrap voltage, shifted ±4.9 V (± 5.6 V ∓ 0.7 V) for the positive and negative
respectively, to the first compensation stage. This is done by the zener diodes.
Above the zener diodes there is a current regulation diode J505 from Vishay to
reduce the voltage dependency of the zener voltage. The voltage from the zener
diodes controls the bipolar transistors that provide the power supply voltage to
the voltage followers.
As long as the voltage followers do not see any difference from the power supply
to the input there will just be a copy of the voltage from the input to the output.
For higher frequencies, when the output from the input stage starts to drop due to
the limited bandwidth and there will be a difference from the input to the power
supply. The amplifier will then have a higher output voltage to be able to satisfy
Equation (3.22), that the voltage is the same at the non-inverting and inverting
input respectively. This is how the correction works.
A slightly different way to look at the correction is to see the two correction
steps as stages producing feedforward signals that are added absolutely to the
5.3 Custom Design
35
Figure 5.4. Vector diagram of correction principle.
output signal of the input stage. This is illustrated by the vector diagram in
Figure 5.4. The ideal function would be two equal vectors, i.e. Vin = Vout . But
since the amplifier will give both amplitude and phase error the first output, Vout1 ,
differs both in magnitude and angle compared to Vin . The two following outputs
Vout2 and Vout3 correct Vout1 back to Vin almost perfectly.
The last op-amp is there to provide most of the output current when the buffer
amplifier is to drive a significant current. Assuming that the voltage is the same at
the input of the last op-amp and the output node (Vin = Vin1 = Vin2 ) the values
of the resistors are chosen according to Equation (5.4). See Figure 5.5, where R44
represent the load of the buffer amplifier and Vout−op is the output of the op-amp
(U21).
Vout−op −Vin
R48
=
Vout−op − Vin =
5.3.1
Vin
R44


Vin R45
R51

⇒
R45
R48
=
R51
R44
(5.4)
Simulation Results
Simulations of this circuit in PSPICE show that the result of the correction is
excellent. Omitting the output stage an amplitude error of less than 0.2 µV/V and
phase error less than 1 µrad, can be achieved with proper component selection and
a load of 1 MΩ when Analog Devices AD817 is used as op-amp. The frequency
dependent input resistance, Rp stays at 20 MΩ up till about 1 MHz where a
discontinuity occurs and the resistance changes to a negative value. More details
about component selection is given in Chapter 6. Simulation plots are available
in Figures B.2 and B.3.
36
Single-Ended Amplifier
Figure 5.5. Output stage of buffer amplifier.
5.4
Comparasion Between Different Options
To avoid loading errors when measuring on voltage dividers there is, as explained,
a need of a buffer amplifier. Since the buffer amplifier published in [1] performs
so well in simulation it is likely to reach the requirements even in reality. The
simulations show results that are many times better than the best commercial
available buffer amplifier found.
Chapter 6
Design of Buffer Amplifier
The simulation results of the buffer amplifier published in [1], further described
in Section 5.3, were so convincing that a decision was made to manufacture a
prototype with this topology. It was decided to use surface mount devices (SMD)
to minimize the signal paths and achieve good high frequency properties. The first
version of the buffer amplifier prototype is called version 1.0.
6.1
Component Selection
To carefully select the components is essential. The op-amps are especially important in this circuit since they directly will affect the performance of the buffer
amplifier. The small error that many other components, e.g. resistors, cause will
be corrected in the correction stages of the amplifier. Anyhow, to reach as good
performance as possible resistors, with low tolerances have been used in critical
places.
6.1.1
Op-amp Used in Version 1.0
To fulfil the requirements and work in this application the op-amp must be very
fast, have low noise and handle a large power supply span. Low input bias currents
and thus offset voltage is also important, so is the offset voltage drift with temperature. The requirement that the op-amp is fast, a lot faster than the 0.9 V/µs
calculated in Section 4.1.3, makes the amplitude and phase requirements reachable. Simulations with different op-amps have shown that a slew rate of at least
60 V/µs is a must to fulfil the requirements. To have some margin the op-amps
that were considered to use in the design have higher slew rate.
Analog Devices AD817, [3], has a slew rate of 350 V/µs and very wide supply
range from ±5 to ±15 V. But the DC-performance of this amplifier is not that good
with an offset of 0.5 mV typically and 10 µ V/℃ drift. Simulations of the buffer
amplifier with this op-amp did however show really good performance. The phase
and amplitude responses stayed well under the requirements. Rp , the frequency
dependent input resistance, was calculated in simulation according to Equation
37
38
Design of Buffer Amplifier
(3.4) and stayed at 20 MΩ up to 1 MHz. Simulation results with this op-amp were
also discussed in Section 5.3 and plots are available in Figures B.2 and B.3.
The first version of the buffer amplifier prototype used this op-amp.
6.1.2
Remaining Components
The input resistor, R3 , was changed from the original value of 10 MΩ to 20 MΩ
to have some margin to the required value of input resistance specified in Table
5.1. The resistors used are standard ±1 % size 1206 SMD.
The N-channel FET input transistors do not have any high requirements of
performance but a low input capacitance and input bias currents kept to a minimum is important. Philips Semiconductor PMBFJ112 fulfil these specifications
and are used in the prototype.
Neither the choice of zener diodes nor the bipolar transistors in the bootstrap
circuits of the corrections steps are critical. BZT52C5V6 from Multicomp are
zener diodes suitable for this task. BC817-25/PLP and BC807-25/PLP are the
choice of bipolar transistors, NPN and PNP respectively.
Since the current regulating diodes, J505 from Vishay, that were used in the
original circuit are obsolete an alternative had to be found. A direct substitute was
not possible since there no longer are any current regulating diodes on the market.
But National Semiconductor manufactures an integrated circuit with the same
function with the difference that the output current is set by an external resistor.
To get the desired current of 1 mA a resistor of 68 Ω shall be used according to
the datasheet, [20]. Precision resistors, ±0.1 % and low temperature coefficient,
were used here to get a lower drift with temperature.
All capacitors are standard ceramic multi-layer capacitors in 1206 case. The
value of the bypass capacitors were chosen to 10 nF in the bootstrap circuit.
6.2
Power Supply Circuit
To feed the active circuits with a stable voltage, a power supply circuit with voltage
regulators was designed, see Figure 6.1.
Figure 6.1. Power supply of the buffer amplifier prototype.
6.3 PCB Design
39
LM7815 and LM7915 were implemented according to the datasheet with the
difference that extra capacitors of 10 nF were added close to the voltage regulators
to ensure good bypassing for high frequencies.
This circuit is fed by an unregulated DC-voltage of ±16 V to ±25 V (±35 V
absolute maximum) and outputs a regulated voltage of ±15 V.
The op-amps and input stage are also bypassed by 100 nF capacitors physically
close to the components to reduce the effect of AC-signals superimposed on the
DC-voltage.
6.3
PCB Design
A printed circuit board (PCB) was designed in EDwin, which is a PCB layout
tool from Jeppson CAD/CAE center. The PCB uses both sides of the board.
The component layer holds a ground plane and the bottom layer holds two power
planes for Vcc and Vee .
Implementing a ground plane helps to reduce noise and ensures that all signals
are referred to the same ground potential. It also makes the design process alot
easier since all ground pins are routed directly to ground. The power planes
together with the ground plane form a large plate capacitor that contributes to
the filtering of the power supplies.
Since it is important to keep the power supply and signal paths separated the
left hand side of the PCB were dedicated to the power supply circuit and the right
hand side to the amplifier circuit.
Layout of the PCB can be seen in Figure 6.2.
Figure 6.2. PCB layout of the buffer amplifier prototype.
Chapter 7
Verification of Buffer
Amplifier
When the PCB was assembled it was time to measure the performance and see
if the buffer amplifier was as good in practice as in simulation. The first two
sections of this chapter focus on how the different measurement systems work
while the following sections present measurement results and the consequences of
the measurements. The assembled buffer amplifier can be seen in Figure 7.1.
Figure 7.1. The assembled buffer amplifier prototype.
41
42
7.1
Verification of Buffer Amplifier
Amplitude and Phase Measurement System
The amplitude and phase response was measured with National Instruments PXI5922 digitizer, [9], together with National Instruments PXI-5441 100 MS/s arbitrary waveform generator (AWG), [8]. PXI-5922 is an award winning two-channel
24-bit flexible resolution digitizer based on National Instruments Flex II ADconverter. It has a resolution of 24 bits with a sample rate of 500 kS/s and
16 bits with a sample rate of 15 MS/s. The digitizer can realize a large variety
of instruments such as oscilloscopes, spectrum analysers and AC-voltmeters. The
AWG and the digitizer are both controlled from a computer with Labview or as
here with Labview Signal Express, which is an interactive measurement software
for acquiring and analyzing signals.
Signals Express performs certain “steps” in a user configured order. A step
is for example a signal generator, data acquisition or different signal analysing
tools. To start with the frequency response was measured with white noise. But
the accuracy of this measurement was not good enough so instead a measurement
system using swept sinusoidal signals was developed. The basic structure of this
system is shown in Figure 7.2.
Figure 7.2. Principle of frequency sweep in Signal Express.
The step called “Tone Extraction” in Figure 7.2 performs a Fast Fourier Transform, FFT, of the acquired numbers of samples and exports the frequency, amplitude and relative phase of the fundamental frequency. The last step calculates the
phase and amplitude errors with channel 0 as reference, since it is coupled directly
from the AWG, see Figure 7.3. The amplitude error is the difference between the
two input signals divided by the reference signal at channel 0 to get the error as a
7.1 Amplitude and Phase Measurement System
43
Figure 7.3. Amplitude and phase error measuring setup with digitizer.
fraction. The phase error is simply the difference in detected phase. Many other
functions can be added to this measurement system as well, e.g. THD and SINAD
calculations. But even with both channels of the digitizer coupled directly from
the AWG there is a non-neglectable error that must be corrected for when really
high accuracy is required. More about this in Section 7.5.1.
7.1.1
Alternative Phase Error Calculation
Assuming that the amplitude is equal to one with a very small error compared to
the phase error, the latter can be calculated from the RMS value of the difference
between the input and output voltage of the amplifier. Using the definition of
RMS and the difference between two arbitrary signals, u, the phase error is given
by Equation (7.1).

u = sin (ωt) − sin (ωt + ϕ) 





v
u
⇒
u ZT

u1

VRM S = t
u2 (t) dt 


T

0
VRM S =
p
1 − cos ϕ
⇒
2
ϕ = arccos (1 − VRM
S)
(7.1)
The value of ϕ is expected to be a bit higher than the phase error calculated
by the tone extraction step, since the amplitude error is neglected here. This way
of determining the phase error was used as a way to check that the tone extraction
step worked as supposed.
7.1.2
Alternative Amplitude Error Measurement
The amplitude can also be determined with an available system for precision AC
voltage measurements at SP. It implements an AC-DC transfer method that converts the AC voltage into a corresponding DC voltage which is easier to measure
44
Verification of Buffer Amplifier
precisely. Fluke 792A is the transfer standard in use at SP. It is in principal
a heat sensing transistor that detects the heat emitted by a resistor that corresponds to the power dissipation in the latter. The transfer standard outputs a DC
voltage that corresponds to the RMS value of the AC input voltage. Repeated
measurements are performed at each frequency to minimize the error. The system
is interfaced to a computer that logs all measurements.
7.2
Input Impedance Measurements
The input impedance was measured with Wayne Kerr 6440 precision LCR meter,
but measuring as high ”active“ impedances as about 20 MΩ is not trivial. Some
problems were encountered with this method, especially for low frequencies. A
capacitive and resistive coupling between the laboratory power supply, that feeds
the buffer amplifier, and the internal power supply of the LCR meter over the
power distribution grid was found to be the reason. To avoid affects of this in
the measurement, the amplifier was power supplied by a battery pack during
measurements.
The input impedance of version 1.1 of the buffer amplifier was also measured
with a traditional method using the AC-DC transfer standard method described
in Section 7.1.2. The output voltage of the amplifier is observed with (Ux ) and
without (U0 ) a series impedance (Rs or Cs ) at the input of the amplifier. The
series impedance creates a voltage divider together with the input impedance, Rp
and Cp . The higher the input impedance is the less the series impedance will affect
the output voltage. This method is described in [21] where Equations (7.2) and
(7.3) are used to calculate Cp and Rp respectively. The inductance of the series
resistor is denoted LR .
U0 −1
(7.2)
Cp ∼
= Cs · UC Rp ∼
= q
7.3
U0
URs
Rs
2
+ ω (2LR Cp − (Rs Cp )2 ) − 1
(7.3)
Measurement Results Version 1.0
Some problems were encountered with the amplifier in the beginning. A quite
heavy load had to be connected to the amplifier to avoid oscillations. The op-amp
in use, Analog Devices AD817, must drive a significant current not to oscillate. So,
a load of 50 Ω was connected to the amplifier during the following measurements.
The current driving stage was configured to drive a load of 50 Ω during these
measurements.
Figure 7.4 shows the amplitude error of the first version of the buffer amplifier.
It can be seen that there is a quite large frequency independent error and the
amplitude deviates about 100 µV/V from 2kHz to 100 kHz. This is a many times
larger error than the simulation showed, see Section 5.3.1. The 50 Ω load degrades
7.3 Measurement Results Version 1.0
45
Figure 7.4. Amplitude error of the buffer amplifier in version 1.0.
the results, which also can be seen in simulation, but it is likely to affect even more
in reality.
Figure 7.5. Amplitude error of the buffer amplifier in version 1.0 measured with AC-DC
transfer.
Figure 7.5 shows the amplitude error measured with the AC-DC transfer method
described in Section 7.1.2. The error at 100 kHz is about 100 µV/V in both measurements, but the AC-DC measurement shows a more linear behaviour at low
frequencies.
Also the phase error of the buffer amplifier is a lot larger than expected, about
4 mrad at 100 kHz, see Figure 7.6. The upper line in Figure 7.7 shows the phase
error calculated as described in Section 7.1.1. The phase errors are in the same
order of magnitude in both measurements.
Neither the resistive part of the input impedance, Rp , was as good as expected
in this version of the buffer amplifier, see Figure 7.8. According to the simulation,
Rp should stay at the value of the input resistor, R3 , until a discontinuity occur
and it changes to a negative value at about 1 MHz. The measurement shows that
46
Verification of Buffer Amplifier
Figure 7.6. Phase error of the buffer amplifier in version 1.0.
Figure 7.7. The upper line shows the phase error of the buffer amplifier in version 1.0
- from RMS.
the discontinuity comes much earlier, at about 40 kHz. However, the capacitive
part of the input impedance, Cp , stays at about 12 pF for all measured frequencies.
Simulations and measurements on Analog Devices AD817 as a standard voltage
follower without bootstrapping shows that there is a discontinuity in Rp at lower
frequencies, similar to the one seen in the measurements on the complete buffer
amplifier. Since there are two voltage followers in parallel seen from the input of
the buffer amplifier this must have been the reason why the measurement looked
as it did. The location of the discontinuity depends on the load as well but only
to a small extent.
7.3.1
Conclusions
Due to the need of a heavy load to prevent oscillations and thereby large amplitude
and phase errors together with the unacceptable behaviour of the input impedance
lead to the requirement of another op-amp. Selecting the perfect op-amp for a
demanding application like this is not trivial.
7.4
New Op-Amps, Buffer Amplifier 1.1
A long list of op-amps that were tried but did not comply with the requirements
could be listed but there is really no reason to do so. Instead the op-amps of choice
7.4 New Op-Amps, Buffer Amplifier 1.1
47
Figure 7.8. Input impedance of buffer amplifier version 1.0.
are presented. Op-amps that showed a similar behaviour in the input impedance
as the AD817 were directly disregarded.
As bootstrapped op-amps, i.e. the op-amps in the two correction steps, Analog
Devices ADA4899 were chosen, [4]. It is a unity gain stable bipolar input op-amp
with extremely low noise, high bandwidth, high slew rate, low output impedance
and descent DC properties. Good DC properties, such as low output offset and
low input bias currents are not easily combined with high speed. All op-amps that
focus on DC properties are way to slow for this application. The drawback with
ADA4899 is that it can not handle as large variations in the power supply voltage
as is required to work in all positions in the buffer amplifier, this also leads to
a lowered maximum input voltage but the required 0.8 V (which is the output
voltage of the voltage divider) can be applied with margin. The op-amp in the
input stage must also be able to handle a large differential input voltage since Vcc
is fed to its input when no input signal is applied.
So for the input stage and the optional output stage Analog Devices AD8510
was chosen. It is a JFET op-amp with low noise and wide bandwidth. It can
handle power supplies from ±5 V to ±15 V and a differential input voltage as
large as the power supply voltage.
Figure A.3 shows the buffer amplifier in version 1.1.
7.4.1
Simulation Results
Simulations of the buffer amplifier with op-amp configuration as described above
shows really good results. With no output stage and load of 1 MΩ, the amplitude
error is less than 1 µV/V and a phase error less than 1 µrad at 100 kHz. The
resistive part of the input impedance, Rp does not deviate much from the earlier
version but the discontinuity is slightly shifted down in frequency and has its top
at about 1 MHz. The capacitive part stays constant at 3 pF up to 1 MHz. The
DC offset is -500 nV which is a lot smaller than with AD817, however a larger DC
48
Verification of Buffer Amplifier
offset is expected in reality since ADA4899 is specified to have an offset of 35 µV
typically.
7.5
Measurement Results Version 1.1
No large load is required to keep the buffer amplifier stable in version 1.1. The
only load connected during the measurements is the measuring instrument, e.g.
the digitizer, which has a nominal input impedance of 1 MΩ. In other words, no
large currents are driven by the amplifier why the current driving stage has been
left out during the following measurements.
The ability of the amplifier to drive a capacitive load was investigated and
found to be about 800 pF, which corresponds to 8 m of coaxial cable.
7.5.1
Amplitude and Phase
The amplitude and phase error are so small in this version of the buffer amplifier
that the error from the digitizer itself must be corrected. First a measurement
with both channels coupled directly to the digitizer was performed. The measured
error is then subtracted from the measurement so that only the error of the buffer
amplifier is left. All data processing was done in MATLAB whereto text files were
exported.
The environment in which the measurement is done in is essential. Electrical fields in the surroundings induce voltages that affect the measurement. The
first normalized measurements of the buffer amplifier showed quite a lot of disturbances. But since they were seen in the measurements without the amplifier as
well they were not created by the amplifier. The frequency and amplitude of the
disturbances varied slightly with time why they are not completely eliminated in
the corrected measurement, see Figure B.4.
The spectrum of the surroundings was measured with an open cable, see Figure
B.5. The frequencies of the tops in the spectrum approximately correspond to the
frequencies that are disturbed in the amplitude and phase measurement. Some
experimentation showed that the big disturbances are due to the LCD screen of
the laptop that is coupled to the PXI system. When this computer is moved about
2 m away the disturbances no longer appears in the measurements.
Figure 7.9 shows the average amplitude and phase error over three measurements. It is also slightly smoothed by the MATLAB function “smooth” which uses
a five point moving average. The phase error is really small, less than 15 µrad at
100 kHz which is a lot better than the required 200 µrad. The amplitude error
shows a frequency independent error but the amplitude does not deviate much
from the low frequency error at higher frequencies, less than 20 µV/V from 2 kHz
to 100 kHz. The amplitude error is also within the requirements.
The standard deviation of these three measurements is shown in Figure 7.10,
and stays at moderate levels over the whole frequency range. This means that the
amplitude and phase measurements are robust and repeatable.
Figure B.6 shows the phase and amplitude error up to 2 MHz.
7.5 Measurement Results Version 1.1
49
Figure 7.9. Amplitude and phase error average of the buffer amplifier in version 1.1.
7.5.2
Input Impedance
Figures 7.11 and 7.12 shows the resistive and capacitive part of the input impedance
respectively. The low frequency discontinuities that were seen in the input resistance measurement (Figure 7.8) of the amplifier in version 1.0 are now gone and
only one discontinuity is seen, just as in simulation. The location of the discontinuity also corresponds well to the simulation. Rp is equal to 10.5 MΩ at 100 kHz
which is higher than the requirement.
Cp stays at a constants level as expected, not as low as the simulation shows but
well at 12.4 pF. The value was expected to deviate a few pF from the simulation
since only the SMB input contact adds 5-10 pF.
Due to the fact that the measurements with the LCR meter is not very robust
the traditional measurement method described in Section 7.2 was performed. Since
the inductance in the series resistance, LR in Equation (7.3), plays a small role for
the result this term was neglected. The method does not give good accuracy for
low frequencies since the standard deviation of the measurement is larger than the
ratio UUR0 for the used Rs of 100 Ω (this means that Rp is high). Larger resistances
can be used to increase the resolution for low frequencies, so was not done since it
is the input resistance at high frequencies that is interesting. Table 7.1 shows the
results of the measurements.
Two measurements with different input voltage and load were performed. When
1 V was applied the load resistance of the buffer amplifier was 400 Ω and when
200 mV was applied the load was 10 MΩ. This is due to the input resistance of
50
Verification of Buffer Amplifier
Figure 7.10. Standard deviation of three amplitude and phase error measurements.
Table 7.1. Input resistance, Rp , in MΩ of the buffer amplifier in version 1.1 measured
by AC-DC transfer standards.
Input voltage
1V
200 mV
100 kHz
17.2
14.1
500 kHz
4.1
2.6
1 MHz
2.4
1.6
the AC-DC transfer standards which vary with the selected voltage range.
7.5.3
THD and SINAD
THD and SINAD were measured with the PXI-5922 digitizer, in a similar manner
as amplitude and phase. Figure 7.13 shows how the THD and SINAD vary with
frequency.
The noise and distortion properties of the buffer amplifier are very good. This
is much thanks to the low noise op-amp, Analog Devices ADA4899.
7.5.4
Power Supply Voltage Dependency
The voltage regulators in the power supply circuit on the PCB are there to ensure
that the buffer amplifier does not depend on the voltage that is fed to it. To verify
this, repeated measurements with different power supply voltages were performed.
Measurement confirms theory in this case, since the standard deviation is not much
7.5 Measurement Results Version 1.1
51
Figure 7.11. Input Rp of the buffer amplifier in version 1.1.
Figure 7.12. Input Cp of the buffer amplifier in version 1.1.
larger when the power supplies are varied compared to repeated measurements
with constant power supply voltage. Compare Figure 7.14 and Figure 7.10.
7.5.5
Ambient Temperature Dependency
The effect of the ambient temperature was investigated by placing the amplifier in
a temperature regulated box, see Figure 7.15. Measurements was carried out at
15, 20, 25 and 30 ℃ which were compared to measurements at the normal ambient
temperature of 23 ℃. The accuracy of the ambient temperatures are ±0.1 ℃ for
20, 23 and 25 ℃ and ±0.2 ℃ for 15 and 30 ℃. The amplifier was turned on
for at least 6 h in each temperature before the measurement was made. Figure
7.16 shows how the amplitude and phase error changes from 23 to 30 ℃ ambient
temperature. Figure B.7 shows the remaining ambient temperatures.
No large deviations can be seen, the amplifier is very stable with temperature.
52
Verification of Buffer Amplifier
Figure 7.13. SINAD and THD of the buffer amplifier in version 1.1.
One interesting thing that can be observed is that the frequency independent error
decreases slightly in low temperatures.
7.5.6
Warm-Up Time
The warm-up time was measured by doing a quick frequency sweep with only a
few steps every 20 seconds until no large deviations were observed. After about
two minutes the changes in amplitude and phase error are small and the amplifier
is close to a steady state. See Figure 7.17 where the error at 113 kHz is shown for
the first 10 min after startup, observe that the error of the digitizer itself not has
been removed in this measurement. Other frequencies show a similar behaviour
except DC, for which it takes almost 15 minutes until no significant changes can
be seen, see Figure B.8.
7.5.7
Conclusions
The measurements of the buffer amplifier prototype in version 1.1 show very good
results. The phase response is well within the requirements and the THD and
SINAD are impressively low. The input impedance stays within the requirement
of 10 MΩ but the results from the two measurements differ. Both input impedance
measurements do however show an input impedance that satisfy the requirements.
The amplitude error complies with the requirement but not much more. Though,
if the amplitude error of the buffer amplifier and the loading error due to the finite
7.5 Measurement Results Version 1.1
53
Figure 7.14. Standard deviation with three different power supply voltages.
input impedance are summarized they will tend to cancel each other since the
amplifier has a top in the frequency response for high frequencies.
The prototyped buffer amplifier can be modified to handle larger input voltages
if this is necessary but since the application in this case not requires a higher input
voltage, this property has not been prioritized. If the buffer amplifier is to drive
a significant load, it is recommended to match the output resistors according to
Equation (5.4), to minimize the phase and amplitude errors. When high impedance
loads are driven the output stage is best disconnected.
54
Verification of Buffer Amplifier
Figure 7.15. Ambient temperature dependency test setup.
Figure 7.16. Difference in amplitude and phase error from 23 to 15 and 25 ℃.
7.5 Measurement Results Version 1.1
55
Figure 7.17. Amplitude and phase error the first 10 min after startup at 113 kHz.
Chapter 8
Discussion and Conclusions
8.1
Discussion
For the second problem of this project, to provide an unloaded condition for the
voltage divider during calibration of power meters and verification of voltage dividers, it was easier to find a good solution than to suppress the common mode
voltage that occurs for current shunts in the corresponding situation. The requirements of an extremely high CMRR together with a linear phase and amplitude
are what make the latter problem very complex.
The models used in simulation are according to the manufacturers specified
by the minimum performance of the circuits. But the accuracy of these models
must be considered anyway. Conclusions from simulations must be questioned,
they seldom reflect the reality when small deviations are simulated. Experience
from this project shows this, many times better results were reached in simulation
than measured for the prototyped buffer amplifier. This might be due to the
limited resolution i PSPICE, inaccurate component models or parasitics that are
not included in the simulations. Of course, parasitics could have been included in
simulations but to place and size them properly is not trivial. This can lead to a
simulation that is further away from reality if the parasitics are sized and placed
incorrectly.
The fact that the simulations and measurements differ a lot for the buffer
amplifier talks against the proposed bootstrapped instrumentation amplifier in
which the simulations results live up the requirements with a quite small margin.
The best solution is probably to use the digitizer in differential mode to solve the
common mode voltage problem. It does not satisfy the requirement of CMRR but
maybe it is possible to do some hardware improvement of the digitizer.
Uncertainty in the measurements of the prototyped buffer amplifier must be
considered. But since the standard deviation between different measurements is as
low as shown in Figure 7.10 the measurements are considered robust and clearly
repeatable. The amplitude measurement also corresponds well to the precision
AC-DC amplitude measurement with transfer standards, and the phase with the
alternative way of calculation in Section 7.1.1. The input impedance has been
57
58
Discussion and Conclusions
measured with two different methods with differing results, but both show that
the input Rp exceeds 10 MΩ at 100 kHz which is the requirement.
The buffer amplifier prototype satisfies the requirements, and compared to
similar published amplifiers it performs well. For example the millivolt-amplifier
in [22], which has very high input impedance (> 20 MΩ) up to 100 kHz but an
amplitude error of 70 µV/V at the same frequency. This is a much larger error
than the prototyped buffer amplifier in this thesis.
Further work with the buffer amplifier would be a PCB optimized for the opamps in version 1.1 and a more appropriate enclosure.
8.2
Conclusions
To the first problem of this project three alternative solutions are presented; prototype a proposed instrumentation amplifier circuit, evaluate the commercially
available instrumentation amplifier Analog Devices AD8130 or let the voltage
measuring device suppress the common mode voltage. One fourth alternative,
to improve the digitizer or suppress the common mode digitally before the digitizer, was also briefly discussed. It is up to the researchers at SP to choose a
solution.
The second problem of this project, how to provide an unloaded condition
for voltage dividers during calibration of power meters and verification of voltage
dividers was solved by building a prototype buffer amplifier. Measurements of it
showed an amplitude error of less than 20 µV/V, a phase error of less than 20
µrad, and an input impedance greater than 10 MΩ. This is performance in line
with the required in Table 2.2.
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http://www.analog.com/static/
imported-files/data_sheets/AD8079.pdf, 2008-06-18, Revision A, 1996.
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imported-files/data_sheets/AD817.pdf, 2008-09-29, Revision B, 2006.
√
[4] Analog Devices. Ada4899-1: Unity-gain stable, ultralow distortion, 1nv/ Hz
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[5] Analog Devices.
Analog devices ad8129/ad8130.
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imported-files/data_sheets/AD8129_8130.pdf, 2008-08-26, Revision C,
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2008-09-03,
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http://www.analog.com/en/training-and-tutorials/tutorials/
design-center/tutorials/CU_tutorials_MT-003/resources/fca.html,
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[11] Sudhanshu Maheshwari. High cmrr wide bandwidth instrumentation amplifier using current controlled conveyors. International Journal of Electronics,
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Op-amps for everyone, design reference.
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[14] Maxim.
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[16] Hewlett Packard. HP 4285A Precision LCR Meter Operational Manual.
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Appendix A
Schematics
63
64
Schematics
Figure A.1. Three op-amp instrumentation amplifier with compensation.
65
Figure A.2. IA with three CCCII.
66
Schematics
Figure A.3. Buffer amplifier version 1.1.
Appendix B
Plots
67
68
Plots
Figure B.1. CMRR of three op-amp IA with compensation.
69
Figure B.2. Amplitude and Phase of buffer amplifier with AD817.
70
Plots
Figure B.3. Input Rp of buffer amplifier version 1.0.
71
Figure B.4. Amplitude and phase error measurement with disturbances.
Figure B.5. Spectrum of the measurement environment.
72
Plots
Figure B.6. Amplitude and phase error buffer amplifier version 1.1.
Figure B.7. Difference in amplitude and phase error from 23 to 20 and 30 ℃.
73
Figure B.8. DC-offset change the first 15 min after startup.
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