Download Design of Ultra-Low-Power Analog-to-Digital Converters Dai Zhang

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Linköping Studies in Science and Technology
Thesis No. 1548
Design of Ultra-Low-Power
Analog-to-Digital Converters
Dai Zhang
Electronic Devices
Department of Electrical Engineering
Linköpings universitet
SE-581 83 Linköping, Sweden
Linköping 2012
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ISBN 978-91-7519-820-0
ISSN 0280-7971
LIU-TEK-LIC-2012:33
Printed by LiU-Tryck, Linköping, Sweden, 2012
Copyright © Dai Zhang 2012
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Acknowledgments
Many people have contributed to my progress as a PhD student along the way. I
would like to express my deepest gratitude to them:
• my supervisor, Prof. Atila Alvandpour, for offering me the opportunity to
pursue my postgraduate study here. He is extremely supportive and has given
me invaluable advice and help on doing research and paper writing.
• Prof. emeritus Christer Svensson. Discussing research problems with him is
very enjoyable, and I can always get insightful feedbacks.
• Christer Jansson for all the interesting technical discussions and invaluable
comments on my circuit design.
• Ameya Bhide. The collaboration with him on our first chip was efficient and
fruitful. Also, thanks to him for being a friendly company here.
• Arta Alvandpour for taking care of the PCB designs, solving computer- and toolrelated problems. Also, thanks to him for teaching me driving and car-related
issues.
• Ali Fazli for the great collaboration on teaching. He is really skillful at explaining tutorial solutions.
• Timmy Sundström and Jonas Fritzin. As senior PhD students in the group
when I came here, they have given me many valuable help, guidance, and
encouragement in research.
• Prakash Harikumar for helping me to improve my English and for being a great
friend.
• Anna Folkesson and Maria Hamnér, who have been invaluable in their efforts
to simplify all the administrative details.
• all former and present members of the Division of Electronic Devices. Because
of them, the working atmosphere is so friendly and fun that I enjoy here.
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iv
• all my friends who have made my life memorable.
• last but not least, my family who always have faith in me. I could not finish
this thesis without their tremendous encouragement and unconditional support.
Dai Zhang
Linköping, July 2012
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Abstract
Power consumption is one of the main design constraints in today’s integrated circuits.
For systems powered by small non-rechargeable batteries over their entire lifetime,
such as medical implant devices, ultra-low power consumption is paramount. In these
systems, analog-to-digital converters (ADCs) are key components as the interface
between the analog world and the digital domain. This thesis addresses the design
challenges, strategies, as well as circuit techniques of ultra-low-power ADCs for
medical implant devices.
Medical implant devices, such as pacemakers and cardiac defibrillators, typically require low-speed, medium-resolution ADCs. The successive approximation
register (SAR) ADC exhibits significantly high energy efficiency compared to other
prevalent ADC architectures due to its good tradeoffs among power consumption,
conversion accuracy, and design complexity. To design an energy-efficient SAR ADC,
an understanding of its error sources as well as its power consumption bounds is
essential. This thesis analyzes the power consumption bounds of SAR ADC: 1) at
low resolution, the power consumption is bounded by digital switching power; 2) at
medium-to-high resolution, the power consumption is bounded by thermal noise
if digital assisted techniques are used to alleviate mismatch issues; otherwise it is
bounded by capacitor mismatch.
Conversion of the low frequency bioelectric signals does not require high speed,
but ultra-low-power operation. This combined with the required conversion accuracy
makes the design of such ADCs a major challenge. It is not straightforward to effectively reduce the unnecessary speed for lower power consumption using inherently
fast components in advanced CMOS technologies. Moreover, the leakage current
degrades the sampling accuracy during the long conversion time, and the leakage
power consumption contributes to a significant portion of the total power consumption.
Two SAR ADCs have been implemented in this thesis. The first ADC, implemented
in a 0.13-µm CMOS process, achieves 9.1 ENOB with 53-nW power consumption
at 1 kS/s. The second ADC, implemented in a 65-nm CMOS process, achieves the
same resolution at 1 kS/s with a substantial (94%) improvement in power consumption, resulting in 3-nW total power consumption. Our work demonstrates that the
ultra-low-power operation necessitates maximum simplicity in the ADC architecture.
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Contents
1
Introduction
1.1 Motivation . . . . . . . . . . . . . . . . . . .
1.2 Review of Power-Efficient ADC Architectures
1.3 Design Challenges and Strategies . . . . . . .
1.4 Thesis Organization . . . . . . . . . . . . . .
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1
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2
SAR ADC Precision Considerations
2.1 Sampling Circuit . . . . . . . . . . . . . . . . .
2.1.1 Thermal Noise . . . . . . . . . . . . . .
2.1.2 Aperture Error . . . . . . . . . . . . . .
2.1.3 Switch-Induced Error . . . . . . . . . . .
2.1.4 Track Bandwidth . . . . . . . . . . . . .
2.1.5 Voltage Droop . . . . . . . . . . . . . .
2.2 Capacitive DAC . . . . . . . . . . . . . . . . . .
2.2.1 Single Binary-Weighted Capacitive Array
2.2.2 Split Binary-Weighted Capacitive Array .
2.3 Comparator . . . . . . . . . . . . . . . . . . . .
2.3.1 Offset . . . . . . . . . . . . . . . . . . .
2.3.2 Thermal Noise . . . . . . . . . . . . . .
2.3.3 Flicker Noise . . . . . . . . . . . . . . .
2.3.4 Metastability . . . . . . . . . . . . . . .
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SAR ADC Power Consumption Bounds
3.1 Power Consumption Estimation of DAC . . . . . . . . . .
3.2 Power Consumption Estimation of Comparator . . . . . .
3.3 Power Consumption Estimation of SAR Logic . . . . . . .
3.4 Power Consumption Estimation of a Complete SAR ADC
3.5 Comparison to Experimental Data . . . . . . . . . . . . .
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viii
CONTENTS
4
A 53-nW 9.1-ENOB SAR ADC in 0.13 µm CMOS Process
4.1 ADC Architecture . . . . . . . . . . . . . . . . . . . .
4.2 Circuit Implementation . . . . . . . . . . . . . . . . .
4.2.1 Capacitive DAC . . . . . . . . . . . . . . . .
4.2.2 Switch Design . . . . . . . . . . . . . . . . .
4.2.3 Dynamic Latch Comparator . . . . . . . . . .
4.2.4 SAR Control Logic . . . . . . . . . . . . . . .
4.3 Measurement Results . . . . . . . . . . . . . . . . . .
5
A 3-nW 9.1-ENOB SAR ADC in 65 nm CMOS Process
5.1 Comparison in Leakage between 0.13 µm and 65 nm CMOS Processes
5.2 ADC Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2.1 Split-Array DAC . . . . . . . . . . . . . . . . . . . . . . .
5.2.2 Bottom-Plate Sampling . . . . . . . . . . . . . . . . . . . .
5.2.3 Low-Voltage Single Supply . . . . . . . . . . . . . . . . .
5.3 Circuit and Chip Implementation . . . . . . . . . . . . . . . . . . .
5.3.1 Capacitive DAC . . . . . . . . . . . . . . . . . . . . . . .
5.3.2 Switch Design . . . . . . . . . . . . . . . . . . . . . . . .
5.3.3 Dynamic Latch Comparator . . . . . . . . . . . . . . . . .
5.3.4 SAR Control Logic . . . . . . . . . . . . . . . . . . . . . .
5.3.5 Chip Implementation . . . . . . . . . . . . . . . . . . . . .
5.4 Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . .
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Conclusions
67
References
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List of Figures
1.1
1.2
1.3
1.4
1.5
1.6
A simplified pacemaker system. . . . . . . . . . . . . . . . . . . .
Voltage and frequency ranges of four classes of bioelectric signals,
where EOG, EEG, ECG, and EMG refer to the electrooculogram, the
electroencephalogram, the electrocardiogram, and the electromyogram, respectively. . . . . . . . . . . . . . . . . . . . . . . . . . .
Published ADCs: (a) power vs. Nyquist sampling rate. (b) power vs
SNDR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A basic SAR ADC. . . . . . . . . . . . . . . . . . . . . . . . . . .
A basic first-order Σ∆ ADC. . . . . . . . . . . . . . . . . . . . . .
Simulated average power consumption versus switching frequency of
an inverter with a fan-out of four in 0.13-µm CMOS process. . . . .
2.1
Sampling circuit:(a) basic circuit (b) switch on-resistance versus input
voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Aperture error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3 Sources of switch-induced error of sampling circuit. . . . . . . . . .
2.4 A single binary-weighted capacitive DAC. . . . . . . . . . . . . . .
2.5 A split binary-weighted capacitive DAC. . . . . . . . . . . . . . . .
2.6 A modified split binary-weighted capacitive DAC to avoid fractional
value of bridge capacitor. . . . . . . . . . . . . . . . . . . . . . . .
2.7 A simplified DAC circuit with the whole sub-DAC connected to ground.
2.8 A simplified DAC circuit with the whole main-DAC connected to
ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.9 Unit capacitance and total array capacitance versus main-DAC resolution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.10 A dynamic latch comparator. . . . . . . . . . . . . . . . . . . . . .
3.1
3.2
3.3
Charge-redistribution SAR ADC. . . . . . . . . . . . . . . . . . . .
Typical signal transient behavior including the differential outputs
and the supply current. Note that there is no static supply current. . .
A typical design of SAR digital logic. . . . . . . . . . . . . . . . .
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x
LIST OF FIGURES
3.4
3.5
3.6
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
4.10
4.11
4.12
4.13
4.14
4.15
4.16
5.1
5.2
5.3
5.4
5.5
5.6
5.7
An extraction example of Ak and Vef f based on simulation. . . . .
Predicted power consumption bounds for both noise-limited and
mismatch-limited SAR ADCs together with their individual components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Predicted power consumption bounds (solid line for mismatch-limited
and dashed line for noise-limited) together with Nyquist SAR ADC
survey data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Architecture of the SAR ADC. . . . . . . . . . . . . . . . . . . . .
The sampling phase of capacitive DAC with MSB preset. . . . . . .
Waveform of the DAC switching procedure. . . . . . . . . . . . . .
Layout of the capacitor array which follows a partial common-centroid
configuration. The capacitors are indicated according to Fig. 4.1. . .
Top-plate sampling switch. . . . . . . . . . . . . . . . . . . . . . .
Simulated leakage current of the sampling switch: (a) test-bench (b)
leakage current versus input voltage. . . . . . . . . . . . . . . . . .
Dynamic latch comparator. . . . . . . . . . . . . . . . . . . . . . .
SAR control logic. . . . . . . . . . . . . . . . . . . . . . . . . . .
Time sequence of the synchronous SAR control logic. . . . . . . . .
Level shifter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Die photograph of the ADC in 0.13-µm CMOS technology. . . . . .
Measured DNL and INL errors. . . . . . . . . . . . . . . . . . . . .
Measured 8,192-point FFT spectrum at 1 kS/s. . . . . . . . . . . . .
ENOB of the ADC versus input frequency. . . . . . . . . . . . . . .
The ADC power breakdown in dual and single supply modes, where
the percentage of digital leakage power is indicated by dark color. .
Predicted mismatch-limited SAR ADC power consumption bounds (solid
line) together with Nyquist SAR ADC survey data (∆) and the implemented ADC (o). . . . . . . . . . . . . . . . . . . . . . . . . . . .
Simulated transistor sub-threshold leakage current versus channel
length in standard 0.13 µm process at 0.15-µm Wmin , 1-V supply,
typical corner, and 27o C. . . . . . . . . . . . . . . . . . . . . . . .
Simulated transistor sub-threshold leakage current versus channel
length in low-power 65 nm process at 0.135-µm Wmin , 1-V supply,
typical corner, and 27o C: (a) standard-VT devices (b) high-VT devices.
SAR ADC architecture. . . . . . . . . . . . . . . . . . . . . . . . .
Time sequence of SAR ADC. . . . . . . . . . . . . . . . . . . . . .
DAC arrays during (a) reset phase (b) sampling phase. . . . . . . .
Layout floor plan of the capacitor array. The capacitors, not indicated
in the figure, are dummies. . . . . . . . . . . . . . . . . . . . . . .
The parasitic capacitance of the bridge capacitor: 1) connected to the
main-DAC (Case 1); 2) connected to the sub-DAC (Case 2). . . . .
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LIST OF FIGURES
5.8
5.9
5.10
5.11
5.12
5.13
5.14
5.15
(a) Top-plate switches. (b) Bottom-plate switches. . . . . . . . . . .
Voltage boosting circuit with bypass function. . . . . . . . . . . . .
Dynamic latch comparator with high- and standard-VT transistors. .
SAR digital control logic. . . . . . . . . . . . . . . . . . . . . . . .
Latch circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Die photo and layout view of the ADC in 65 nm CMOS process. . .
Measured DNL and INL errors of 1-kS/s 0.7-V ADC. . . . . . . . .
Measured 8,192-point FFT spectrums of 1-kS/s 0.7-V ADC: (a) near
DC (b) near Nyquist. . . . . . . . . . . . . . . . . . . . . . . . . .
5.16 Predicted mismatch-limited SAR ADC power consumption bounds (solid
line) together with Nyquist SAR ADC survey data (∆) and the implemented ADCs (o). . . . . . . . . . . . . . . . . . . . . . . . . . . .
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xii
LIST OF FIGURES
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List of Tables
2.1
Required Minimum Capacitance Versus Resolution based on Eq. (2.2) 10
3.1
Parameter Values Used in Eq. (3.17) . . . . . . . . . . . . . . . . .
32
4.1
4.2
4.3
ADC Measurement Summary . . . . . . . . . . . . . . . . . . . . .
ADC Performance Under Different Supply Settings . . . . . . . . .
ADC Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . .
48
48
48
5.1
ADC Dynamic Performance With Respect to Bridge Capacitor Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Simulated Power Consumption . . . . . . . . . . . . . . . . . . . .
ADC Measurement Summary . . . . . . . . . . . . . . . . . . . . .
Measured ADC Performance Under Different Supply Voltages . . .
ADC Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . .
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62
65
65
65
5.2
5.3
5.4
5.5
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xiv
LIST OF TABLES
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List of Abbreviations
ADC
Analog-to-Digital Converter
AFE
Analog Front End
CMOS
Complementary Metal Oxide Semiconductor
DAC
Digital-to-Analog Converter
DFF
D-type Flip Flop
DNL
Differential Nonlinearity
DSP
Digital Signal Processor
ENOB
Effective Number of Bit
ERBW
Effective Resolution Bandwidth
FFT
Fast Fourier Transform
FOM
Figure of Merit
INL
Integral Nonlinearity
ISSCC
International Solid-State Circuits Conference
JLCC
J-Leaded Chip Carrier
LPF
Low-Pass Filter
LSB
Least Significant Bit
MIM
Metal Insulator Metal
MSB
Most Significant Bit
SAR
Successive Approximation Register
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xvi
List of Abbreviations
SFDR
Spurious-Free Dynamic Range
SMR
Signal-to-Metastability-Error Ratio
SNDR
Signal-to-Noise-and-Distortion Ratio
SNR
Signal-to-Noise Ratio
THD
Total Harmonic Distortion
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Chapter 1
Introduction
1.1
Motivation
An analog-to-digital converter (ADC) converts real-world continuous signals to discrete digital numbers. As the interface between the analog world and the digital
domain, ADCs are ubiquitous in many applications. The applications that require
ultra-low-power consumption in the ADC are frequently found in wireless sensor networks [1][2][3] and biomedical interfaces [4][5].These systems are typically powered
by harvested energy or small batteries, thereby placing stringent requirements on the
power consumption of the circuits.
Implantable medical electronics, such as pacemakers and cardiac defibrillators,
are typical examples of devices where ultra-low-power consumption is paramount.
The implanted units rely on a small nonrechargeable battery to sustain a lifespan of
up to 10 years. Fig. 1.1 shows a simplified pacemaker system [6]. The ADC is a key
component in such systems as the interface between the analog front end (AFE) and
the digital signal processor (DSP). The bioelectric signals, shown in Fig. 1.2, have
dynamic range between tens of micro-volt to hundreds of milli-volt, and they cover a
frequency band where the highest frequency is less than 10 kHz [7]. Measuring these
bioelectric signals requires medium-resolution, low-speed ADCs.
This thesis will focus on the design and implementation of ultra-low-power ADCs
working at medium resolution (e.g., 10 bit) and low speed (e.g., 1 kS/s) for medical
implant devices.
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Introduction
Power
Management
2
Sensing
Filtering
Amplifying
ADC
Clock
Programmable
Digital Functions
Pace
Driver
Pace
Multiplexing
Figure 1.1: A simplified pacemaker system.
V (V)
100m
EMG
10m
1m
ECG
EEG
100µ
EOG
10µ
0.01 0.1
1
10 100 1K 10K
f (Hz)
Figure 1.2: Voltage and frequency ranges of four classes of bioelectric signals, where EOG, EEG,
ECG, and EMG refer to the electrooculogram, the electroencephalogram, the electrocardiogram,
and the electromyogram, respectively.
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1.2 Review of Power-Efficient ADC Architectures
1.2
3
Review of Power-Efficient ADC Architectures
Since ultra-low-power operation is critical in the design, architecture selection is
driven by an examination of the power consumption of prevalent ADCs. Fig. 1.3
plots the power consumption of ADCs versus the sampling rate and the signal-tonoise-and-distortion ratio (SNDR), respectively. The ADCs were published in the
international solid-state circuits conference(ISSCC) between 1997 and 2012 [8]. As
shown, successive approximation register (SAR) ADCs and oversampling ADCs
are typically used for low-speed, medium-to-high resolution applications. Pipelined
ADCs dominate at medium-speed and medium-resolution applications, and flash
ADCs at high-speed and low-resolution. With respect to the desired speed and
resolution, SAR and oversampling ADCs are primary candidates due to their good
power efficiency.
4
10
2
Power [mW]
10
0
10
SAR
Pipelined
Oversampling
Flash
−2
10
−4
10
0
2
10
4
6
10
10
10
Nyquist Sampling Rate [kHz]
8
10
(a)
4
10
2
Power [mW]
10
0
10
−2
10
−4
10
20
40
SAR
Pipelined
Oversampling
Flash
60
80
100
120
SNDR [dB]
(b)
Figure 1.3: Published ADCs: (a) power vs. Nyquist sampling rate. (b) power vs SNDR.
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4
Introduction
Figure 1.4 shows the architecture of a basic SAR ADC. It consists of a sampleand-hold circuit, a digital-to-analog converter (DAC), a comparator, and a successiveapproximation register. The SAR ADC works based on the binary-search algorithm.
First, the input voltage is sampled. Then the conversion starts with an approximation
of the most-significant-bit (MSB); the comparator compares the input voltage with
half of the reference voltage; the SAR control logic stores the comparison result
and simultaneously generates the next approximation; the DAC converts the digital
information sent by the SAR to a voltage; based on the DAC output, the comparator
does the comparison again. The conversion continues until the least-significantbit (LSB) is decided. For an N-bit SAR ADC it usually takes at least N clock cycles
to complete one conversion. Since there is only one comparator and no amplifiers
in the converter, the SAR ADC is highly power-efficient [9]. Moreover, owing to its
dynamic nature, the SAR ADC is also amenable to technology scaling [3].
VIN
VREF
Sample/Hold
DAC
SAR Control Logic
DOUT
Figure 1.4: A basic SAR ADC.
The oversampling ADC is referred to Σ∆ ADC or ∆Σ ADC. Fig. 1.5 shows
the topology of a basic first-order Σ∆ ADC. An integrator and a comparator are
in the forward path. A 1-bit DAC in the feedback path provides ±VREF to the
adder input based on the comparator output. The output of the modulator, VOU T ,
consists of a quantized value of the input signal delayed by one sample period, plus a
differencing of the quantization error between the present and previous values [10].
Hence, the transfer function from VIN to VOU T follows that of a low-pass filter.
While, the transfer function of the quantization noise follows that of a high-pass filter,
thereby pushing the noise out of the signal bandwidth. The modulator is succeeded
with a low-pass filter (LPF) which removes the out-of-band quantization noise and
downsamples the signal. The oversampling feature of Σ∆ modulation eases the
anti-aliasing requirements. In addition, the noise shaping characteristic makes Σ∆
ADC dominate in high-resolution regime [11][12].
Nonetheless, among the designs plotted in Fig. 1.3, SAR ADCs consume the lowest power in medium-resolution and low-speed regime. The ADC designs presented
“lic˙thesis” — 2012/8/1 — 12:14 — page 5 — #21
1.3 Design Challenges and Strategies
VIN
5
VOUT
VERR
Digital
LPF
DOUT
VFB
1-bit
DAC
Figure 1.5: A basic first-order Σ∆ ADC.
in this thesis will utilize the SAR architecture. Ultra-low-power design challenges,
strategies, as well as circuit techniques of SAR architecture will be addressed in the
thesis.
1.3
Design Challenges and Strategies
As mentioned previously, conversion of the low frequency bioelectric signals does not
require high speed, but ultra-low-power operation (e.g. in nW range). This combined
with the required conversion accuracy makes the design of such ADCs a major
challenge. So far, most of the research on ADCs has been focused on medium- and
high-speed applications, while efficient design methodologies and circuit techniques
for low-speed and ultra-low-power ADCs have not been explored in depth.
Trading speed for lower power consumption at such slow sampling rate is not a
straightforward task. The major challenge is how to efficiently reduce the unnecessary
speed and bandwidth for ultra-low-power operation using inherently fast devices in
advanced CMOS technologies. Moreover, the leakage current degrades the sampling
accuracy during the long conversion time, and the leakage power consumption contributes to a significant portion of the total power consumption. As an example, Fig. 1.6
shows the average power consumption of an inverter as a function of its switching
frequency. The power consumption was simulated at two different supplies (1.0 V
and 0.4 V) over two different sizes (Wmin /Lmin and Wmin /2Lmin ). It can be seen
that the leakage power at 1-10 kHz can constitute more than 50% (50% at 10 kHz) of
the total power.
Considering the above discussion and the fact that every nano-watt counts for
such ADCs, the main key to achieve the ultra-low-power operation turns out to be the
maximal simplicity in the ADC architecture and low transistor count. This essentially
means that we avoid ADC techniques with additional complexity and circuit overhead,
which are useful for higher sampling rates. Digital error correction [13][14][15] has
been frequently used in high-speed ADCs, where capacitor redundancy is utilized
to meet the linearity requirement without degrading the speed. However, the circuit
overhead required for the digital post-processing leads to additional switching and
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Introduction
Average Power Consumption [ pW ]
6
3
10
VDD = 1.0V, W/L = 0.15µ/0.13µ
V
V
V
DD
= 1.0V, W/L = 0.15µ/0.26µ
DD
= 0.4V, W/L = 0.15µ/0.13µ
DD
= 0.4V, W/L = 0.15µ/0.26µ
2
10
Pleak /P total @10kHz = 53 %
1
10 2
10
3
4
10
10
Frequency [ Hz ]
5
10
Figure 1.6: Simulated average power consumption versus switching frequency of an inverter with
a fan-out of four in 0.13-µm CMOS process.
leakage power consumption. On-chip digital calibration [16][17] serves as an alternative solution without large amount of digital post-processing, but it requires additional
calibrating capacitor arrays and registers. Besides, to ensure the calibration efficiency,
the comparator offset should be removed prior to linearity calibration.
Taking advantage of the low speed, the proposed ADCs utilize matched capacitive
DACs, being sized to achieve the targeted conversion accuracy without digital error
correction or calibration, thus eliminating additional devices and significant leakage
currents. Moreover, the matched capacitive DACs use switching schemes that allow
full-range input sampling without additional voltage sources. The two designed SAR
ADCs utilized a top-plate sampling scheme and a bottom-plate sampling scheme,
which will be described in Chapter 4 and Chapter 5, respectively. Compared to the
energy-efficient switching schemes [9][18][19], the employed approaches introduce
less overhead in the SAR control logic [9][19] and avoid additional bias voltages in
the comparator [18].
To further reduce the power consumption, lowering the supply voltage was employed in both ADCs. The first ADC in 0.13 µm process utilized a dual-supply
voltage scheme which allows the SAR logic to operate at 0.4 V, reducing the overall
power consumption of the ADC by 15% without any loss in performance. In dualsupply mode (1.0 V for analog and 0.4 V for digital), the ADC consumes 53 nW
at a sampling rate of 1 kS/s and achieves the effective-number-of-bit (ENOB) of
9.1 bit. The second ADC took advantage of the availability of standard- and high-VT
devices in 65 nm process. The utilized multi-VT design allowed the ADC to achieve
9.1-ENOB and consume 3-nW power consumption with a single supply voltage of
0.7 V, thereby reducing both the switching and leakage power consumption. Our
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1.4 Thesis Organization
7
measurement results (in Sec. 5.4) show that the ADC can operate down to a supply
voltage of 0.6 V, achieving an optimal energy efficiency of 4.5 fJ/conversion-step with
8.8 ENOB at 1 kS/s.
1.4
Thesis Organization
This thesis outlines the study and designs of ultra-low-power SAR ADCs and is a
result of the research performed at the Devision of Electronic Devices, Department
of Electrical Engineering, Linköping University between April 2009 and June 2012.
The research during this period has resulted in the following publications:
• Dai Zhang and Atila Alvandpour, ”A 3-nW 9.1-ENOB SAR ADC at 0.7 V and
1 kS/s”, accepted for publication in proceedings of the European Solid-State
Circuit Conference (ESSCIRC), Bordeaux, France, September 2012 [20].
• Dai Zhang, Ameya Bhide, and Atila Alvandpour, ”A 53-nW 9.1-ENOB 1-kS/s
SAR ADC in 0.13-µm CMOS for Medical Implant Devices”, in IEEE Journal
of Solid-State Circuits, vol.47, no.7, pp.1585-1593, July, 2012 [21].
• Dai Zhang, Ameya Bhide, and Atila Alvandpour, ”A 53-nW 9.12-ENOB
1-kS/s SAR ADC in 0.13-µm CMOS for Medical Implant Devices”, in proceedings of the European Solid-State Circuit Conference (ESSCIRC), pp.467-470,
Helsinki, Finland, September 2011 [22].
• Dai Zhang, Christer Svensson, and Atila Alvandpour, ”Power consumption
bounds for SAR ADCs”, in proceedings of the European Conference on Circuit Theory and Design (ECCTD), pp.556-559, Linköping, Sweden, August
2011 [23].
• Dai Zhang, Ameya Bhide, and Atila Alvandpour, ”Design of CMOS sampling
switch for ultra-low power ADCs in biomedical applications”, in proceedings
of the Norchip Conference, pp.1-4, Tempera, Finland, November 2010 [24].
The rest of this thesis is organized as follows. Chapter 2 discusses the precision
considerations of SAR ADC blocks. The analysis of power consumption bounds for
SAR ADCs is described in Chapter 3. In Chapter 4 and Chapter 5, two SAR ADC
designs are presented: a 53-nW 9.1-ENOB SAR ADC in 0.13 µm CMOS and a 3-nW
9.1-ENOB SAR ADC in 65 nm CMOS. Finally, the thesis is concluded in Chapter 6.
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8
Introduction
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Chapter 2
SAR ADC Precision
Considerations
During the conversion from an analog signal to a digital word, three major tasks are
performed by the ADC: sampling, quantization, and comparison. For a SAR ADC,
the three tasks are correspondingly executed in the sampling circuit, the capacitive
DAC, and the comparator. In this chapter, we will analyze the design considerations
of each block.
2.1
Sampling Circuit
A basic sampling circuit consists of a switch and a capacitor, shown in Fig. 2.1(a).
When the switch is on, the input voltage is connected to the top-plate of the sampling
capacitor. When the switch is off, the top-plate node of the capacitor is isolated, and
the capacitor holds the sampled voltage value. Generally, the switch can be implemented by PMOS, NMOS, or CMOS devices. Fig. 2.1(b) shows the on-resistance versus
the input voltage for the three types of switch. Compared with NMOS and PMOS,
the CMOS switch has the lowest on-resistance and allows full-range input sampling.
The general design considerations of the sampling circuit are: thermal noise,
aperture error, switch-induced error, track bandwidth, and voltage droop.
2.1.1
Thermal Noise
The thermal noise, introduced by the on-resistance of the switch, is given by kT /CS ,
where k is the Boltzmann constant, T is the absolute temperature, and CS is the
sampling capacitor. Since the thermal noise appears as random errors which can’t be
calibrated, it will degrade the signal-to-noise ratio (SNR).
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10
SAR ADC Precision Considerations
RON
NMOS
PMOS
Vin
Vout
CMOS
CS
VTHP
(a)
VDD-VTHN Vin
(b)
Figure 2.1: Sampling circuit:(a) basic circuit (b) switch on-resistance versus input voltage.
As we know, the quantization noise sets a fundamental limit on the SNR of the
ADC. If we consider an N -bit ADC with a full-scale range voltage of VF S , the
quantization noise is given by
Vq2 =
VF2S
12 · 22N
(2.1)
Assuming that the thermal noise is designed to be equal to the quantization noise,
the total noise power will be increased by a factor of 2, thus decreasing the SNR by
3 dB. Then, the minimum value of sampling capacitor CS can be calculated by
CS = 12kT
22N
VF2S
(2.2)
To get some feeling for the value of the sampling capacitor, Table 2.1 lists a set of
capacitance versus ADC resolution for 1-V VF S .
Table 2.1: Required Minimum Capacitance Versus Resolution based on Eq. (2.2)
N
8
9
10
11
12
CS
3
13
52
208
833
unit
fF
fF
fF
fF
fF
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2.1 Sampling Circuit
11
Aperture
Uncertainty
TA
EA
Aperture
Error
Sampling
V0
Hold
O
t
-V0
Figure 2.2: Aperture error.
2.1.2
Aperture Error
Aperture error is caused by the uncertainties in the time from sample mode to hold
mode, as shown in Fig. 2.4. This variation is mainly due to the noise on the sampling
clock. The aperture error voltage, denoted as EA , depends on the slew rate of the
input signal and the aperture uncertainty, denoted as TA . For a sine wave input as
shown, the maximum slew rate occurs at the zero crossing point and is given by
dV
|max = 2πfIN V0
(2.3)
dt
where fIN is the input frequency and V0 is the input amplitude. To ensure the aperture
error to be less than 1/2 LSB at the point of maximum slew rate, for N -bit converter
we have
1
2V0
LSB = N +1
2
2
Hence the maximum input frequency is given by
2πfIN V0 TA <
fIN @M AX =
1
π×
2N +1
× TA
(2.4)
(2.5)
Equation (2.5) can also be applied to the context of sampling time jitter. For
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12
SAR ADC Precision Considerations
instance, when a 10-bit converter suffers a jitter of 1 ps, the input frequency should
be less than 150 MHz.
2.1.3
Switch-Induced Error
CGS
Vin
(1-k)Qch
CGD
Vout
kQch
Charge injection
Clock feedthrough
CS
Figure 2.3: Sources of switch-induced error of sampling circuit.
Charge injection and clock feedthrough, shown in Fig. 2.3, collectively known as the
switch-induced error, are the major error sources caused at the moment the switch
turns off. Charge injection introduces error to the sampled voltage by depositing
part of the charge from the conduction channel of the transistor onto the sampling
capacitor. Clock feedthrough affects the sampled voltage by capacitance coupling
during the transition of the sample signal. The switch-induced error voltage for both
NMOS and PMOS can be approximated as [25]
kWN LN COX (VDD − VT HN − VIN )
CGD,N
−
VDD
CS
CS + CGD,N
kWP LP COX (VIN − |VT HP |)
CGD,P
∆Ve,P =
+
VDD
CS
CS + CGD,P
∆Ve,N = −
(2.6)
(2.7)
where k is the fraction of charge injected on the output node, COX is the gate-oxide
capacitor, VT HN and VT HP are the threshold voltages, and CGD,N and CGD,P are
the gate-drain overlap capacitance of NMOS and PMOS, respectively. In Eq. (2.6)
for NMOS (respectively PMOS), the first part of the right-half side represents the
charge injection error, which varies with the input signal in a linear fashion if body
effect is neglected. The second part represents the clock feedthrough error, which is
input-independent and can be taken as an offset error.
Since charge-injection error voltage is input-dependent, which will introduce
conversion linearity error, it should be alleviated. A straightforward way is to increase
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2.1 Sampling Circuit
13
the sampling capacitance with a sacrifice of speed. Alternative techniques, such as
bottom-plate sampling, can also be used to reduce the error.
2.1.4
Track Bandwidth
The sampling circuit forms a low-pass RC network, which determines the track
bandwidth
f3dB =
1
2πRON CS
(2.8)
where RON is the on-resistance of the switch. Based on its exponential response, the
time budget for the sampled voltage to settle with an error less than 1/2 LSB for N -bit
resolution can be derived from
1
(2.9)
2N +1
Further assuming that a half-period sampling-clock is used as the time budget, it
requires
ln2 × (N + 1)
f3dB >
fS
(2.10)
π
where fS is the sampling frequency.
The switch resistance is strongly signal-dependent, thus leading to varying track
bandwidth. For mid-rail input voltage, the switch resistance goes to the maximum
value, which determines the minimum track bandwidth. Under this circumstance,
Eq. (2.10) should be satisfied. Otherwise, the limited bandwidth will introduce
nonlinear errors to the sampling.
e
2.1.5
t
ON CS
−R
<
Voltage Droop
Voltage droop introduced by the leakage current of the switch becomes a critical
error source as the sampling rate goes low. The subthreshold leakage current of the
transistor is the dominant leakage contributor to the switch, which is expressed as [26]
IDS = µ0 COX
VGS −VT H
V
W
− DS
× (1 − e VT )
(m − 1)VT2 × e mVT
L
(2.11)
where m is the subthreshold swing coefficient, and VT is the thermal voltage. Eq. (2.11)
indicates that the leakage current shows nonlinear dependence on the input-output
voltage difference across the switch, thereby introducing harmonic distortions.
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14
2.2
SAR ADC Precision Considerations
Capacitive DAC
Once the input voltage is sampled, the ADC maps the input value to a corresponding
digital form based on a set of reference voltages. This process is called quantization.
In a SAR ADC, a capacitive DAC is commonly used to generate wighted reference
voltages. Compared to a resistive DAC, the capacitor array is more easily fabricated
with less mismatch errors, and it is also more power-efficient.
In this section, we will discuss the mismatch errors of capacitive DACs with a
focus on two commonly-employed architectures: single binary-weighted array and
split binary-weighted array.
2.2.1
Single Binary-Weighted Capacitive Array
VDAC
VRST
2N-1CU 2N-2CU
2CU
CU
DN-1
D1
D0
DN-2
CU
VREF
GND
Figure 2.4: A single binary-weighted capacitive DAC.
Figure 2.4 shows a single binary-weighted capacitive DAC. It mainly works at two
modes. During the reset mode, all the bottom-plate nodes are reset to ground and the
top-plate node is connected to a reset voltage, allowing the capacitors to discharge.
When comes to the conversion mode, the digital codes determine the switch status,
generating a corresponding reference voltage.
The unit capacitor, denoted as CU , should be kept as small as possible for power
saving. In practice, it is usually determined by the thermal noise and capacitor
mismatch. In Sec. 2.1.1, we have discussed the thermal noise. Here, we will focus on
the mismatch.
Generally, the unit capacitor is modeled with a nominal value of Cu and a standard
deviation of σu . For a binary-weighted capacitor array, the worst-case standard
deviation of differential nonlinearity (DNL) and integral nonlinearity (INL) occur at
the MSB code transition due to the accumulation of the capacitor mismatch. Following
the analysis in [27], they can be expressed in terms of LSB as
σDN L,M AX =
p
2N − 1
σu
LSB
Cu
(2.12)
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2.2 Capacitive DAC
15
√
σIN L,M AX =
2N −1
σu
LSB
Cu
(2.13)
Comparing Eq. (2.12) with Eq. (2.13), the derived worst-case standard deviation
of DNL is larger than that of INL. Therefore, Eq. (2.12) is chosen to be a reference in
the following analysis. For a typical metal-insulator-metal (MIM) capacitor, it has
σ(
∆C
Kσ
)= √
C
A
C = KC · A
(2.14)
(2.15)
where σ(∆C/C) is the standard deviation of capacitor mismatch, Kσ is the matching
coefficient, A is the capacitor area, and KC is the capacitor density parameter.
√ The standard deviation of a single capacitor to the nominal value is by factor
2 smaller √
than that of the difference between two capacitors. Thus, σ(∆C/C)
divided by 2 is equal to σu /CU . For high yield, it is necessary to maintain
3σDN L,M AX < 1/2LSB. Combining the earlier equations, we obtain a lower
bounds for the mismatch-limited unit capacitor
(2.16)
CU = 18 · (2N − 1) · Kσ2 · KC
Assuming a MIM capacitor in certain technology has a density of 2 fF/µm2 and a
matching of 1% µm. It leads to a minimum unit capacitance of 4 fF.
So far, the discussion is for the single-ended architecture. For the differential
configuration, the unit capacitance can be reduced by half while still satisfying the
mismatch requirement.
√ This is because the differential mode doubles the signal range
but only increases 2 times of the error voltage introduced by the mismatch.
2.2.2
Split Binary-Weighted Capacitive Array
CB
VDAC
2M-1CU
2CU
CU
2S-1CU
2CU
CU
DS-1
D1
D0
Reset
CU
Reset
DN-1
DN-M+1 DN-M
VREF
GND
M-bit Main-DAC
S-bit Sub-DAC
Figure 2.5: A split binary-weighted capacitive DAC.
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16
SAR ADC Precision Considerations
A split binary-weighted capacitive DAC, shown in Fig. 2.5, is commonly used to
reduce the total size of the capacitive array. It consists of an M -bit main-DAC and
an S-bit sub-DAC, where M + S = N . Via a bridge capacitor, denoted as CB in
Fig. 2.5, the sub-DAC interpolates between transition voltages generated by the mainDAC. The bridge capacitance is commonly chosen to be the ratio of total sub-DAC
capacitance and total main-DAC capacitance
CB =
2S
· CU
2M − 1
(2.17)
CU
VDAC
2M-1CU
2CU
CU
2S-1CU
2CU
CU
Reset
Reset
DN-1
DN-M+1 DN-M
DS-1
D1
D0
VREF
GND
M-bit Main-DAC
S-bit Sub-DAC
Figure 2.6: A modified split binary-weighted capacitive DAC to avoid fractional value of bridge
capacitor.
Assuming M and S are both set to 5 to achieve 10-bit resolution, the bridge
capacitor is calculated to be 32/31CU . The fractional value of CB introduces layout
difficulties and additional mismatch. Hence, to avoid the fractional value a modified
split-DAC is employed, shown in Fig. 2.6, where the dummy capacitor at sub-DAC
part is removed and the bridge capacitor is equal to the unit capacitor. This modification will introduce gain error to the conversion, which will be discussed in the
following section.
2.2.2.1
Gain Error
First, we consider the case, shown in Fig. 2.7, where the entire sub-DAC is connected
to ground and several capacitors in the main-DAC is connected to VREF . The voltage
at VM is
CVMREF
VREF
(2M − 1)CU + (1 − 2−S )CU
CM
= M V REF
VREF
2 (1 − 2−N )CU
VM =
(2.18)
(2.19)
where CVMREF denotes the total capacitors connected to VREF in the main-DAC.
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2.2 Capacitive DAC
17
CS=(1-2-S)CU
CU
VM
VDAC
2M-1CU
DN-1
2CU
CU
Sub-DAC
DN-M+1 DN-M
VREF
GND
Figure 2.7: A simplified DAC circuit with the whole sub-DAC connected to ground.
Secondly, we consider the case, shown in Fig. 2.8, where the entire main-DAC is
connected to ground and several capacitors in the sub-DAC is connected to VREF .
The voltage at VS is
CVS REF
VREF
(2S − 1)CU + (1 − 2−M )CU
CVS REF
= S
VREF
2 (1 − 2−N )CU
(2.20)
VS =
(2.21)
where CVS REF denotes the total capacitors connected to VREF in the sub-DAC.
CM=(1-2-M)CU
VDAC
CU
V’M
Main-DAC
VS
2S-1CU
2CU
CU
DS-1
D1
D0
VREF
GND
Figure 2.8: A simplified DAC circuit with the whole main-DAC connected to ground.
0
Thirdly, we calculate the voltage at the top-plate of main-DAC, denoted as VM
CU
VS
(2M − 1)CU + CU
1
= M VS
2
0
VM
=
(2.22)
(2.23)
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18
SAR ADC Precision Considerations
Finally, we can derive the voltage at the DAC output, denoted as VDAC , it is
0
VDAC = VM + VM
=
CVMREF
M
2 (1 − 2−N )C
(2.24)
VREF +
U
CVS REF
1
M
S
2 2 (1 − 2−N )C
VREF
(2.25)
U
VREF CVMREF
CS
(
+ V REF
)
−N
M
1−2
2
2N
VREF 2S CVMREF + CVS REF
=
1 − 2−N
2N
=
(2.26)
(2.27)
Equation (2.27) shows a gain factor of 1/(1 − 2−N ). If necessary, the gain error
introduced by the modified architecture can be calibrated in the digital domain.
2.2.2.2
Mismatch Error
Since the effect of the capacitor mismatch in the sub-DAC is reduced by 1/2M , as
indicated in Eq. (2.23), the main-DAC dominates the total mismatch performance.
Note that here we assume M is relatively large, which is commonly chosen to be
equal to or larger than N/2 in practice.
Based on Eq. (2.12), the worst-case standard deviation of DNL for M -bit subDAC is
p
σu
σDN L,M AX = 2M − 1 LSB 0
(2.28)
Cu
where LSB 0 is equal to VREF /2M . Considering the mismatch error should be less
than 1/2LSB, where the LSB is equal to VREF /2N , we further write
p
σu VREF
1 VREF
2M − 1
<
M
Cu 2
2 2N
σu
1
√
<
Cu
2N −M +1 2M − 1
(2.29)
(2.30)
Following a similar method which derives the lower bounds of mismatch-limited
unit capacitor for a single binary-weighted capacitive array in Sec. 2.2.1, we write the
lower bounds of mismatch-limited unit capacitor for the modified split architecture
CU = 18 · (2M − 1) · 22(N −M ) · Kσ2 · KC
(2.31)
If we choose M to be equal to N , which means the split architecture returns to a
single binary-weighted one, we will find Eq. (2.31) matches Eq. (2.16).
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2.3 Comparator
19
It will be informative to do a plot based on Eq. (2.31). Assuming 10-bit resolution, Kσ = 1%µm and KC = 1f F/µm2 , the mismatch-limited minimum unit
capacitance together with the corresponding total array capacitance versus main-DAC
resolution are plotted in Fig. 2.9.
Capacitance in fF
Minimum unit capacitance vs. Main−DAC resolution
60
40
20
0
5
6
7
8
9
10
Capacitance in pF
Total DAC capacitance vs. Main−DAC resolution
4
3
2
1
5
6
7
8
9
Main−DAC resolution [bit]
10
Figure 2.9: Unit capacitance and total array capacitance versus main-DAC resolution.
As shown, the linearity requirements impose much larger unit capacitance and
total array capacitance to the split architecture compared to the single architecture.
However, the actual implementation of the minimum capacitor could be limited by the
technology design-kit, denoted as CP RE . For a single architecture, a unit capacitance
of CP RE might be much larger than necessary to meet the linearity requirements,
resulting in considerably large array capacitance. In this case, a split architecture is
preferred, which requires larger unit capacitor but still arrives at smaller total array
capacitance.
2.3
Comparator
The comparator is commonly composed of a pre-amplifier and a latch. However,
recent state-of-arts in SAR ADC designs show a trend of directly using dynamic latch
comparator to achieve moderate resolution with high power-efficiency.
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20
SAR ADC Precision Considerations
In this section, we focus on one type of dynamic latch comparators, shown in
Fig. 2.10. It works at two phases: reset and regeneration phases. The differential
outputs are initially pre-charged (reset) to the supply voltage. During the regeneration
phase, the outputs discharge toward ground at unequal speed depending on the input
voltages. When these nodes are low enough, one of the cross-coupled inverters is
activated and initiates the regeneration. Finally, one of the outputs is pulled towards
ground, and another one is pulled up to the supply.
VDD
M5
M6
VON
VOP
C1
C2
M3
VIP
M4
M1
Clk
M2
VIN
M7
Figure 2.10: A dynamic latch comparator.
The general design considerations of the comparator, such as offset, noise, and
metastability, will be discussed in the following sections.
2.3.1
Offset
There are mainly two types of offset voltages in the comparator: 1) offset voltage from
the mismatch in transistor current factors and in threshold voltages due to process
variation; 2) offset voltage from the mismatch in the parasitic capacitors.
It is well known that increasing the transistor size will reduce the first-type offset
voltage. Here, we are more interested in the second-type offset voltage which is
caused by the load capacitor mismatch. It has been demonstrated that a capacitive
imbalance of 1 fF at the output of a simplified latch model (a cross-coupled inverter
pair) can lead to offsets of several tens of millivolts [28]. In [28], it also shows that
the offset voltage is more affected by the relative capacitance mismatch (∆C12 /C2 )
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2.3 Comparator
21
than the absolute capacitance mismatch (∆C12 ). A possible strategy to minimize the
offset voltage is sizing up the cross-coupled inverter pair so that the relative mismatch
is reduced. Moreover, if the requirement of comparator speed can be easily met,
additional capacitors with good matching properties can be added to the output nodes
to further reduce the relative mismatch.
2.3.2
Thermal Noise
Thermal noise is one of the critical limiting factors to the comparison accuracy.
Unlike operational amplifiers whose operation regions of all the transistors are welldefined, the dynamic latch comparators possess time-varying nature, thus making
the noise analysis more difficult. In [29], the authors performed noise analysis based
on stochastic differential equations. In [30], the authors estimated the comparator
decision error probability based on linear, periodically time-varying systems. They
both show that the noise terms have the usual kT /C-form with the addition of some
other factors. Here we refer to the result used in [31], where the input-referred thermal
noise of the latch comparator is approximated to be
2
VnC
=κ
kT γ
CC
(2.32)
where κ is an architecture-dependent parameter, γ is a thermal-noise factor, and CC
is the load capacitance at the bandwidth-limiting node of the comparator.
2.3.3
Flicker Noise
Apart from thermal noise, flicker noise is another important noise source. We start
the estimation by referring a known result of flicker noise on the transistor gate [32],
which is given by
2
VnF
=
Kf Bn
ln
Cg fL
(2.33)
where Kf is the noise coefficient, Cg is the gate capacitance, Bn is the noise bandwidth, and fL is a lower frequency limit. Bn and fL can be further expressed with
gm
4CC
1
fL =
tsys
Bn =
(2.34)
(2.35)
where gm is the transistor transconductance, CC is the parasitic capacitance at the
output, and tsys is the system lifetime. gm can be further expressed using the cut-off
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22
SAR ADC Precision Considerations
frequency fT
gm = 2πCg fT
(2.36)
Assume Cg is one-fourth of CC , considering that CC is at least contributed by two
diffusion capacitors and two gate capacitors of the cross-coupled inverter. Combining
all the above equations, we rewrite Eq. (2.33) as
2
VnF
=
4Kf
× ln(2πfT tsys )
CC
(2.37)
We assume Kf is on the order of 10−25 V 2 F [33], fT is around 100 GHz, and
tsys is about 10 years. Hence, the flicker noise can be approximated to
2
VnF
≈ 1.8e−23 ·
1
CC
(2.38)
Moving to the approximation of thermal noise, we evaluate Eq. (2.32) with
assumption of κ = 1 and γ = 1 and obtain the value of thermal noise as
2
VnC
≈ 4.1e−21 ·
1
CC
(2.39)
Comparing Eq. (2.38) to Eq. (2.39), the contribution of flicker noise is much less
significant than that of thermal noise.
2.3.4
Metastability
Metastability is the phenomenon where a bistable element requires an indeterminate
amount of time to generate a valid output [34]. The metastability in a latch comparator
occurs when the differential input signal is so small that the latch does not have enough
time to produce a well-defined logic levels, which might be interpreted differently by
succeeding gates, leading to substantial conversion error. In this section, we calculate
the probability of metastability taking place in the dynamic latch comparator.
During regeneration, the differential output voltage follows this equation
VO,dif f = Ak |VI,dif f |et/τ
(2.40)
where VO,dif f is the output voltage difference, Ak acts as a gain factor from the inputs
to the initial imbalance of the inverter pair, VI,dif f is the input voltage difference, and
τ is the regeneration time constant of the comparator, given by CC /gm,IN V . gm,IN V
is the total transconductance of the inverter.
Assume that the acceptable logic level (trip point) for VO,dif f is VDD /2, otherwise, metastable outputs will be caused. Based on the allowable comparator decision
time, denoted as Tmax , the minimum required input voltage difference can be ex-
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2.3 Comparator
23
pressed as
VI,dif f @M IN =
1 VDD −Tmax /τ
e
Ak 2
(2.41)
Further assume that the input signal follows a uniform distribution across a voltage
range VM . The probability of metastable error pM is equal to the probability when
the input voltage difference is less than VI,dif f @M IN , we have
pM = P (|VI,dif f | < VI,dif f @M IN )
VI,dif f @M IN
=2×
VM
1 VDD −Tmax /τ
=
e
Ak V M
(2.42)
(2.43)
(2.44)
In [35], the signal-to-metastability-error ratio (SMR) of SAR ADC was calculated
to quantify the effect of the metastability. The metastability error power is defined by
the product of the calculated probability and the power of output error voltage caused
by metastable state. It shows that errors in the first bit contribute most to the output
noise power [35].
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24
SAR ADC Precision Considerations
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Chapter 3
SAR ADC Power Consumption
Bounds
As aforementioned, SAR ADCs are particularly successful in achieving low power
consumption. In order to further reduce the power consumption of SAR ADCs, a
deeper understanding of its lower bounds is essential. The power consumption bounds
of SAR ADCs was discussed in [36]. However, we are less conservative than the
authors in [36], thus arriving at comparatively lower bounds.
As we are looking for the lower power consumption bounds, we have limited our
study to power-efficient SAR ADC architectures, such as a charge-redistribution SAR
ADC [37]. As shown in Fig. 3.1, the ADC consists of a binary-weighted capacitive
array, a dynamic latch comparator, and a SAR control logic. Since most of the SAR
ADCs in the literature don’t have a driver at the input, the sampling power, previously
discussed in [31], will not be included in the following analysis.
2N-1CU
2N-2CU
2CU CU
CU
SAR
Control Logic
VIN
VREF
DOUT
Figure 3.1: Charge-redistribution SAR ADC.
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26
3.1
SAR ADC Power Consumption Bounds
Power Consumption Estimation of DAC
Power consumption of the DAC depends on the unit capacitance, the input signal
swing, and the employed switching approach. For a uniformly distributed input
signal between ground and the reference voltage, the average switching power per
conversion for N -bit can be derived as [18]
PDAC = ζ
N
X
2
2N +1−2i (2i − 1)CU VREF
fS
(3.1)
i=1
where VREF is the reference voltage, fS is the sampling frequency, and ζ is a
normalized switching scheme-dependent parameter. For conventional switching
approach [37], ζ = 1.
The unit capacitor should be kept as small as possible for power saving. In practice,
it is usually determined by thermal noise and capacitor mismatch. In Sec. 2.1.1, we
derived the minimum sampling capacitance limited by thermal noise. Considering
the DAC realizes the sample-and-hold function, Eq. (2.1) can be used to calculate the
noise-limited minimum DAC array capacitance. Further deviding the calculated value
by 2N , we derive the noise-limited minimum CU
CU,n = 12kT
2N
VF2S
(3.2)
In Sec. 2.2.1, we derived the mismatch-limited minimum CU . For ease of reference, we copy Eq. (2.16) here
CU,m = 18 · (2N − 1) · Kσ2 · KC
(3.3)
Apart from the above two limiting factors, the process will also set a lower limit
to the capacitance so that the total array capacitance at least need to be equal to
the parasitic capacitance at the DAC output, which results in a 50% attenuation of
the output voltage. The parasitic capacitance include both the gate capacitance of
the comparator input and the parasitic capacitance of interconnection. We further
assume it is comparable to the input capacitance of a minimum-sized inverter, which
is denoted as Cmin . Regarding the value of Cmin , we follow the same assumption
in [31], where Cmin is equal to 1 fF for 65-90 nm CMOS processes.
Finally, CU in Eq. (3.1) can be replaced with
CC = max(CU,n , CU,m , Cmin )
(3.4)
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3.2 Power Consumption Estimation of Comparator
3.2
27
Power Consumption Estimation of Comparator
We estimate the comparator power based on the dynamic latch comparator due to
its high power efficiency. The schematic of the comparator is shown in Fig. 2.10. A
typical signal transient behavior of the differential outputs and the supply current of
the comparator is visualized in Fig. 3.2.
1
Regeneration Phase
Reset Phase
Curent [ A]
Voltage [V]
50
VOP
VON
0.5
IVDD
0
treg
0
2
4
6
Time [ns]
8
10
Figure 3.2: Typical signal transient behavior including the differential outputs and the supply
current. Note that there is no static supply current.
To compute the charge during the regeneration mode, we denote that there is a
current, ID , flowing only during the regeneration time, treg . Hence, the total regenerative charge can be expressed as 2ID treg . treg can be calculated from Eq. (2.40). For
ease of reference, we copy Eq. (2.40) here
VO,dif f = Ak VI,dif f et/τ
(3.5)
where τ = CC /gm,IN V .
Further defining a parameter Vef f , we can write gm,IN V = ID /Vef f [31]. Assuming that the regeneration is finished when VO,dif f becomes VDD . It results in the
following expression of treg
treg =
Vef f CC
VDD
ln
ID
Ak VI,dif f
(3.6)
Using Eq. (3.6), we can rewrite the expression of the regenerative charge for one
conversion step as
VDD
QC,reg−s = 2Vef f CC ln
(3.7)
Ak VI,dif f
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28
SAR ADC Power Consumption Bounds
Since an N -bit SAR ADC needs N steps to complete one conversion, the input
voltage difference of the comparator for the ith-step can be expressed as
VI,dif f (i) = | − VIN + DN −1
VREF
VREF
|, 1 ≤ i ≤ N
+ ··· +
2
2i
(3.8)
where VIN is the input voltage, DN −1 is the decision of MSB.
We assume that VIN is evenly distributed between 0 and VREF . This further
indicates that VI,dif f is also evenly distributed between 0 and a binary-weighted
value of VREF , which is denoted as Vm . Then, the average charge for one step can be
expressed by
1
Vm
Vm
Z
QC,reg−s dVI,dif f = 2Vef f CC (ln
0
VDD
+ 1)
Ak Vm
(3.9)
Hence, the charge of a complete conversion can be derived from the sum of
N -steps’ charge
QC,reg =
N
X
(2Vef f CC (ln
k=1
= 2Vef f CC (N ln
VDD
+ 1))
Ak (VREF /2k )
VDD
N (N + 1)
+
ln2 + N )
Ak VREF
2
(3.10)
(3.11)
Moving to the reset charge, we assume that it is mainly consumed by the capacitive
load at the comparator output. Consequently, the total power consumption of the
comparator is equal to the reset charge at the clock frequency and the regenerative
charge at the sampling frequency
PC = N fS VDD QC,rst + fS VDD QC,reg
(3.12)
We rewrite Eq. (3.12) by replacing QC,rst with CC VDD and QC,reg with Eq. (3.11).
Thus,
VDD
N (N + 1)
ln2 + N )
+
Ak VREF
2
(3.13)
Since the comparator offset introduces ADC offset rather than nonlinearities, the
fundamental limitation on the achievable comparator resolution is noise. Based on
the analysis presented in Sec. 2.3, we find that flicker noise is much smaller than
thermal noise. Consequently, the comparator is constrained by thermal noise, which
is derived by Eq. (2.32). Equalizing the thermal noise to the quantization noise of an
2
PCOM P = N fS CC VDD
+ 2fS VDD Vef f CC (N ln
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3.3 Power Consumption Estimation of SAR Logic
29
N -bit converter gives a minimum load capacitance
CC,n = 12kT γκ
22N
VF2S
(3.14)
where κ = 1 and γ = 1 [31] is used in this analysis.
Considering that the effect of the process also set a lower limit to the capacitance
through minimum feature size. We therefore include Cmin , the input capacitance of a
minimum-sized inverter. And CC in Eq. (3.13) can be replaced with
(3.15)
CC = max(CC,n , Cmin )
3.3
Power Consumption Estimation of SAR Logic
A straightforward way to build a SAR logic is to use 2 × N D-type Flip Flops (DFFs)
for N -bit resolution, as shown in Fig. 3.3. A typical transmission-gate DFF is
composed of 2 cross-coupled inverter pairs and 4 transmission gates. We therefore
assume that the capacitive load of one DFF is equivalent to that of 8 inverters. Hence,
the equivalent capacitive load of the SAR logic can be approximated to 16 × N
inverters in total.
CLK
D
COMP
Q
D
D
Q
DN
Q
D
D
Q
Q
D
D
Q
DN-1
D1
Q
D
Q
D0
Figure 3.3: A typical design of SAR digital logic.
Leakage power consumption could be significant for a circuit designed in a highleaky process. In this analysis, for simplicity we only consider the dynamic power
consumption. Assuming a total activity of the SAR logic to be α, and then we derive
the power consumption of the SAR logic as
2
PSAR = 16N 2 αfS Cmin VDD
(3.16)
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30
SAR ADC Power Consumption Bounds
Assume that one-fourth of the transistors in the SAR logic are clocked and the
activity of the rest is 0.2, we approximate α to be 0.4.
3.4
Power Consumption Estimation of a Complete
SAR ADC
Adding together Eq. (3.1), Eq. (3.13), and Eq. (3.16), the earlier derived equations of
block power consumption, we can express the total power consumption of a complete
SAR ADC
PADC = ζ
N
X
2
2N +1−2i (2i − 1)CU VREF
fS
i=1
2
+ N fS CC VDD
+ 2fS VDD Vef f CC (N ln
2
+ 16N 2 αfS Cmin VDD
N (N + 1)
VDD
ln2 + N )
+
Ak VREF
2
(3.17)
In Eq. (3.17), we have included many parameters. For ease of reference, the
following list summerizes the parameters used in this equation.
• ζ: normalized switching scheme-dependent parameter.
• N : resolution of the ADC.
• CU : DAC unit capacitance, where CU = max(CU,n , CU,m , Cmin ).
• CU,n : thermal-noise-limited DAC unit capacitance.
• CU,m : mismatch-limited DAC unit capacitance.
• Cmin : input capacitance of a minimum-sized inverter in a particular technology
node.
• VREF : reference voltage of the ADC.
• fS : sampling frequency of the ADC.
• CC : capacitive load of the comparator, where CC = max(CC,n , Cmin ).
• CC,n : thermal-noise-limited capacitive load of the comparator.
• VDD : supply voltage of the ADC.
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3.4 Power Consumption Estimation of a Complete SAR ADC
31
• Vef f : effective voltage, which is the ratio of drain current ID and transconductance gm . For classical long-channel transistors in strong inversion Vef f =
(VGS − VT )/2; for weak inversion Vef f = m · kT /q [38]; for modern shortchannel MOS transistors, transistors’ being often biased in the transition region
between weak and strong inversion makes both formulas useless [31]. In this
analysis, we have tried to approximate Vef f from simulation, which will be
discussed later.
• Ak : gain factor from the inputs to the initial imbalance of the inverter pair. In
this analysis, we have tried to approximate Ak from simulation, which will be
discussed later.
• α: switching activity of the SAR logic.
Approximation of Ak and Vef f
Equation. (3.7) can be further decomposed to
QC,reg−s = 2Vef f CC ln
VDD
− 2Vef f CC lnVI,dif f
Ak
(3.18)
The first term in the right-hand side of Eq. (3.18) turns out to be a constant offset,
and the second term is linear with the logarithm of input voltage difference. Since it
is not easy to analytically derive the value of Ak and Vef f due to the time-varying
nature of the comparator, we first simulated QC,reg−s under a set of VI,dif f , and
then extracted Ak and Vef f based on the simulation results via a least-squares fit.
Figure 3.4 gives an example of curve fitting based on simulated results.
16
Simulated
Least−squares fit
Simulated QC,reg−s [fC]
14
12
10
8
6
Ak = 1.3
4
Veff = 56 mV
−6
−5
−4
−3
−2
Logarithm of VI,diff [ln(V)]
−1
Figure 3.4: An extraction example of Ak and Vef f based on simulation.
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32
SAR ADC Power Consumption Bounds
We implemented a latch comparator with minimum transistor size in a 90-nm
CMOS process and a capacitive load of 20 fF. We obtained Ak = 1.3 and Vef f =
56mV based on the simulation results. Varying the common-mode voltage applied
to the comparator input, the value of Ak and Vef f will change, but they are almost
kept between 0.5 to 1.8 and 50 mV to 100 mV, respectively. The variations are fairly
independent of scaling and apply to typical CMOS technologies from 130 nm to
65 nm. In this analysis, we use Ak = 1.0 and Vef f = 75mV.
Figure 3.5 shows our analyzed P/fS of the SAR ADC together with its individual
blocks. Table 3.1 shows the parameter values used in the demonstration. We plot the
DAC power consumption limited by noise and mismatch, respectively. It is interesting
to note that the digital logic dominates the total power when the resolution is low.
However, for higher resolution, the total power is very close to the DAC power, if
mismatch is the limiting factor. When mismatching is not considered, the comparator
power dominates the total power.
Table 3.1: Parameter Values Used in Eq. (3.17)
ζ=1
VDD = 1V
Kσ = 1%µm
γ=1
α = 0.4
T = 300K
VREF = 1V
KC = 1f F/µm2
Vef f = 75mV
Cmin = 1f F
VF S = 1V
κ=1
Ak = 1
4
10
Total−mismatch
Total−noise
DAC−mismatch
DAC−noise
COMP
SAR
2
Power/fs [pJ]
10
0
10
−2
10
−4
10
4
6
8
10
ENOB [bit]
12
14
Figure 3.5: Predicted power consumption bounds for both noise-limited and mismatch-limited
SAR ADCs together with their individual components.
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3.5 Comparison to Experimental Data
3.5
33
Comparison to Experimental Data
The predicted power consumption bounds together with Nyquist SAR ADC survey
data from [8] is shown in Fig. 3.6. We note that several experimental points are very
close to our estimated power, indicating that our model describes reality well. The
power per conversion of the SAR ADC described in [9] is very close to our estimated
value. The ADC is indicated by a black circle in Fig. 3.6. This 8.75-ENOB 1-MS/s
ADC was designed in a 65 nm CMOS process without any digital error correction
circuit. The measured P/fS is 1.9 pJ. Our theoretical bounds for a mismatch-limited
8.75-ENOB converter is 1.1 pJ. The ADC achieves a close value compared to our
estimation by using: 1) a binary-weighted DAC with a total capacitance of 600 fF;
2) a step-wise charging for the three MSB capacitors with two intermediate steps,
which further reduces the DAC power; 3) a dynamic latch comparator without static
bias. With these considerations, we find a reasonable agreement between our bounds
and the experimental result in [9].
4
10
3
Power/fs [pJ]
10
2
10
1
10
0
10
Mismatch−limited SAR
Noise−limited SAR
−1
10
4
6
8
10
ENOB [bit]
12
14
Figure 3.6: Predicted power consumption bounds (solid line for mismatch-limited and dashed line
for noise-limited) together with Nyquist SAR ADC survey data.
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34
SAR ADC Power Consumption Bounds
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Chapter 4
A 53-nW 9.1-ENOB SAR ADC
in 0.13 µm CMOS Process
In this chapter, we will present a 53-nW 9.1-ENOB SAR ADC in 0.13 µm CMOS
process. To achieve the nano-watt range power consumption, an ultra-low power
design strategy has been utilized, imposing maximum simplicity on the ADC architecture, low transistor count and matched capacitive DAC with a switching scheme
which results in full-range sampling without switch bootstrapping and extra reset
voltage. Furthermore, a dual-supply voltage scheme allows the SAR logic to operate
at 0.4 V, reducing the overall power consumption of the ADC by 15% without any
loss in performance. In dual-supply mode (1.0 V for analog and 0.4 V for digital), the
ADC achieves 9.1 ENOB, consumes 53 nW at 1 kS/s. The leakage power constitutes
25% of the 53-nW total power consumption.
4.1
ADC Architecture
Figure 4.1 shows the block diagram of the proposed ADC. It comprises a matched
binary-weighted capacitive DAC, a low-power dynamic latch comparator, a lowleakage/low-voltage synchronous SAR digital logic, and level shifters between the
digital logic and the analog blocks. In addition, a differential architecture was
employed to have a good common-mode noise rejection.
In a conventional SAR ADC [37], the input voltage is sampled on the bottom-plate
nodes of the capacitor array and the top-plate nodes are reset with a fixed voltage.
The fixed voltage is commonly chosen to be one of the power rails in order to avoid
extra voltage levels. However, this makes the DAC outputs go beyond the rails during
the conversion when full-range input sampling is applied. One common way to solve
this problem is to decrease the input range with the penalty of degrading the signal-to-
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36
A 53-nW 9.1-ENOB SAR ADC in 0.13 µm CMOS Process
GND
VDDH
VDDH
C9
VINP
C8
C0
C0
SP
VDACP
COUT
VINN
VDACN
SN
C9
VDDH
GND
C8
C0
C0
Sample/
Control
Signals
Clock
VDDH
VDDL
Voltage Level Shifters
VDDL
CLK
RST
Successive Approximation Register
D0 ~ D9
Figure 4.1: Architecture of the SAR ADC.
noise ratio. Another alternative is to make the top-plate switches bootstrapped. In this
work, we use top-plate sampling [9] with MSB preset to achieve full-range sampling
without switch bootstrapping and extra reset voltages. As shown in Fig. 4.2, the
differential inputs are initially connected to the top-plates of the capacitor array, and
simultaneously the MSB is reset to high and all other bits are reset to low. Next, the
top-plate sampling switch is open and the input data is sampled on the capacitor array.
The comparator then performs the first comparison. If VDACP is higher than VDACN ,
the MSB remains high. Otherwise, it goes low. Then, the second approximation
step starts by setting MSB-1 to high, and the comparator does the comparison again.
The ADC repeats this procedure until all 10 bits are decided. During the entire
conversion, the DAC outputs always remain within the rails. Moreover, the commonmode voltage of the DAC outputs is the same as that of the differential inputs, which
is equal to mid-rail voltage for full-range input sampling, as shown in Fig. 4.3. The
constant common-mode voltage reduces the signal-dependent offset voltage of the
comparator [18].
“lic˙thesis” — 2012/8/1 — 12:14 — page 37 — #53
4.1 ADC Architecture
37
VDD VDD
VDD
(0 ~ VDD)
VIP
VIN
Sample
VDACP
MSB
VDACN
MSB-1
VDD
Sampling Phase
Related Time Sequence
Figure 4.2: The sampling phase of capacitive DAC with MSB preset.
VDD
VDACP
VCM
VDD/2
MSB-2
MSB-1
VDACN
MSB
0
Figure 4.3: Waveform of the DAC switching procedure.
Lowering the supply voltage is an efficient technique to reduce both the switching
and leakage power consumption. This is particularly true at low data-rates, where
transistors can be slow but still meet the target speed. However, for the analog circuits
operating with low supply voltages, noise and a reduced dynamic range can degrade
the ADC performance. To avoid the analog performance degradation, in this design,
we use a dual-supply voltage scheme, which allows the SAR logic to operate at low
supply voltages. Our measurement results (in Sec. 4.3) show that this voltage scaling
has reduced the overall power consumption of the ADC by 15% without any loss in
performance.
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38
A 53-nW 9.1-ENOB SAR ADC in 0.13 µm CMOS Process
4.2
Circuit Implementation
In this section, the circuit level design of the DAC, switches, comparator, and SAR
digital logic are described. Since these components are critical with regards to power
consumption, speed, and accuracy of the entire ADC, much of the design effort was
focused on characterizing and optimizing their performance.
4.2.1
Capacitive DAC
C4
C3
C0
C2
C1
C9
C8
C7
C9
C8
C7 C6 C5 C6 C7 C8
C9
C7 C8
C9
Bottom-plate switch network
The capacitive DAC was implemented with a binary-weighted capacitor array. In this
technology, a MIM capacitor has a density of 2 fF/µm2 and a matching of 1%µm.
Eq. (2.16), which calculates the lower bounds for the mismatch-limited unit capacitor,
leads to a minimum unit capacitance of 4 fF. Apart from the mismatch, the design
rule will also set a minimum value on the MIM capacitance, which is 27 fF in this
process. Consequently, the unit capacitance was set to be 13.5 fF in our work, which
was implemented by two minimum process-defined MIM capacitors in series. Hence,
the total array capacitance is about 14 pF.
C0
Figure 4.4: Layout of the capacitor array which follows a partial common-centroid configuration.
The capacitors are indicated according to Fig. 4.1.
Besides capacitor sizing, a careful layout to avoid linearity degradation is important as well. In this work, we have utilized a partial common-centroid layout
strategy for the capacitor array. Fig. 4.4 illustrates the layout floor plan. The MSB
capacitors (C9 -C5 ) follow a common-centroid configuration to minimize the errors
from the non-uniform oxide growth in the MIM capacitors. However, the smaller
LSB capacitors (C4 -C0 ) have been placed close to the bottom-plate switches to simplify the routing, thereby reducing the parasitic capacitance and resistance of the
interconnection. Post-layout simulations showed that the reduced parasitic of the
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4.2 Circuit Implementation
39
employed partial common-centroid layout results in better DAC linearity, compared
to a capacitor array with a full common-centroid layout (where the LSB capacitors
were placed in the middle of the array). Based on the simulations, the DAC with
the partial common-centroid layout had a peak DNL of +0.18/-0.20 LSB and INL of
+0.30/-0.23 LSB, while the DAC with a full common-centroid layout had a peak DNL
of +0.35/-0.16 LSB and INL of +0.40/-0.36 LSB.
4.2.2
Switch Design
The top-plate sampling switch was implemented using transmission gate, shown
in Fig. 4.5, to achieve full-range input sampling. The switch together with the
DAC capacitor array acts as the sample-and-hold circuit of the ADC. In Sec. 2.1.4,
Eq. (2.10) derives the minimum track bandwidth of a sampling circuit. In this design,
the sampling time is determined by the system clock, which is N+2 times the sampling
rate. Hence, we have
(N + 1) · (N + 1) · ln2
fS
(4.1)
π
Based on Eq. (4.1), for a 10-bit 1-kS/s SAR ADC, the required minimum f3dB
is about 30 kHz. Taking account of the 14-pF sampling capacitance, the switch
on-resistance (RON ) should be designed to be less than 380 kΩ.
f3dB >
Sample
VIN
CARRAY
1.1µ/0.26µ
1.1µ/0.26µ
0.3µ/0.26µ
0.3µ/0.26µ
Sample
Figure 4.5: Top-plate sampling switch.
Apart from the bandwidth requirement, the voltage droop introduced by the
leakage current of the switch can also degrade the sampling accuracy due to the long
conversion time. The sub-threshold leakage current of the transistor is the dominant
leakage contributor to the switch. In addition, the leakage current shows nonlinear
dependence on the input-output voltage difference across the switch, thus introducing
harmonic distortion. Increasing the channel length is an effective solution to reduce
the sub-threshold leakage current. To further reduce the leakage current, we have
utilized a two-transistor stack [39] (shown in Fig. 4.5). Figure 4.6 shows the simulated
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A 53-nW 9.1-ENOB SAR ADC in 0.13 µm CMOS Process
sub-threshold leakage currents of two different switches versus their input voltages.
The figure compares the leakage current of a single transistor with a channel length
of 4Lmin to two transistors in series with channel lengths of 2Lmin . It can be seen
that the stacked transistors show lower leakage for small input voltages in the range
from 0 V to 0.1 V.
High
ILEAK
0.5 V
VIN
Low
Stack
2Lmin
Single
2Lmin
4Lmin
(a)
60
Leakage current [pA]
50
Single 4Lmin
Stack 2Lmin
40
30
20
10
0
0
0.05
0.1
Input voltage [V]
0.15
0.2
(b)
Figure 4.6: Simulated leakage current of the sampling switch: (a) test-bench (b) leakage current
versus input voltage.
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4.2 Circuit Implementation
41
To determine the channel length of the stacked transistors, the sampling circuit
was simulated at 1-kHz sampling frequency with full-range input signal for three
different switch lengths (Lmin +Lmin , 2Lmin +2Lmin , and 3Lmin +3Lmin ). The
frequency of the input signal was swept from near-DC to near-Nyquist bandwidth.
The voltage of the sampled output signal was recorded at the end of the hold phase
to track the voltage droop. The simulated worst-case SNDR of the recorded voltage
was found at near-Nyquist operation. The resulted SNDR for three different switch
lengths were 60.9 dB, 67.4 dB, and 67.5 dB, respectively. Thus increasing the total
channel length beyond 4Lmin (2Lmin +2Lmin ) did not introduce much benefit for the
leakage reduction. Hence, in this work, the channel length of the stacked transistors
was chosen to be 2Lmin (0.26 µm).
Furthermore, we sized the transistor width and simulated the switch RON over the
entire input range under -40◦ C at the slow process corner. The simulated maximum
RON based on the chosen transistor widths (0.3 µm for NMOS and 1.1 µm for
PMOS) is about 80 kΩ. With the total array capacitance of 14 pF, the f3dB of the
sampling circuit is then calculated to be about 140 kHz, which gives a design margin
with more than four times the required minimum f3dB .
At the bottom-plate sides, inverters connect the capacitors to the power rails.
Ideally, minimum-size transistors can be used for all the inverters because of the low
sampling rate, thus minimizing power consumption. In practice, however, special
care must be taken during sizing of the MSB inverter. The NMOS top-plate sampling
switch introduces parasitic PN-junction on the top-plate node. After a near-ground
input voltage is sampled, during the MSB to MSB-1 transition, the voltage on the
top-plate node can undershoot below ground, forward-biasing the PN-junction and
causing charge loss. To avoid the undershoot voltage, the PMOS transistor in the
MSB inverter was sized up to six times the minimum width.
4.2.3
Dynamic Latch Comparator
The dynamic latch comparator [40] is shown in Fig. 4.7. Buffers have been used to
make the output loading identical. A succeeding SR latch stores the comparison result
for the entire clock cycle.
Since the input common-mode voltage of the comparator is kept at mid-rail
voltage, the total comparator offset appears as static offset, which does not affect the
linearity of the ADC [18]. Though the offset of the comparator does not affect the
accuracy, it will decrease the input voltage range, thus degrading the signal-to-noise
ratio. Monte Carlo simulations of the comparator offset [41] showed a total offset
voltage of 35.1 mV with 3-σ being considered. The simulated offset voltage decreases
the SNR by 0.3 dB, thereby introducing an ENOB loss of 0.05 bit.
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A 53-nW 9.1-ENOB SAR ADC in 0.13 µm CMOS Process
Clock
MP5
S1
VINP
Clock
MP1
S2
MP3
MP2
VINN
S3
MP4
Clock
VON
VOP
S4 MN1
MN2 S5
Figure 4.7: Dynamic latch comparator.
4.2.4
SAR Control Logic
For low power SAR control logic, we investigated both synchronous and asynchronous
solutions. Asynchronous processing [42] has been frequently used for high-speed
SAR ADCs in order to avoid a high-frequency system clock. The SAR control
logic starts the conversion on the rising edge of a sampling clock, and triggers the
internal comparison from MSB to LSB successively. The delay, usually generated
by an inverter line [9], has a large dependency on process, voltage, and temperature
variations, which makes it difficult to ensure the DAC settling. Moreover, the shortcircuit current caused by the slow transition of the inverters introduce extra power
consumption [9].
The proposed ADC utilizes a synchronous SAR logic, shown in Fig. 4.8. It
generates the sample signal and the switch control signals for the DAC. The operation
of its multiple-input 10-bit shift resister is similar to [43]. A 4-bit counter and a
decoder generate the control signals for the 10-bit shift register. The entire logic uses
16 transmission-gate DFFs and the decoder has been optimized for minimum logic
depth and gate count. Fig. 4.9 shows the time sequence of the SAR logic. A 12-kHz
system clock has been used, and the sampling clock of 1 kHz is generated by the SAR
logic.
Since the operating frequency of the SAR logic is 12 kHz, and its switching
activity is not high, the leakage power dominates the total power consumption. Several
techniques have been used to reduce the leakage currents, including increased channel
length, minimum transistor width, and replacing the gate transistors with stacked
pairs [44].
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4.2 Circuit Implementation
43
Decoder
4-bit
counter
MUX
RST
D
Q
D
CLK
CLK RST
D9
MFF
D0
MFF
MFF
Multiple-input
10-bit shift register
CLK
COMP
RST
sample and control signals to the level shifters
Figure 4.8: SAR control logic.
1
2
3
4
5
6
7
8
9
10
11 12 13
CLK
Sample
DOUT
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Figure 4.9: Time sequence of the synchronous SAR control logic.
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A 53-nW 9.1-ENOB SAR ADC in 0.13 µm CMOS Process
To further reduce the switching and leakage power consumption, a dual-supply
voltage scheme has been employed, allowing the SAR logic to operate at 0.4 V. A
conventional level shifter, shown in Fig. 4.10, has been used to convert the logic
levels between the SAR and the analog parts. In the entire ADC, twelve level shifters
have been used: ten for the DAC control signals, one for the sampling signal of the
top-plate switch, and one for the clock signal of the comparator.
VDDH
OUT-
OUT+
VDDL
VDDL
IN
Figure 4.10: Level shifter.
4.3
Measurement Results
The prototype SAR ADC with a core area of 357×536 µm2 was designed and
fabricated in a general purpose 0.13-µm one-poly six-metal (1P6M) CMOS process.
It was packaged in a 1.27 mm pitch J-Leaded Chip Carrier (JLCC) package. A
photograph of the chip is shown in Fig. 4.11. The unmarked part around the ADC
core includes the decoupling capacitors and the I/O buffers for the pads.
357µm
536µm Switches
Comparator
DAC
SAR +
Level Shifters
Figure 4.11: Die photograph of the ADC in 0.13-µm CMOS technology.
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4.3 Measurement Results
45
Histogram test [45] was conducted to measure the linearity of the ADC. A fullswing, differential sinusoidal input near DC frequency with amplitude of 1 V was
applied to the 1-kS/s ADC. Fig. 4.12 shows the measured DNL and INL error with
respect to the output code. The peak DNL error is +0.54/-0.61 LSB, and the peak INL
error is +0.45/-0.46 LSB.
DNL [ LSB ]
1
0.5
0
-0.5
-1
0
200
400
600
200
400
600
Output Code
800
1000
800
1000
INL [ LSB ]
1
0.5
0
-0.5
-1
0
Figure 4.12: Measured DNL and INL errors.
The SNDR of the ADC was measured using tone testing. A fast Fourier transform (FFT) of the 1-kS/s ADC at near-Nyquist operation is shown in Fig. 4.13. The
amplitude of the test stimulus was set to -0.5 dBFS. The measured SNDR is 56.7 dB,
providing 9.1 ENOB. Fig. 4.14 shows the ENOB of this ADC with respect to the
input frequency, where the ENOB remains almost constant over the entire bandwidth. Hence, the effective resolution bandwidth (ERBW) is higher than the Nyquist
bandwidth.
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A 53-nW 9.1-ENOB SAR ADC in 0.13 µm CMOS Process
0
PSD [ dB ]
-20
-40
-60
-80
-100
0
0.1
0.2
0.3
0.4
Frequency [ f / f s ]
0.5
Figure 4.13: Measured 8,192-point FFT spectrum at 1 kS/s.
ENOB [ bit ]
9.5
9
8.5
0
0.1
0.2
0.3
0.4
Normalized f in/f s
0.5
Figure 4.14: ENOB of the ADC versus input frequency.
Multiple supply voltage domains were utilized, allowing detailed measurement of
the power consumption in the DAC, comparator, and SAR control logic, respectively.
The total measured power consumption of the 1-kS/s ADC is 53 nW in dual-supply
mode (VDDH of 1.0 V for DAC and comparator, and VDDL of 0.4 V for SAR logic)
and 72 nW in 1-V single-supply mode. The measured leakage power of the digital
part is 13 nW in dual-supply mode and 22 nW in 1-V single-supply mode, which
constitutes 25% and 31% of the total power consumption, respectively. It implies
that the digital leakage power consumption is a major contributor to the total power
consumption.
The power of the level shifters was simulated based on post-layout extraction.
In dual-supply mode, the level shifters consume 12 nW; in 1-V single-supply mode,
they consume 10 nW. Excluding the 10-nW power consumption of level shifters from
the total 72 nW would result in a total ADC power consumption of 62 nW in the
single-supply mode. This indicates that the voltage scaling has reduced the overall
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4.3 Measurement Results
47
power consumption of the ADC by 15% without any loss in performance. Fig. 4.15
shows the power breakdown of the ADC in the two modes. Table 4.1 summarizes the
measured performance of the ADC.
62%
DAC
Control Logic
(SAR + Level Shifter)
34%
Leakage 25%
Comparator
4%
0%
10%
20% 30%
40%
50%
60%
70%
Percentage of block power within the total power
(a) Dual-supply mode VDDH = 1.0V and VDDL = 0.4V
46%
DAC
Control Logic
(SAR + Level Shifter)
51%
Leakage 31%
Comparator
3%
0%
10%
20% 30%
40%
50%
60%
70%
Percentage of block power within the total power
(b) Single-supply mode VDDH = VDDL = 1.0V
Figure 4.15: The ADC power breakdown in dual and single supply modes, where the percentage
of digital leakage power is indicated by dark color.
The power and dynamic performance of the 1-kS/s ADC under different supply
settings were measured. The figure-of-merit (FOM) which has been used to compare
the ADC performance is defined as
F OM =
P ower
min{fS , 2 × ERBW } × 2EN OB
(4.2)
Table 4.2 shows the measurement results together with the corresponding FOM.
The ADC achieves the optimal performance at VDDH = 1.0 V and VDDL = 0.4 V
with the lowest FOM of 94.5 fJ/Conversion.
As demonstrated in this work, at such low-sampling rates, leakage power becomes a significant portion of the total power, degrading the FOM as compared to
ADCs for higher sampling rates. Therefore, Table 4.3 compares the measurement
results of this work to previously published SAR ADCs with comparable sampling
rates [46][47][48]. As the table shows, this ADC achieves the lowest power and FOM.
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A 53-nW 9.1-ENOB SAR ADC in 0.13 µm CMOS Process
Table 4.1: ADC Measurement Summary
ADC Performance
Technology
standard 0.13-µm CMOS
Core area [mm2 ]
0.19
Resolution [bits]
10
Input range
0 - VDD
Sampling rate [kS/s]
1
DNL [LSB]
+0.54/-0.61
INL [LSB]
+0.45/-0.46
SNDR (at Nyquist) [dB]
56.7
SFDR (at Nyquist) [dB]
67.6
ADC Power Breakdown
Supply voltage [V]
Comparator, DAC
1.0
1.0
SAR
0.4
1.0
Comparator [nW]
2
2
Capacitive DAC [nW]
33
33
Control Logic (SAR+Level Shifter) [nW] 18
37
Total Power [nW]
53
72
Table 4.2: ADC Performance Under Different Supply Settings
VDDH /VDDL [V ]
Power [nW]
ENOB (at Nyquist) [bit]
FOM [fJ/Conv.]
0.8/0.4
45
8.7
108.1
1.0/0.4
53
9.1
94.5
1.0/1.0
72
9.1
129.4
1.2/1.2
94
9.2
159.8
Table 4.3: ADC Comparison
Technology
Sampling rate [kS/s]
Power [nW]
ENOB [bit]
FOM [fJ/Conv.]
[46]
0.8 µm
0.8
3000
9
7300
[47]
0.35 µm
1
230
10.2
195
[48]
0.18 µm
4.1
850
6.9
1700
This Work
0.13 µm
1
53
9.1
94.5
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4.3 Measurement Results
49
A comparison of the implemented ADC with our mismatch-limited power consumption bounds is shown in Fig. 4.16. The ADC is a bit far from the bounds because
leakage power consumption, which is neglected in our power analysis for simplicity, does take a significant portion of the total ADC power consumption, thereby
degrading the energy efficiency.
4
10
3
Power/fs [pJ]
10
2
10
← This ADC
1
10
0
10
−1
10
4
6
8
10
ENOB [bit]
12
14
Figure 4.16: Predicted mismatch-limited SAR ADC power consumption bounds (solid line)
together with Nyquist SAR ADC survey data (∆) and the implemented ADC (o).
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A 53-nW 9.1-ENOB SAR ADC in 0.13 µm CMOS Process
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Chapter 5
A 3-nW 9.1-ENOB SAR ADC
in 65 nm CMOS Process
In Chapter 4, we presented a 53-nW 9.1-ENOB SAR ADC at 1 kS/s in 0.13 µm CMOS
process. Following a design strategy with maximum simplicity in the architecture,
the ADC achieved the ultra-low-power consumption by using a binary-weighted
capacitive DAC with a top-plate sampling technique, a dual-supply voltage scheme
allowing the SAR control logic to operate at 0.4 V, as well as low-leakage circuit
techniques and considerable design optimizations.
Based on the understanding from our previous work, in this chapter we present a
single-supply-voltage 10-bit (9.1-ENOB) 1-kS/s SAR ADC in 65 nm CMOS process,
with a substantial (94%) improvement in power consumption, resulting in 3-nW total
power consumption.
Taking advantage of the smaller feature size and the availability of standard- and
high-VT devices in 65 nm process, the ultra-low-power consumption is achieved by:
1) a split-array capacitive DAC, which substantially reduces the DAC capacitance
while still ensuring sufficient linearity; 2) a bottom-plate sampling approach reducing
the charge injection error due to use of small DAC capacitance, while enabling fullrange input sampling without extra voltage sources; 3) a multi-VT design, allowing
the ADC to meet the target performance with a single supply voltage of 0.7 V, thereby
reducing both the switching and leakage power consumption; and 4) a latch-based
SAR control logic resulting in reduced power consumption and low transistor count.
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A 3-nW 9.1-ENOB SAR ADC in 65 nm CMOS Process
5.1
Comparison in Leakage between 0.13 µm and
65 nm CMOS Processes
400
NMOS
300
200
100
Leakage Current [pA]
Leakage Current [pA]
The previous design in 0.13 µm CMOS process has shown that leakage is the issue.
Fig. 5.1 shows the simulated transistor sub-threshold leakage current versus channel
length in the standard 0.13 µm CMOS process, and Fig. 5.2 in the low-power 65 nm
CMOS process. It can be seen that the leakage performance is much better in the
low-power 65 nm process than that in the standard 0.13 µm process. Moreover,
high-VT devices are the primary choice in this design where leakage is the major
concern.
0
0
0.2
0.4
0.6
0.8
40
30
PMOS
20
10
0
0
0.2
0.4
0.6
Length [µm]
0.8
Figure 5.1: Simulated transistor sub-threshold leakage current versus channel length in standard
0.13 µm process at 0.15-µm Wmin , 1-V supply, typical corner, and 27o C.
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50
NSVTLP
40
30
20
10
0
Leakage Current [pA]
Leakage Current [pA]
60
0.1
0.2
0.3
15
PSVTLP
10
5
0
0
0.1
0.2
0.3
Length [µm]
(a)
0.4
53
4.5
4
NHVTLP
3.5
3
2.5
2
0
0.4
Leakage Current [pA]
Leakage Current [pA]
5.1 Comparison in Leakage between 0.13 µm and 65 nm CMOS Processes
0.1
0.2
0.3
0.4
2
1.8
PHVTLP
1.6
1.4
1.2
1
0
0.1
0.2
0.3
Length [µm]
0.4
(b)
Figure 5.2: Simulated transistor sub-threshold leakage current versus channel length in low-power
65 nm process at 0.135-µm Wmin , 1-V supply, typical corner, and 27o C: (a) standard-VT devices
(b) high-VT devices.
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54
5.2
A 3-nW 9.1-ENOB SAR ADC in 65 nm CMOS Process
ADC Architecture
The architecture of the proposed SAR ADC is shown in Fig. 5.3. It comprises a
differential capacitive DAC, a dynamic latch comparator, and a synchronous SAR
control logic.
VREF
VIN
C
16C
C
VDD
16C
C
VDACN
COUT
VDACP
C
C
Reset
16C
C
16C
VIP
VREF
Successive Approximation Control Logic
VDD
CLK
RST
DOUT (D0 ~ D9)
Figure 5.3: SAR ADC architecture.
5.2.1
Split-Array DAC
The metal capacitor in 65 nm CMOS process has good matching properties. It has
a matching of 0.5 %µm and a density of 0.4 fF/µm2 . For a 10-bit binary-weighted
capacitive array, it leads to a minimum unit capacitance of 0.2 fF based on Eq. (2.31).
While the minimum metal capacitance defined by the design-kit is 10 fF, which is
much larger than necessary to meet the linearity requirements, thereby resulting in
considerably large array capacitors and high switching power consumption.
Hence, we implemented a split binary-weighted capacitive array with 5-bit subDAC and 5-bit main-DAC. Based on Eq. (2.31), it requires a larger unit capacitor of
6 fF compared to that in a single-array DAC. Further considering the design margin, a
15-fF unit capacitance is chosen, which still arrives at a smaller total array capacitance
of 945 fF.
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5.2 ADC Architecture
5.2.2
55
Bottom-Plate Sampling
Since the array capacitance is significantly reduced, the charge injection during
sampling will degrade the conversion accuracy, and therefore bottom-plate sampling
technique is used to minimize the error.
When a full-range input voltage is sampled on the bottom-plates, the top-plate
nodes are usually reset to the input common-mode. Otherwise, the DAC outputs will
go beyond the rails for certain input range. In this work, we use a sampling approach
to avoid introducing the extra reset voltage source, and at the same time the approach
still ensures full-range input sampling without degrading the signal-to-noise ratio.
1
2
3
4
5
6
7
8
9 10 11 12
CLK
SR
ST
SB
DOUT
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Figure 5.4: Time sequence of SAR ADC.
(a)
VIN
VCM
VIP
(b)
Figure 5.5: DAC arrays during (a) reset phase (b) sampling phase.
Figure 5.4 illustrates the time sequence of the SAR ADC, which takes 11 clock
cycles in total to complete one conversion. The first clock cycle is divided into reset
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A 3-nW 9.1-ENOB SAR ADC in 65 nm CMOS Process
phase and sampling phase. Fig. 5.5 depicts the switching status of DAC arrays during
the two phases. In reset phase (Fig. 5.5(a)), the control signal, indicated as SR in
Fig. 5.4, becomes high. The capacitors are discharged to ground. When it comes to
the sampling phase (Fig. 5.5(b)), the control signals, driving the bottom-plate switches
and the top-plate connection switch, turn to high, which are indicated as ST and SB
in Fig. 5.4, respectively. The bottom-plates of the differential capacitor arrays are
then connected to the differential input. The top-plates are shorted, and their voltage
becomes the input common-mode. Consequently, only the differential-mode input is
sampled on the array, which makes the DAC outputs always remain within the rails.
To minimize the charge injection error, the top-plate connection switch is turned
off before the bottom-plate switches. As shown in Fig. 5.4, the signal SB is delayed
by a series of weak inverters compared to the signal ST .
5.2.3
Low-Voltage Single Supply
Lowering the supply voltage is an efficient technique to reduce both the switching and
leakage power. This is particularly true for digital circuits, where transistors can be
substantially slow but still meet the target data-rates. For the analog circuits, however,
low voltages will introduce sampling distortions and comparator decision error. In
our previous work, a dual-supply voltage scheme was utilized. The additional supply
and level shifters increase the design complexity and consume extra power.
In this work we chose a single supply for simplicity. In addition, a combination
of high-VT and standard-VT transistors is utilized to minimize the leakage while
still ensuring sufficient speed at low voltages (down to 0.6 V), thereby achieving the
optimal energy efficiency. Our measurement results (in Sec. 5.4) show that the ADC
achieves 4.5 fJ/conversion-step with 8.8 ENOB at 0.6 V and 1 kS/s.
5.3
5.3.1
Circuit and Chip Implementation
Capacitive DAC
As aforementioned, the DAC with split-array, shown in Fig. 5.3, is composed of two
binary-weighted capacitive arrays with an attenuation capacitor in the middle. The
attenuation capacitor is set to be the unit capacitance instead of a fractional value for
ease of layout and good matching. Removing a dummy unit capacitor at the end of
the sub-DAC introduces gain error about 1 LSB. If necessary, the gain error can be
calibrated in the digital domain.
A careful layout to avoid linearity degradation is important as well. Fig. 5.6
illustrates the DAC layout floor plan for one differential branch. Both the mainDAC (C9 -C5 ) and sub-DAC (C4 -C0 ) use a partial common-centroid strategy. The
MSB capacitors follow a common-centroid configuration to minimize the errors from
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5.3 Circuit and Chip Implementation
57
C6
C9
C8
C7
C8
Main-DAC
C9
C5
C4
C3
C2 C3
C4
CB
Bridge-CAP
C1
Sub-DAC
C0
Figure 5.6: Layout floor plan of the capacitor array. The capacitors, not indicated in the figure, are
dummies.
the non-uniform oxide growth in the metal capacitors. The smaller LSB capacitors
are placed close to the switch network to simplify the interconnection.
CB
CB
VDAC
VDAC
Main-DAC
Sub-DAC
Case 1
Main-DAC
Sub-DAC
Case 2
Figure 5.7: The parasitic capacitance of the bridge capacitor: 1) connected to the mainDAC (Case 1); 2) connected to the sub-DAC (Case 2).
The parasitic capacitance associated with the bridge capacitor degrades the ADC
performance. Fig. 5.7 shows two connection cases of the parasitic capacitor. Intuitively, the capacitor plate which contributes the major parasitic capacitance should
be connected to the main-DAC, which is ’Case 1’ in Fig. 5.7. Since the sub-DAC
interpolates between transition voltages generated by the main-DAC, if the parasitic
capacitor is connected to the sub-DAC, it will introduce more step variations to the
transfer curve. To verify the effect by simulation, the capacitive DAC was implemented under three cases: 1) parasitic capacitance of 10 fF connected to the main-DAC; 2)
parasitic capacitance of 10 fF connected to the sub-DAC; and 3) ideal bridge capacitor
without parasitics. The ADC dynamic performance at near-DC input frequency of the
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A 3-nW 9.1-ENOB SAR ADC in 65 nm CMOS Process
three cases based on transistor-level simulations are given in Table 5.1. Compared
to the ideal case, the parasitic capacitor degrades the ADC performance. Moreover,
the worst case happens when the parasitic capacitor is connected to the sub-DAC.
Therefore, in the DAC layout, the plate of the bridge capacitor which contributes the
major parasitic capacitance is deliberately connected to the main-DAC.
Table 5.1: ADC Dynamic Performance With Respect to Bridge Capacitor Connection
Case 1 (to Main-DAC)
Case 2 (to Sub-DAC)
Case 3 (Ideal)
5.3.2
SNR
60.77
60.24
60.84
SNDR
60.39
59.77
60.45
THD
-71.13
-69.64
-71.14
Unit
dB
dB
dB
Switch Design
The switches of the capacitor array are shown in Fig. 5.8. Multi-VT design approach
has been used. Three types of transistors are provided by the process: high-VT ,
standard-VT , and low-VT . Because low-VT transistors have high leakage current,
they are not suitable for this design. Hence, only high-VT and standard-VT transistors
are used, and they are indicated by HVT and SVT in the figure, respectively.
Since the conversion time is long and the top-plate nodes are floating during the
conversion, to minimize the voltage droop caused by leakage current, the top-plate
switches are all using high-VT NMOS. Moreover, in order to further reduce the
leakage current, the reset-switches utilize a two-transistor stack and long channel
length (1µm), and the connection-switch uses four times the minimum channel length.
At the bottom-plates of the capacitive array, transmission gates with standardVT devices are used to speed up the DAC settling when VIN is near mid-range.
However, the inverters, switching the bottom-plate nodes between ground and VREF ,
are implemented with high-VT transistors to reduce the leakage current from VREF .
“lic˙thesis” — 2012/8/1 — 12:14 — page 59 — #75
5.3 Circuit and Chip Implementation
59
Bypassed
ST
Connection Switch
0.135µ/0.24µ
Boosted
HVT
HVT
HVT
VDACP
HVT
HVT
VDACN
Reset Switch
0.135µ/1.0µ
(a)
C
HVT INV:
PMOS 0.135µ/0.06µ
NMOS 0.135µ/0.06µ
SVT
SVT
SVT TG:
PMOS 0.27µ/0.06µ
NMOS 0.135µ/0.06µ
VREF
HVT
VIN
(b)
Figure 5.8: (a) Top-plate switches. (b) Bottom-plate switches.
VDD
M3
M2
M1
BYPASS
CB
VB
VC
CLKIN
CLKOUT
Figure 5.9: Voltage boosting circuit with bypass function.
Though the top-plate connection-switch with high-VT devices effectively reduces
the sub-threshold leakage current, its high on-resistance will introduce severe distortions at low supplies when it passes midrail voltages. In view of this, a voltage
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60
A 3-nW 9.1-ENOB SAR ADC in 65 nm CMOS Process
boosting circuit, similar to [49], is used to drive the connection-switch at low supply
voltages. As depicted in Fig. 5.9, when the input clock goes low, M1 and M3 turn
on, M2 turns off, VC goes to ground, VB connects to VDD , and the output clock goes
low; when the input clock goes high, M1 and M3 turn off, M2 turns on, VC connects
to VDD , VB is then boosted to 2VDD , and the output clock goes high with 2VDD . In
practice, due to charge sharing between CB and the parasitic capacitance associated
to node VB , the boosted output is less than 2VDD .
The boosting circuit can be disabled by setting the BYPASS signal to high. The
output of the NOR gate is then kept at ground, and the output logic high always equal
to VDD .
5.3.3
Dynamic Latch Comparator
The dynamic latch comparator [50] is shown in Fig. 5.10. It has no static biasing.
Buffers are connected successively to make the output loading identical. A followed
cross-coupled NAND gates store the comparison result for an entire clock cycle. The
reset signal is synchronous with the clock of the SAR control logic.
Similarly, the comparator utilizes a combination of high-VT and standard-VT
transistors to minimize the leakage while ensuring the target speed at low voltages.
Standard-VT devices are used for the differential input transistors and the crosscoupled inverters to enhance the comparison speed. A high-VT PMOS is implemented
for the bias transistor to reduce the leakage current from the supply.
Reset
VINP
Reset
HVT
SVT
VINN
SVT
HVT
HVT
SVT
Reset
SVT
VON
VOP
HVT
SVT
SVT
HVT
Figure 5.10: Dynamic latch comparator with high- and standard-VT transistors.
“lic˙thesis” — 2012/8/1 — 12:14 — page 61 — #77
5.3 Circuit and Chip Implementation
61
Since the input common-mode voltage of the comparator is kept at mid-rail
voltage, the comparator offset appears as static offset, which does not affect the ADC
linearity [18]. However, the offset decreases the input voltage range, thus degrading
the signal-to-noise ratio. Monte Carlo simulations of the comparator offset showed a
standard deviation of 17 mV. Assuming 3σ is considered, it results in a total offset
voltage of 51 mV, decreasing the SNR by 0.7 dB. The decreased SNR introduces an
ENOB loss of 0.1 bit.
5.3.4
SAR Control Logic
The SAR control logic is shown in Fig. 5.11. It consists of a shift register, a set of
bit latches, a sample signal generator, and a combinational switching logic. Due to
the low sampling rate, static logic instead of dynamic one is used for the register and
latches to avoid charge leakage. On the other hand, since speed is not a major concern,
the logic circuits are designed with minimum size.
CLK
Q
D
Q
D
RST
D
RST
Q
RST
D
SET
START
SR
Q
RST
DFF
DFF
DFF
th
th
9
10
2
nd
DFF
st
BYPASS
Sample
Gen
ST
SB
1
CLR
COUT
L
Q
Latch
L
Q
Latch
1st
L
Q
Latch
RST
Latch
RST
2nd
RST
Q
9th
RST
L
10th
START
Combinational Switching Logic
To control the bottom-plate switches of differential capacitive array
Figure 5.11: SAR digital control logic.
A latch instead of a DFF, shown in Fig. 5.12, is used to store the comparator
decision, thus reducing the transistor count and lowering the power consumption.
However, special care must be taken during generating the latch signal. The latch may
miss the current comparator result and record the successive one due to an improper
latch signal. In this design, the output signal from the corresponding-order DFF of
the shift register, indicated in Fig. 5.11, is used to clock the latch.
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62
A 3-nW 9.1-ENOB SAR ADC in 65 nm CMOS Process
LATCH
Race
Avoided!
VDD
D
LATCH
RST
Q
D
Figure 5.12: Latch circuit.
5.3.5
Chip Implementation
A micrograph of the entire ADC in 65 nm CMOS process is shown in Fig. 5.13. The
core occupies 0.037 mm2 , while the remaining area in the figure is used for supply
decoupling. For clarity, the right part of Fig. 5.13 shows the ADC layout including
the differential capacitive DAC, the comparator, and the SAR digital logic.
Table 5.2 shows the power breakdown of the ADC at 0.7 V and 1 kS/s according
to simulations. By subtracting the schematic-based total power consumption from
the post-layout-based one, the power consumption of parasitics is approximated to
be 1.24 nW, which constitutes a large portion of the total power (44%). This can be
improved by optimizing the layout, but it also demenstrates that the interconnection
becomes more significant for such a low-speed design with small transistor dimensions in deep-submicron technology. In addition, according to the schematic-level
simulation, the total leakage power is 0.67 nW, which contributes 43% of the total
power consumption.
Table 5.2: Simulated Power Consumption
Comparator
DAC
SAR logic
Total
Schematic [nW]
0.09 (6%)
0.75 (48%)
0.73 (46%)
1.57 (100%)
Post-layout [nW]
0.25 (9%)
1.10 (39%)
1.46 (52%)
2.81 (100%)
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63
DACP
Comparator
SAR
5.4 Measurement Results
DACN
0.037 mm2
Figure 5.13: Die photo and layout view of the ADC in 65 nm CMOS process.
5.4
Measurement Results
DNL [LSB]
Histogram and tone test were conducted to measure the static and dynamic performance of the 1-kS/s ADC, respectively. At VDD of 0.7 V, the measured peak DNL
error is +0.48/-0.55 LSB, and the peak INL error is +0.52/-0.61 LSB, as shown in
Fig. 5.14.
0.5 [−0.55, +0.48]
0
−0.5
INL [LSB]
0
200
400
600
800
1000
600
800
1000
0.5 [−0.61, +0.52]
0
−0.5
0
200
400
code
Figure 5.14: Measured DNL and INL errors of 1-kS/s 0.7-V ADC.
At the same supply, the measured FFT spectrums of the ADC at both near-DC and
near-Nyquist operations are depicted in Fig. 5.15. The amplitude of the test stimulus
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64
A 3-nW 9.1-ENOB SAR ADC in 65 nm CMOS Process
was set to -0.65 dBFS. At near-DC operation, the measured SNDR is 57.1 dB,
providing 9.2 ENOB. When the input frequency increases to near-Nyquist bandwidth,
the measured SNDR becomes 56.6 dB, resulting in 9.1 ENOB.
PSD [ dB ]
0
−20
SNDR = 57.1dB; ENOB = 9.2bit
−40
THD = −71.7dB; SFDR = 77.8dB
−60
−80
−100
−120
0
0.1
0.2
0.3
Frequency [ f / fs ]
0.4
0.5
(a)
PSD [ dB ]
0
−20
SNDR = 56.6dB; ENOB = 9.1bit
−40
THD = −68.9dB; SFDR = 74.5dB
−60
−80
−100
−120
0
0.1
0.2
0.3
Frequency [ f / fs ]
0.4
0.5
(b)
Figure 5.15: Measured 8,192-point FFT spectrums of 1-kS/s 0.7-V ADC: (a) near DC (b) near
Nyquist.
The measured total power of the 1-kS/s ADC at 0.7 V is 3 nW, leading to a FOM
of 5.5 fJ/conversion-step. Table 5.3 summarizes the measured performance of the
ADC.
The power and ENOB of the 1-kS/s ADC under different supply voltages were
also measured, and the results are shown in Table 5.4. At VDD from 0.6 V to 1.0 V,
the sampling switch is boosted; At VDD of 1.2 V, the boosted circuit is bypassed. The
ADC achieves the minimum FOM of 4.5 fJ/conversion-step at 0.6 V.
Table 5.5 compares the measurement results of this work to previously published
SAR ADCs with comparable sampling rates. As the table shows, this ADC achieves
the lowest power and FOM.
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5.4 Measurement Results
65
Table 5.3: ADC Measurement Summary
Technology
Core area [mm2 ]
Resolution [bit]
Input range [V]
Sampling rate [kS/s]
Supply voltage [V]
DNL [LSB]
INL [LSB]
SNDR (near Nyquist) [dB]
SFDR (near Nyquist) [dB]
THD (near Nyquist) [dB]
ENOB [bit]
Total power [nW]
FOM [fJ/Conv.]
low-power 65-nm CMOS
0.037
10
0 - VDD
1
0.7
+0.48/-0.55
+0.52/-0.61
56.6
74.5
-68.9
9.1
3
5.5
Table 5.4: Measured ADC Performance Under Different Supply Voltages
VDD [V] Power [nW] ENOB [bits] FOM [fJ/Conv.]
0.6
2
8.8
4.5
0.7
3
9.1
5.5
0.8
4
9.1
7.3
0.9
5
9.2
8.5
1.0
6
9.2
10.2
1.2
8
9.0
15.6
Note: For VDD = 0.6 V - 1.0 V, the sampling switch is
boosted; for VDD = 1.2 V, the sampling switch is not
boosted.
Table 5.5: ADC Comparison
Technology
Sampling rate
Area [mm2 ]
Supply voltage [V]
Power [nW]
ENOB [bit]
FOM [fJ/Conv.]
[47]
0.35 µm
1 kS/s
N/A
1.0
230
10.2
195
[48]
0.18 µm
4.1 kS/s
0.11
0.5
850
6.9
1700
[22]
0.13 µm
1 kS/s
0.19
1.0/0.4
53
9.1
94.5
[51]
65 nm
20 kS/s
0.212
0.55
206
8.84
22.3
This Work
65 nm
1 kS/s
0.037
0.7
3
9.1
5.5
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66
A 3-nW 9.1-ENOB SAR ADC in 65 nm CMOS Process
A comparison of the implemented ADC with our mismatch-limited power consumption bounds is shown in Fig. 5.16. Compared to the previous ADC, this ADC is
quite close to the bounds. The leakage power consumption is significantly reduced
due to the less-leaky low-power 65 nm CMOS process, thus improving the energy
efficiency.
4
10
3
Power/fs [pJ]
10
2
10
← Previous ADC
1
10
← This ADC
0
10
−1
10
4
6
8
10
ENOB [bit]
12
14
Figure 5.16: Predicted mismatch-limited SAR ADC power consumption bounds (solid line)
together with Nyquist SAR ADC survey data (∆) and the implemented ADCs (o).
“lic˙thesis” — 2012/8/1 — 12:14 — page 67 — #83
Chapter 6
Conclusions
Implantable medical electronics require low-speed, medium-resolution ADCs with
ultra-low-power operation. Among prevalent ADC architectures, SAR ADCs are
favored due to their high energy efficiency. The error sources as well as the power
consumption bounds of the SAR ADC have been analyzed. At low resolution, the
power consumption of SAR ADC is bounded by digital switching power. At mediumto-high resolution, the power consumption is bounded by thermal noise if digital
assisted techniques are used to alleviate mismatch issues; otherwise it is bounded by
capacitor mismatch.
Two 10-bit 1-kS/s SAR ADCs have been implemented. Following the design
strategy with maximum simplicity in the architecture, the first ADC, implemented
in a standard 0.13 µm CMOS process, achieves 9.1 ENOB with 53-nW power
consumption by using a binary-weighted capacitive DAC with a top-plate sampling
technique, a dual-supply voltage scheme allowing the SAR control logic to operate at
0.4 V, as well as low-leakage circuit techniques and considerable design optimizations.
The leakage power constitutes 25% of the total power consumption.
Based on the understanding from the first chip, the second ADC, implemented in a
low-power 65 nm CMOS process, achieves 9.1 ENOB and makes a substantial (94%)
improvement in power consumption, resulting in 3-nW total power consumption.
The ultra-low-power consumption is achieved by using an architecture with maximal
simplicity, a small split-array capacitive DAC, a bottom-plate sampling approach
reducing charge injection error and allowing full-range input sampling without extra
voltage sources, and a latch-based SAR control logic resulting in reduced power and
low transistor count. Furthermore, a multi-VT circuit design approach allows the
ADC to meet the target performance with a single supply voltage of 0.7 V. The ADC
can even operate down to a supply voltage of 0.6 V, achieving an optimal energy
efficiency of 4.5 fJ/conversion-step with 8.8 ENOB at 1 kS/s.
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68
Conclusions
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References
[1] M.D. Scott, B.E. Boser, and K.S.J. Pister. An ultralow-energy ADC for smart
dust. IEEE Journal of Solid-State Circuits, 38(7):1123 – 1129, July 2003.
[2] N. Verma and A.P. Chandrakasan. An ultra low energy 12-bit rate-resolution
scalable SAR ADC for wireless sensor nodes. IEEE Journal of Solid-State
Circuits, 42(6), June 2007.
[3] A. Shikata, R. Sekimoto, T. Kuroda, and H. Ishikuro. A 0.5v 1.1MS/sec
6.3fj/conversion-step SAR-ADC with tri-level comparator in 40nm CMOS. In
VLSI Symposium on Circuits, pages 262 –263, June 2011.
[4] Hua Gao, R.M. Walker, P. Nuyujukian, K.A.A. Makinwa, K.V. Shenoy, B. Murmann, and T.H. Meng. HermesE: A 96-channel full data rate direct neural
interface in 0.13 µm CMOS. IEEE Journal of Solid-State Circuits, 47(4):1043
–1055, April 2012.
[5] R. Sarpeshkar, C. Salthouse, Ji-Jon Sit, M.W. Baker, S.M. Zhak, T.K.-T. Lu,
L. Turicchia, and S. Balster. An ultra-low-power programmable analog bionic
ear processor. IEEE Transactions on Biomedical Engineering, 52(4):711 –727,
April 2005.
[6] H.-J. Yoo and C. van Hoof (Editors). Bio-Medical CMOS ICs. New York:
Springer, 2011.
[7] J. G. Webster. Medical Instrumentation Application and Design. Wiley, 1998.
[8] ADC performance survey 1997-2012.
˜murmann/adcsurvey.html.
http://www.stanford.edu/
[9] M. van Elzakker, E. van Tuijl, P. Geraedts, D. Schinkel, E. Klumperink, and
B. Nauta. A 1.9 µW 4.4 fJ/conversion-step 10 b 1 MS/s charge-redistribution
adc. In IEEE International Solid-State Circuits Conference Digest of Technical
Papers (ISSCC), pages 244 –245, Feb. 2008.
[10] R.J.Baker. CMOS: Circuit design, Layout, and Simulation. Wiley, 2005.
“lic˙thesis” — 2012/8/1 — 12:14 — page 70 — #86
70
REFERENCES
[11] A.P. Perez, E. Bonizzoni, and F. Maloberti. A 84dB SNDR 100kHz bandwidth
low-power single op-amp third-order ∆Σ modulator consuming 140µw. In
IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), pages 478 –480, Feb. 2011.
[12] P. Witte, J.G. Kauffman, J. Becker, Y. Manoli, and M. Ortmanns. A 72dbDR ∆Σ CT modulator using digitally estimated auxiliary DAC linearization
achieving 88fJ/conv in a 25MHz BW. In IEEE International Solid-State Circuits
Conference Digest of Technical Papers (ISSCC), pages 154 –156, Feb. 2012.
[13] F. Kuttner. A 1.2V 10b 20MSample/s non-binary successive approximation
ADC in 0.13 µm CMOS. In IEEE International Solid-State Circuits Conference
Digest of Technical Papers (ISSCC), volume 1, pages 176 –177 vol.1, Feb. 2002.
[14] Wenbo Liu, Pingli Huang, and Yun Chiu. A 12b 22.5/45MS/s 3.0mW 0.059mm2
CMOS SAR ADC achieving over 90dB SFDR. In IEEE International SolidState Circuits Conference Digest of Technical Papers (ISSCC), pages 380 –381,
Feb. 2010.
[15] Chun-Cheng Liu, Soon-Jyh Chang, Guan-Ying Huang, Ying-Zu Lin, ChungMing Huang, Chih-Hao Huang, Linkai Bu, and Chih-Chung Tsai. A 10b
100MS/s 1.13mW SAR ADC with binary-scaled error compensation. In IEEE
International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), pages 386 –387, Feb. 2010.
[16] Yanfei Chen, Xiaolei Zhu, H. Tamura, M. Kibune, Y. Tomita, T. Hamada,
M. Yoshioka, K. Ishikawa, T. Takayama, J. Ogawa, S. Tsukamoto, and T. Kuroda.
Split capacitor DAC mismatch calibration in successive approximation ADC.
In IEEE Custom Integrated Circuits Conference (CICC), pages 279 –282, Sep.
2009.
[17] M. Yoshioka, K. Ishikawa, T. Takayama, and S. Tsukamoto. A 10b 50MS/s
820 µw SAR ADC with on-chip digital calibration. In IEEE International
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), pages 384
–385, Feb. 2010.
[18] Chun-Cheng Liu, Soon-Jyh Chang, Guan-Ying Huang, and Ying-Zu Lin. A
10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure.
IEEE Journal of Solid-State Circuits, 45(4):731 –740, April 2010.
[19] B.P. Ginsburg and A.P. Chandrakasan. 500-MS/s 5-bit ADC in 65-nm CMOS
with split capacitor array DAC. IEEE Journal of Solid-State Circuits, 42(4):739
–747, April 2007.
[20] D. Zhang and A. Alvandpour. A 3-nW 9.1-ENOB SAR ADC at 0.7 V 1 kS/s.
In European Solid-State Circuit Conference (ESSCIRC), pages 666 – 668, Sep.
2012.
“lic˙thesis” — 2012/8/1 — 12:14 — page 71 — #87
REFERENCES
71
[21] D. Zhang, A. Bhide, and A. Alvandpour. A 53-nW 9.1-ENOB 1-kS/s SAR ADC
in 0.13-µm CMOS for medical implant devices. IEEE Journal of Solid-State
Circuits, 47(7):1585 –1593, July 2012.
[22] D. Zhang, A. Bhide, and A. Alvandpour. A 53-nW 9.12-ENOB 1-kS/s SAR
ADC in 0.13-µm CMOS for medical implant devices. In European Solid-State
Circuit Conference (ESSCIRC), pages 467 –470, Sep. 2011.
[23] D. Zhang, C. Svensson, and A. Alvandpour. Power consumption bounds for
SAR ADCs. In European Conference on Circuit Theory and Design (ECCTD),
pages 556 –559, Aug. 2011.
[24] D. Zhang, A. Bhide, and A. Alvandpour. Design of CMOS sampling switch for
ultra-low power ADCs in biomedical applications. In NORCHIP, 2010, pages 1
–4, Nov. 2010.
[25] C.J.B. Fayomi and G.W. Roberts. Design and characterization of low-voltage
analog switch without the need for clock boosting. In Midwest Symposium on
Circuits and Systems (MWSCAS), volume 3, pages 315–318, July 2004.
[26] K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand. Leakage current
mechanisms and leakage reduction techniques in deep-submicrometer CMOS
circuits. Proceedings of the IEEE, 91(2):305 – 327, Feb. 2003.
[27] T. Wakimoto, H. Li, and K. Murase. Statistical analysis on the effect of capacitance mismatch in a high-resolution successive-approximation ADC. IEEJ
Trans. on Electrical and Electronic Engineering, 6:s89–s93, 2011.
[28] A. Nikoozadeh and B. Murmann. An analysis of latch comparator offset due
to load capacitor mismatch. IEEE Transactions on Circuits and Systems II:
Express Briefs, 53(12):1398 –1402, Dec. 2006.
[29] P. Nuzzo, F. De Bernardinis, P. Terreni, and G. Van der Plas. Noise analysis of
regenerative comparators for reconfigurable ADC architectures. IEEE Transactions on Circuits and Systems I: Regular Papers, 55(6):1441 –1454, July
2008.
[30] J. Kim, B.S. Leibowitz, J. Ren, and C.J. Madden. Simulation and analysis of
random decision errors in clocked comparators. IEEE Transactions on Circuits
and Systems I: Regular Papers, 56(8):1844 –1857, Aug. 2009.
[31] T. Sundstrom, B. Murmann, and C. Svensson. Power dissipation bounds for
high-speed Nyquist analog-to-digital converters. IEEE Transactions on Circuits
and Systems I: Regular Papers, 56(3):509 –518, March 2009.
[32] Christer Svensson and J. Wikner. Power consumption of analog circuits: a
tutorial. Analog Integrated Circuits and Signal Processing, 65:171–184, 2010.
“lic˙thesis” — 2012/8/1 — 12:14 — page 72 — #88
72
REFERENCES
[33] B. Razavi. Design of Analog CMOS Integrated Circuits. The McGraw-Hill,
2001.
[34] C.L. Portmann and H.Y. Meng. Metastability in CMOS library elements in
reduced supply and technology scaled applications. IEEE Journal of Solid-State
Circuits, 30(1):39 –46, Jan. 1995.
[35] Jan-Erik Eklund and Christer Svensson. Influence of metastability errors on
SNR in successive-approximation A/D converters. Analog Integrated Circuits
and Signal Processing, 26:183–190, 2001.
[36] B. Bechen, T. v. d. Boom, D. Weiler, and B.J. Hosticka. Theoretical and practical
minimum of the power consumption of 3 ADCs in SC technique. In European
Conference on Circuit Theory and Design (ECCTD), pages 444 –447, Aug.
2007.
[37] J.L. McCreary and P.R. Gray. All-MOS charge redistribution analog-to-digital
conversion techniques. i. IEEE Journal of Solid-State Circuits, 10(6):371 –379,
Dec. 1975.
[38] C C Enz and E A Vittoz. CMOS low-power analog circuit design. Emerging
Technologies Designing Low Power Digital Systems, 1(1):79–133, 1996.
[39] K. Ishida, K. Kanda, A. Tamtrakarn, H. Kawaguchi, and T. Sakurai. Managing
subthreshold leakage in charge-based analog circuits with low-VTH transistors
by analog T-switch (AT-switch) and super cut-off CMOS (SCCMOS). IEEE
Journal of Solid-State Circuits, 41(4):859 – 867, April 2006.
[40] G. Van der Plas and B. Verbruggen. A 150MS/s 133µW 7b ADC in 90nm
digital CMOS using a comparator-based asynchronous binary-search sub-ADC.
In IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), pages 242 –244, Feb. 2008.
[41] A methodology for the offset-simulation of comparators. http://www.
designers-guide.org/Analysis/comparator.pdf.
[42] S.-W.M. Chen and R.W. Brodersen. A 6-bit 600-MS/s 5.3-mW asynchronous
ADC in 0.13-µm CMOS. IEEE Journal of Solid-State Circuits, 41(12):2669
–2680, Dec. 2006.
[43] A. Rossi and G. Fucili. Nonredundant successive approximation register for
A/D converters. Electronics Letters, 32(12):1055 –1057, June 1996.
[44] S. Narendra, V. De, S. Borkar, D.A. Antoniadis, and A.P. Chandrakasan. Fullchip subthreshold leakage power prediction and reduction techniques for sub0.18-µm CMOS. IEEE Journal of Solid-State Circuits, 39(3):501 – 510, March
2004.
“lic˙thesis” — 2012/8/1 — 12:14 — page 73 — #89
REFERENCES
73
[45] J. Doernberg, H.-S. Lee, and D.A. Hodges. Full-speed testing of A/D converters.
IEEE Journal of Solid-State Circuits, 19(6):820 – 827, Dec. 1984.
[46] B. Bechen, D. Weiler, T. V. D. Boom, and B. J. Hosticka. A 10 bit very
low-power CMOS SAR-ADC for capacitive micro-mechanical pressure measurement in implants. In Advances in Radio Science, volume 4, pages 243 – 246,
2006.
[47] Xiaodan Zou, Xiaoyuan Xu, Libin Yao, and Yong Lian. A 1-v 450-nW fully
integrated programmable biomedical sensor interface chip. IEEE Journal of
Solid-State Circuits, 44(4):1067 –1077, April 2009.
[48] J. Sauerbrey, D. Schmitt-Landsiedel, and R. Thewes. A 0.5-V 1-µw successive
approximation ADC. IEEE Journal of Solid-State Circuits, 38(7):1261 – 1265,
July 2003.
[49] D.C. Daly and A.P. Chandrakasan. A 6-bit, 0.2 V to 0.9 V highly digital
flash ADC with comparator redundancy. IEEE Journal of Solid-State Circuits,
44(11):3030 –3038, Nov. 2009.
[50] J. Craninckx and G. Van der Plas. A 65fJ/conversion-step 0-to-50MS/s 0-to0.7mW 9b charge-sharing SAR ADC in 90nm digital CMOS. In IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC),
pages 246 –600, Feb. 2007.
[51] M. Yip and A.P. Chandrakasan. A resolution-reconfigurable 5-to-10b 0.4-to1V power scalable SAR ADC. In IEEE International Solid-State Circuits
Conference Digest of Technical Papers (ISSCC), pages 190 –192, Feb. 2011.