Download International Electrical Engineering Journal (IEEJ) Vol. 5 (2014) No.10, pp. 1586-1593

International Electrical Engineering Journal (IEEJ)
Vol. 5 (2014) No.10, pp. 1586-1593
ISSN 2078-2365
http://www.ieejournal.com/
A Fuzzy Logic Based D-STATCOM
Topology with Reduced VSI Rating, DC
Link Voltage and Filter Size
R.Manikanta, S.N.V.S.K Chaitanya
[email protected]
Abstract—The distribution static compensator (DSTATCOM)
is used for load compensation in power distribution network.
In this paper, a new DSTATCOM topology with non stiff
source is proposed. The proposed topology reduces the rating
of VSI and size of interfacing filter with enhanced current
compensation capabilities. It uses a series capacitor along with
the interfacing inductor to reduce the dc link voltage of the
DSTATCOM. Therefore the rating of VSI gets reduced as it is
directly proportional to dc link voltage. An LCL filter is used
to reduce the size of the interfacing filter. An LCL filter
provides better switching harmonics elimination capability
while using lower value of inductor as compared to
conventional L filter. The proposed topology will reduce size,
cost and rating of the DSTATCOM with enhanced current
compensation capability compared to conventional topology.
Detailed design aspects of the series capacitor and LCL Filter
parameters are discussed in this paper. A simulation study of
the traditional and proposed topology has been carried out
using Matlab/simulink platform. Finally, the proposed
topology is implemented with fuzzy logic and the results are
presented.
Index Terms— dc-link voltage, DSTATCOM, VSC, LCL
Filter, Series Capacitor, Nonstiff source.
I. INTRODUCTION
Power quality in distribution systems affects all connected
electrical and electronics equipments. Due to this there is
deviation in voltage, current, frequency of a particular
system and associated components [1]. In present days, use
of power converters in adjustable speed drives, power
supplies etc... are continuously increasing. These
equipments draw harmonic currents from AC mains and
increase the supply demands. These loads can be treated as
linear (lagging power factor loads), nonlinear (voltage or
current source type of harmonic generating loads),
unbalanced and mixed type of loads. Some of power quality
problems associated with these loads include poor power
factor, high harmonics, reactive power burden, load
unbalancing, voltage variation etc. A
Survey on power quality problems is discussed for suitable
corrective and preventive actions to identify these problems.
Different types of custom power devices are developed and
successfully implemented to compensate various power
quality problems in a distribution system. These custom
power devices are categorized as the DSTATCOM
(Distribution Static Compensator), DVR (Dynamic Voltage
Restorer) and UPQC (Unified Power Quality Conditioner)
[2]. The DSTATCOM is a shunt-active power filter
connected in distribution system. It injects harmonic and
reactive component of load current such that the unbalanced,
harmonic, and reactive loads are converted into balanced
linear resistive loads.
Generally, a DSTATCOM requires high power compared to
load power to operate in real time. The Power rating of the
SAPF is directly proportional to the compensated load
current and dc link voltage [3]. In traditional topology, the
dc link voltage has much higher value than the peak value of
the line to neutral voltage. By the use of high dc link voltage
the rating of VSI increases and IGBT switches must be
designed for this higher value of voltage and current. Finally
the size, cost, weight and power rating of VSI increases. In
traditional topology of DSTATCOM
L filter is used at
front of VSI for shaping the injected currents. L filter having
a bulky inductor and produces large voltage drop across it.
Due to which it requires higher value of dc link voltage for
better compensation. Therefore, L filter further increases the
cost, size and power rating VSI [4]. To decrease the size and
power rating of the SAPF, several topologies have been
proposed. In which an active filter is used with passive
components [5]–[6]. In [5], authors used a hybrid filter
tuned at seventh harmonic and it is designed for motor drive
applications only. In [6], authors used a capacitor which is
connected in series with interfacing filter to reduce the dc
link voltage. However, the reduction in dc link voltage is
limited due to large drop in L filter and it makes filter bulky,
bigger in size, and has a low slew rate for tracking the
reference currents. In [7]-[9] authors used LCL filter at the
front end of VSI instead of L filter. LCL filter provides
better reference tracking performance while using lower
value of passive components. This lower value of passive
1586
Manikanta and Chaitanya
A Fuzzy Logic Based D-STATCOM Topology with Reduced VSI Rating, DC Link Voltage and Filter Size
International Electrical Engineering Journal (IEEJ)
Vol. 5 (2014) No.10, pp. 1586-1593
ISSN 2078-2365
http://www.ieejournal.com/
components ensures that the voltage drop across them is
much less than the conventional L filter. Therefore, the dc
link voltage will decrease while using LCL filter. In [10],
author proposed new DSTATCOM topology which having
the advantages of both series capacitor and LCL filter. LCL
filter is placed at the front end of the VSI, which is followed
by the series capacitor. Proposed DSTATCOM topology
reduces the size of the passive components, rating of the dc
link voltage, and provides better reference current tracking
performance. In this paper a comparison is made between
traditional and proposed topology and Fuzzy logic control is
applied to proposed topology. Finally traditional and
proposed topologies by using PI controller & proposed
topology by using fuzzy controller are verified through
extensive simulation using MATLAB/SIMULINK and
results are also presented.
Fig. 1: Traditional DSTATCOM topology in distribution system.
II. THREE-PHASE TRADITIONAL AND PROPOSED
DSTATCOM TOPOLOGY
Three phase traditional and proposed topologies are
described in this section. Here Fig. 1 is considered as
traditional topology throughout this paper. Traditional
topology contains a three-phase four-wire, two-level,
neutral-point-clamped voltage source inverter. It uses two dc
storage capacitors but each leg of the VSI can be
independently controlled [11]. Vsabc and Isabc are source
voltages and currents of phases a, b, and c respectively. Rs
and Ls are the resistance and inductance of a feeder. Vtabc and
Ilabc are the load voltages and currents in phases a, b, and c
respectively. Here both linear and nonlinear loads are used.
Lf and Rf is the inductance and resistance of a VSI. Ifabc is
the DSTATCOM injected currents in respective phases. The
dc link capacitors are represented by Cdc1 =Cdc2 =Cdc,
whereas voltages maintained across them are Vdc1 = Vdc2 =
Vdc = Vdcref respectively.
Proposed topology is shown in Fig 2. Here an LCL filter is
placed in the place of L filter followed by a series capacitor
Cse. Here,R1 and L1 represents the resistance and inductance
at the filter side, R2and L2 represents the resistance and
inductance at the grid side and C is the capacitance of a
filter forming LCL filter in all three phases. if1abc and if2abc
are currents at filter and grid side in all three phases. Rd is
the damping resistance used in series with C to damp out
resonance and to provide passive damping to the overall
system, Vcabc and Icabc are voltages and currents through the
branch containing series C and Rd in three phases
respectively.
Fig. 2: Proposed DSTATCOM topology in distribution system.
III. REFERENCE CURRENT GENERATION
Here the reference currents (i*fa, i*fb, i*fc) are generated by
using instantaneous symmetrical component theory [12].
The reference currents generated by this theory are given as
follows
i∗!" = i!" − i∗!" = i!" −
!!"
i∗!" = i!" − i∗!" = i!" −
!!"
i∗!" = i!" − i∗!" = i!" −
!!"
∆!
∆!
∆!
P!"# + P!"## (1)
P!"# + P!"## P!"# + P!"## Where
Vsa, Vsb, Vsc are the voltages of a, b and c phases.
∆s=V2sa+V2sb+V2sc
Plav is the average load power and Ploss is the losses in VSI
which are computed as follows
P!"## = K ! V!"#$% − V!" + K !
P!"# =
!
!
V!"#$% − V!"
V!" i!" + V!" i!" + V!" i!" (2)
Where Vdcref and Vdc are the reference and actual
compensator voltage, Kp, and Ki, are the proportional and
integral gain.
1587
Manikanta and Chaitanya
A Fuzzy Logic Based D-STATCOM Topology with Reduced VSI Rating, DC Link Voltage and Filter Size
International Electrical Engineering Journal (IEEJ)
Vol. 5 (2014) No.10, pp. 1586-1593
ISSN 2078-2365
http://www.ieejournal.com/
By using above reference currents error signal e(t) is
obtained by subtracting the actual filter current from the
reference currents. This error signal is then fed to the relay
with the desired hysteresis band to obtain the switching
pulses for the inverter. The switching pulses are generated
according to the relationship given below.
if e(t) ≥ h, then upper switch of a leg is TURN ON and
lower switch is TURN OFF.
else If e(t) ≤ - h, then upper switch of a leg is TURN OFF
and lower switch is TURN ON.
IV. DESIGN OF TRADITIONAL TOPOLOGY
PARAMETERS
In practical constraints the dc link voltage should satisfy the
following condition:
(3)
Where VCErated is the maximum value of collector to emitter
voltage of the power switches. Vm is the peak value of AC
system voltage.
The dc link voltage can be written as
V!" = mV! = 1.6V!
(4) Therefore, for a line to neutral voltage of 230V, the Vdcref
will be 520 V.
2) Storage capacitance (Cdc): The value of dc capacitor can
be selected on the basis of voltage sag/swell or load
transients in the system and its ability to control the dc link
voltage under these conditions.
Suppose controller is working after n cycles. Therefore, nST
is the maximum energy that capacitor can supply to load or
absorb from the load and it will be equal to change in stored
energy of the capacitor.
!
!
!
!
C!" V!"#$%
− V!"
= nST
(5)
Where Vdc is maximum voltage variation from Vdcref during
transients, S is the Load rating and T is the system time
period.
The dc link capacitor is given as
!"#$
!
!!
!"#$% !!!"
(6)
For a load rating of 15 KVA and Vdcref is 520 V. The value
of capacitor is 3300µf.
3) Switching Frequency limits of VSI: The switching
frequency of VSI depends upon the type of power switches
used. The IGBT switches are generally preferred because
these switches having higher power handling capacity,
better switching speed, and it requires low power for
switching. The maximum switching frequency of IGBT
switches may be 20Khz.
The switching frequency can be expressed as
1) Reference dc link voltage( Vdcref): when the dc link
voltage is approximately equal to the 1.6 times the peak of
ac system voltage, the percentage total harmonic distortion
(THD) of the compensated source currents is minimum [13].
V! ≤ V!" ≤ V!"#$%&'
C!" =
f!"#$% =
!!!
!"!!
(7)
Where Lf is the interface inductance and h is the ripple in
current.
4) Interfacing inductor: The value of interfacing filter
plays a crucial role in tracking the reference currents. If the
value of interface inductance is large then the dc link
voltage should be very large enough to achieve good
compensation.
The interface inductor can be expressed as
L! =
!!!
!"!!"#$%
(8) For a maximum switching Frequency of 10 Khz, dc link
voltage of 520V and ripple current of 0.5A. The value of
interface inductance is 26mh.
IV. DESIGN OF PROPOSED TOPOLOGY
PARAMETERS
1) Design of LCL Filter: Generally the filters are designed
to satisfy the following two criteria
1) To ensure the dynamic behaviour of the current i.e
!
I
!" !"
=
!
I
!" !
(9) Where I!" is the harmonic current of the load and I! is the
current injected by the active filter.
2) To prevent the harmonic components generated by the
switching frequency.
LCL filter is used in the field of power electronic
applications, because it provides good attenuation with a
reasonable filter cost. While designing LCL filter
1588
Manikanta and Chaitanya
A Fuzzy Logic Based D-STATCOM Topology with Reduced VSI Rating, DC Link Voltage and Filter Size
International Electrical Engineering Journal (IEEJ)
Vol. 5 (2014) No.10, pp. 1586-1593
ISSN 2078-2365
http://www.ieejournal.com/
components constraints such as cost of inductor, resonance
frequency (fres), switching frequency (fsw) and choice of
damping resistor (Rd) must be considered [14].
Consider L1 of LCL filter is used. For a small ripple current
the switching frequency of IGBT decreases which lower the
losses. From equ(8) it can be seen that smaller ripple current
results in higher inductance value which causes more core
losses. So a current ripple of 20% is taken for compromising
ripple and inductor size. By using series capacitor the dc
link voltage as low as 110 V. placing a new value of ripple
current, dc link voltage Vdcnew and keep the switching
frequency fswmax constant at 10Khz in (8) the value of L1
becomes 2.75 mH. Finally L1 is taken 3mH to restrict
switching frequency below 10 Khz. L1 is chosen to
attenuate lower order harmonics. L2 and C need to be
designed for elimination of higher order harmonics.
Consider the capacitance of LCL filter is used. If the
reactance of capacitor is too much high then the high
frequency harmonics that flow through the shunt capacitor
branch is not enough [15]. As a result high frequency
harmonic currents flow in to power network, Which in turn
compensated by larger inductor. If the reactance of capacitor
is too small it will provide low impedance path for
harmonics but it will draw more reactive current from VSI
which further increases loss in L1 and IGBT switches. To
compromise these e requirements the value of capacitor is
10µF is chosen.
The resonance frequency of LCL filter is given by
f!"# =
Where
𝐾=
!
!!!
!"
!!! !
(10)
!!
!!
The Resonance frequency value is taken such that it must be
greater than the highest order of harmonics current to be
compensated. Suppose the highest order harmonics to be
compensated is 40 and taking a safety factor of 20%, fres
comes out to be 2400 Hz. The value of k is obtained from
equ(10) by substituting the values of fres, L1 and C is 0.172.
The value of L2 is obtained by knowing the values of L1 and
K is 0.6mH. At fres the equivalent impedance of the LCL
filter approaches to zero and system becomes unstable. But,
it can be prevented by placing a resistance (Rd) in series
with the capacitor. At fres the reactance offered by C is 6.63
Ω. Due to this lower reactance losses will increase. Taking
these into consideration, a resistance of 15 Ω, which is two
times the reactance offered by C at resonance, is chosen.
2) Series Capacitor: The purpose of designing Cse is that it
should provide a low impedance path for the fundamental
frequency current component and high impedance path for
the lower order harmonics. In simplified circuit, R1, R2, L1,
L2 and Cse are connected in series. In this case the
fundamental current supplied by the filter is
I!" =
!!"#$ !!!"
!! !! !!" !!!"#
(11) Where
Rf=R1+R2
Xl1=ω1(L1+L2)
Xse1=1/ ω1Cse
Vt1 is fundamental rms PCC voltage
Vinv1 is fundamental rms voltage at VSI terminal
V!"#$ =
!!"
(12)
!
After Simplification (11) becomes
I!" =
!!"#$ !!!" !! !! !!"#$ !!!" !!" !!!"#
!
!!
! ! !!" !!!"#
(13) Interfacing resistances are very small compared to reactive
part so it can be neglected. The imaginary part magnitude of
the If1 will be
I! I!" = −
!!"#$ !!!"
!!" !!!"#
(14) From equ(14) it can be observed that to inject reactive
current from compensator to PCC, the fundamental rms
voltage per phase available at the VSI terminal should be
greater
than
the
terminal
voltage.
Otherwise,
thecompensation will not be satisfactory. In Traditional
topology series capacitor is absent, so maximum injected
current only depends upon the dc link voltage (Xl1 and Vt1
are fixed). Therefore, dc voltage is maintained at much
higher value than the terminal voltage. When capacitor is
connected in series with filter the total impedance provided
by compensator decreases. Therefore, for same reactive
current injection the dc link voltage should be reduced from
its reference value.The value of series capacitor depends
upon the maximum reactive current of filter and extent up to
what level we want to decrease the dc link voltage.
Maximum reactive current that a compensator can supply
should be same as that of maximum reactive current of the
load to achieve unity power factor at load terminal. The
Load current will be maximum when it having a minimum
impedance (Zlmin = Rlmin + jXlmin) i.e., at full load. Therefore
the maximum fundamental current drawn by the load in a
particular phase is given as
I!"#$ =
!!"
!!"#$ !!!!"#$
(15) 1589
Manikanta and Chaitanya
A Fuzzy Logic Based D-STATCOM Topology with Reduced VSI Rating, DC Link Voltage and Filter Size
International Electrical Engineering Journal (IEEJ)
Vol. 5 (2014) No.10, pp. 1586-1593
ISSN 2078-2365
http://www.ieejournal.com/
After simplification equ(15) The imaginary part of Ilmax will
be
I! I!"#$ = −
!!"#$ !!"
(16) !!
!"#$
Equating imaginary currents of filter and load i.e
equ(14)=equ(16) then we got
!!" !!"#$
!!
!"#$
!!"#$ !!!"
=
(17) !!" !!!"#
After simplification of equ(17) the reactance of capacitor is
given by
X !"# = X !" −
!!"#$ !!!"
!!"#$ !!!"!
!"#$
(18) Fig 3: Fuzzy controller
In Fuzzy Logic controller firstly the input values will be
converting to fuzzy variables. This is called Fuzzification.
After Fuzzification, these Fuzzy inputs enter to rule base or
interface engine and then outputs are sent to defuzzification
to calculate the final outputs.
Where
Ilmax=Vt1 /Zlmin
Pflmin =Rlmin/Zlmin
The equ(17) is used when the load impedances are known
for calculation of capacitance but in practical situations
name plate details will be given in that case equ(18) is used.
The value of series capacitor is found to be 65 µF for dc
link voltage of 110V.
V. FUZZY CONTROLLER
Fig 4: Fuzzy control Block diagram
To convert these numerical variables into linguistic
variables, the following seven fuzzy sets or levels are
chosen as: NL (negative Large), NM (negative medium), NS
(negative small), ZE (zero), PL (positive Large), PM
(positive medium), and PS (positive small).
In a fuzzy logic controller, the control action is obtained
from the evaluation of a set of simple linguistic rules. The
implementation of the rules requires a thorough
understanding of the process to be controlled, but it does not
require any mathematical model of the system.
In this paper, fuzzy logic control is used to control the dc
link voltage of the DSTATCOM. The control scheme
consists of Fuzzy controller, limiter, and three phase
symmetrical component theory for generation of reference
currents and Hysteresis current control theory for generation
of switching signals [16]. The peak value of reference
currents is estimated by controlling the DC link voltage. The
actual capacitor voltage is compared with a reference
voltage. Then the error signal is processed through a Fuzzy
controller, which contributes to zero steady state error in
tracking the reference current signal.
Fig 5: Control Rules
Fuzzification: The process of converting a numerical
variable (real number) into a linguistic variable (fuzzy
number) is called fuzzification.
De-fuzzification: The Process of converting fuzzified
output into a crisp value. From the rules of FLC it generate
required output in a linguistic variable (Fuzzy Number),
according to our requirement these linguistic variables have
to be transformed to crisp output (Real number).
1590
Manikanta and Chaitanya
A Fuzzy Logic Based D-STATCOM Topology with Reduced VSI Rating, DC Link Voltage and Filter Size
International Electrical Engineering Journal (IEEJ)
Vol. 5 (2014) No.10, pp. 1586-1593
ISSN 2078-2365
http://www.ieejournal.com/
Database: The Database which stores the definition of the
membership Function required by fuzzifier and defuzzifier.
injected currents by VSI. Fig 8(d) shows the voltage across
upper and lower capacitors. Fig 8(e) shows the THD
analysis of source current.
V. MATLAB/SIMULINK RESULTS
Fig 7: Simulation diagram of traditional topology
15
10
Source Current(Amp)
The advantages of proposed topology over traditional
topology are that it uses lower value of interfacing filter
inductor and lower rating of VSI, lower overall cost, size
and weight. All these advantages are verified in
Matlab/simulink software. The Performance comparison of
two topologies regarding percentage total harmonic
distortion (THD) and comparison of VSI parameters are
illustrated in Table I&II.
Fig. 6(a) shows the three phase source currents without
compensation which are same as load currents. These
currents are distorted and unbalanced due to presence of
unbalanced linear and non-linear loads. Fig. 6(b) shows the
three phase terminal voltages which are also distorted and
unbalanced due to presence of feeder impedance. Fig6(c)
shows the THD analysis of a source current without
compensation.
5
0
-5
-10
-15
1
1.02
1.04
1.06
1.08
1.1
Time(Sec)
1.12
1.14
1.16
1.18
1.2
1.02
1.04
1.06
1.08
1.1
Time(Sec)
1.12
1.14
1.16
1.18
1.2
1.02
1.04
1.06
1.08
1.1
Time(Sec)
1.12
1.14
1.16
1.18
1.2
1.02
1.04
1.06
1.08
1.1
Time(Sec)
1.12
1.14
1.16
1.18
1.2
1.02
1.04
1.06
1.08
1.1
Time(Sec)
1.12
1.14
1.16
1.18
1.2
0
0.2
0.4
0.6
0.8
1
Time(Sec)
1.2
1.4
1.6
1.8
2
0
0.2
0.4
0.6
0.8
1
Time(Sec)
1.2
1.4
1.6
1.8
2
15
400
300
5
200
0
Source Voltage(Volts)
Source Current(Amp)
10
-5
-10
-15
1
1.02
1.04
1.06
1.08
1.1
Time(Sec)
1.12
1.14
1.16
1.18
100
0
-100
-200
1.2
-300
400
-400
0
-100
-200
-300
-400
1
1.02
1.04
1.06
1.08
1.1
Time(sec)
1.12
1.14
1.16
1.18
1.2
Fig.3: Before compensation (a) Source currents and (b) Terminal voltages
(c) THD Analysis.
The simulation diagram of traditional topology with PI
controller is shown in Fig 7. Fig 8(a) shows the three phase
source currents, which are sinusoidal and balanced. Fig 8(b)
shows the three phase terminal voltages which are also
sinusoidal and balanced. Fig 8(c) shows the three phase
Dc Link Voltage 1(Volts)
100
Dc Link Voltage 2(Volts)
Source Voltage(Volts)
200
Filter Current(Amo) Filter Current(Amp) Filter Current(Amp)
300
1
10
0
-10
1
10
0
-10
1
10
0
-10
1
600
400
200
0
600
400
200
0
1591
Manikanta and Chaitanya
A Fuzzy Logic Based D-STATCOM Topology with Reduced VSI Rating, DC Link Voltage and Filter Size
International Electrical Engineering Journal (IEEJ)
Vol. 5 (2014) No.10, pp. 1586-1593
ISSN 2078-2365
http://www.ieejournal.com/
400
300
Source Voltage(Volts)
200
100
0
-100
-200
-300
DC Link Voltage 1(Amp)
The simulation diagram of proposed topology with PI
controller is shown in Fig 9. The parameters L1=3mH,
L2=0.6mH, C=10µF, Rd=15Ω, Cse=65µF and Vdc= 110V are
obtained based on designed procedure. Fig 10(a) shows the
three phase source currents, which are sinusoidal and
balanced and having less switching harmonics compared to
traditional topology. Fig 10(b) shows the three phase
terminal voltages which are also sinusoidal and balanced
and having less switching harmonics. Fig 10(c) shows the
three phase injected currents by VSI. Fig 10(d) shows the
voltage across upper and lower capacitors which are much
lower value than the traditional topology capacitor voltages.
Fig 10(e) shows the THD analysis of source current.
DC Link Voltage 2(Volts)
Fig 8: In Traditional Topology (a) Source currents, (b) Terminal voltages,
(c) DSTATCOM injected currents, and (d) Voltage across Capacitors (e)
THD Analysis
Filter Current(Amp) Filter Current(Amp) Filter Current(Amp)
-400
1
1.02
1.04
1.06
1.08
1.1
Time(Sec)
1.12
1.14
1.16
1.18
1.2
1.02
1.04
1.06
1.08
1.1
Time(Sec)
1.12
1.14
1.16
1.18
1.2
1.02
1.04
1.06
1.08
1.1
Time(Sec)
1.12
1.14
1.16
1.18
1.2
1
1.02
1.04
1.06
1.08
1.1
Time(Sec)
1.12
1.14
1.16
1.18
1.2
0
0.2
0.4
0.6
0.8
1
Time(Sec)
1.2
1.4
1.6
1.8
2
0
0.2
0.4
0.6
0.8
1
Time(Sec)
1.2
1.4
1.6
1.8
2
10
0
-10
1
10
0
-10
1
10
0
-10
120
100
80
60
40
20
0
120
100
80
60
40
20
0
Fig 9: Simulation diagram of Proposed Topology
Fig 10: In Proposed Topology (a) Source currents, (b) Terminal voltages,
(c) DSTATCOM injected currents, and (d) Voltage across Capacitors (e)
THD Analysis.
15
Source Current(Amp)
10
5
0
-5
-10
-15
1
1.02
1.04
1.06
1.08
1.1
Time(Sec)
1.12
1.14
1.16
1.18
1.2
Now the Proposed topology is implementing with Fuzzy
logic controller. This controller controls the dc link at
desired value by using Fuzzy logic rules there by controlling
the injected currents. By using this controller we can
achieve better harmonic elimination compared to PI
controller. Fig 11 shows the THD analysis of a source
current. Table I shows the comparison of THD of traditional
and proposed topology with PI controller and proposed
topology with Fuzzy controller, Table II shows the
1592
Manikanta and Chaitanya
A Fuzzy Logic Based D-STATCOM Topology with Reduced VSI Rating, DC Link Voltage and Filter Size
International Electrical Engineering Journal (IEEJ)
Vol. 5 (2014) No.10, pp. 1586-1593
ISSN 2078-2365
http://www.ieejournal.com/
comparison of VSI parameters of traditional and proposed
topology.
topology is implemented with Fuzzy logic which gives
better compensation than PI controller. Therefore, the size,
cost, weight, and power rating of the DSTATCOM will be
greatly reduced compared to traditional topology.
REFERENCES
Fig 11: THD Analysis in proposed topology by using Fuzzy Controller
TABLE I
PERCENTAGE THDS IN SOURCE CURRENTS AND TERMINAL
VOLTAGES
System
Configuration
Without
Compensation
Compensation with
Traditional
Topology by using
PI controller
Compensation with
Proposed Topology
by using PI
controller
Compensation with
Proposed Topology
by using Fuzzy
controller
isa
isb
isc
Vta
Vtb
Vtc
10.97
12.56
13.73
7.29
7.42
7.47
1.49
1.60
2.00
3.51
4.06
3.51
0.74
0.81
1.38
0.49
0.51
1.02
0.43
0.49
0.93
0.47
0.49
1.02
TABLE II
COMPARISON OF VSI PARAMETERS
Parameters
Traditional
Topology
Proposed
Topology
Percentage
Reduction
Inductor Value
Voltage at DC bus
26mH
1040V
3.6mH
220V
86.15
78.85
VI. CONCLUSION
A new hybrid DSTATCOM topology comprising of a LCL
filter at the front end of voltage source inverter followed by
a series capacitor has been proposed in this paper. The
designed parameters of Traditional and Proposed topologies
are presented. The Traditional and proposed topologies by
using PI controller are validated through simulation in a 3-ϕ
distribution system with the neutral clamped DSTATCOM
topology. It is observed that the proposed topology provides
better current compensation compared to traditional
topology by using a much lower value of dc link voltage as
well as interfacing filter inductor. Finally the Proposed
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1593
Manikanta and Chaitanya
A Fuzzy Logic Based D-STATCOM Topology with Reduced VSI Rating, DC Link Voltage and Filter Size