Download a 4/8 Channel Fault-Protected Analog Multiplexers ADG508F/ADG509F/ADG528F*

a
FEATURES
Low On Resistance (300 ⍀ Typ)
Fast Switching Times
tON 250 ns Max
t OFF 250 ns Max
Low Power Dissipation (3.3 mW Max)
Fault and Overvoltage Protection (–40 V to +55 V)
All Switches OFF with Power Supply OFF
Analog Output of ON Channel Clamped within Power
Supplies if an Overvoltage Occurs
Latch-Up Proof Construction
Break before Make Construction
TTL and CMOS Compatible Inputs
4/8 Channel Fault-Protected
Analog Multiplexers
ADG508F/ADG509F/ADG528F*
FUNCTIONAL BLOCK DIAGRAMS
ADG508F/ADG528F
ADG509F
S1
S1A
DA
S4A
D
S1B
DB
S4B
S8
ADG528F
ONLY
WR
RS
APPLICATIONS
Existing Multiplexer Applications (Both Fault-Protected
and Nonfault-Protected)
New Designs Requiring Multiplexer Functions
1 OF 8
DECODER
1 OF 4
DECODER
A0 A1 A2 EN
A0 A1 EN
GENERAL DESCRIPTION
2. ON channel turns off while fault exists.
The ADG508F, ADG509F, and ADG528F are CMOS analog
multiplexers, the ADG508F and ADG528F comprising eight
single channels and the ADG509F comprising four differential
channels. These multiplexers provide fault protection. Using a
series n-channel, p-channel, n-channel MOSFET structure,
both device and signal source protection is provided in the event
of an overvoltage or power loss. The multiplexer can withstand
continuous overvoltage inputs from –40 V to +55 V. During
fault conditions, the multiplexer input (or output) appears as an
open circuit and only a few nanoamperes of leakage current will
flow. This protects not only the multiplexer and the circuitry
driven by the multiplexer, but also protects the sensors or signal
sources that drive the multiplexer.
3. Low RON.
Model
Temperature Range
Package Option*
The ADG508F and ADG528F switch one of eight inputs to a
common output as determined by the 3-bit binary address lines
A0, A1, and A2. The ADG509F switches one of four differential inputs to a common differential output as determined by the
2-bit binary address lines A0 and A1. The ADG528F has on-chip
address and control latches that facilitate microprocessor interfacing. An EN input on each device is used to enable or disable
the device. When disabled, all channels are switched OFF.
ADG508FBN
ADG508FBRN
ADG508FBRW
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
N-16
R-16N
R-16W
ADG509FBN
ADG509FBRN
ADG509FBRW
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
N-16
R-16N
R-16W
ADG528FBN
ADG528FBP
–40°C to +85°C
–40°C to +85°C
N-18
P-20A
4. Fast Switching Times.
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PRODUCT HIGHLIGHTS
1. Fault Protection.
The ADG508F/ADG509F/ADG528F can withstand continuous voltage inputs from –40 V to +55 V. When a fault
occurs due to the power supplies being turned off, all the
channels are turned off and only a leakage current of a few
nanoamperes flows.
5. Break-Before-Make Switching.
Switches are guaranteed break-before-make so that input
signals are protected against momentary shorting.
6. Trench Isolation Eliminates Latch-up.
A dielectric trench separates the p and n-channel MOSFETs
thereby preventing latch-up.
ORDERING GUIDE
*N = Plastic DIP; P = Plastic Leaded Chip Carrier (PLCC); RN = 0.15" Small
Outline IC (SOIC), RW = 0.3" Small Outline IC (SOIC).
*Patent Pending.
REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001
ADG508F/ADG509F/ADG528F–SPECIFICATIONS
Dual Supply (V
DD =
+15 V ⴞ 10%, VSS = –15 V ⴞ 10%, GND = 0 V, unless otherwise noted)
B Version
–40ⴗC to
+25ⴗC
+85ⴗC
Parameter
ANALOG SWITCH
Analog Signal Range
300
RON
RON Drift
RON Match
LEAKAGE CURRENTS
Source OFF Leakage IS (OFF)
Drain OFF Leakage I D (OFF)
ADG508F/ADG528F
ADG509F
Channel ON Leakage I D, IS (ON)
ADG508F/ADG528F
ADG509F
FAULT
Output Leakage Current
(With Overvoltage)
Input Leakage Current
(With Overvoltage)
Input Leakage Current
(With Power Supplies OFF)
VSS + 3
VDD – 1.5
350
V min
V max
Ω typ
400
Ω max
0.6
5
± 0.02
±1
± 0.04
±1
±1
± 0.04
±1
±1
± 0.02
±2
± 0.005
±2
± 0.001
±2
Unit
%/°C typ
% max
± 50
± 60
± 30
± 60
± 30
±2
Test Conditions/Comments
–10 V < VS < +10 V, IS = 1 mA;
VDD = +15 V ± 10%, VSS = –15 V ± 10%
–10 V < VS < +10 V, IS = 1 mA;
VDD = +15 V ± 5%, VSS = –15 V ± 5%
VS = 0 V, IS = 1 mA
VS = 0 V, IS = 1 mA
nA typ
nA max
nA typ
nA max
nA max
nA typ
nA max
nA max
VD = ± 10 V, VS = ⫿10 V;
Test Circuit 2
VD = ± 10 V, VS = ⫿10 V;
Test Circuit 3
nA typ
µA max
µA typ
µA max
µA typ
µA max
VS = ± 33 V, VD = 0 V, Test Circuit 3
VS = VD = ± 10 V;
Test Circuit 4
VS = ± 25 V, VD = ⫿10 V, Test Circuit 5
VS = ± 25 V, VD = VEN = A0, A1, A2 = 0 V
Test Circuit 6
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DIGITAL INPUTS
Input High Voltage, V INH
Input Low Voltage, VINL
Input Current, IINL or IINH
CIN, Digital Input Capacitance
DYNAMIC CHARACTERISTICS 1
tTRANSITION
tOPEN
tON (EN, WR)
tOFF (EN, RS)
tSETT, Settling Time
0.1%
0.01%
ADG528F Only
tW, Write Pulsewidth
tS, Address, Enable Setup Time
tH, Address, Enable Hold Time
tRS, Reset Pulsewidth
Charge Injection
OFF Isolation
CS (OFF)
CD (OFF)
ADG508F/ADG528F
ADG509F
POWER REQUIREMENTS
IDD
ISS
2.4
0.8
±1
V min
V max
µA max
pF typ
5
200
300
50
25
200
250
200
250
VIN = 0 or VDD
400
ns typ
ns max
ns typ
ns min
ns typ
ns max
ns typ
ns max
RL = 1 MΩ, CL = 35 pF;
VS1 = ± 10 V, VS8 = ⫿10 V; Test Circuit 7
RL = 1 kΩ, CL = 35 pF;
VS = 5 V; Test Circuit 8
RL = 1 kΩ, CL = 35 pF;
VS = 5 V; Test Circuit 9
RL = 1 kΩ, CL = 35 pF;
VS = 5 V; Test Circuit 9
1
2.5
µs typ
µs typ
RL = 1 kΩ, CL = 35 pF;
VS = 5 V
120
100
10
100
4
68
50
5
ns min
ns min
ns min
ns min
pC typ
dB typ
dB min
pF typ
50
25
pF typ
pF typ
100
0.1
0.1
400
10
400
0.2
0.1
mA max
mA max
VS = 0 V, RS = 0 Ω, CL= 1 nF; Test Circuit 12
RL = 1 kΩ, CL = 15 pF, f = 100 kHz;
VS = 7 V rms; Test Circuit 13
VIN = 0 V or 5 V
NOTES
1
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
–2–
REV. D
ADG508F/ADG509F/ADG528F
Table I. ADG508F Truth Table
Table II. ADG509F Truth Table
A2
A1
A0
EN
ON Switch
A1
A0
EN
ON Switch Pair
X
0
0
0
0
1
1
1
1
X
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
NONE
1
2
3
4
5
6
7
8
X
0
0
1
1
X
0
1
0
1
0
1
1
1
1
NONE
1
2
3
4
X = Don’t Care
X = Don’t Care
Table III. ADG528F Truth Table
A2
A1
A0
EN
WR
RS
ON Switch
X
X
X
0
0
0
0
1
1
1
1
X
X
X
0
0
1
1
0
0
1
1
X
X
X
0
1
0
1
0
1
0
1
X
X
0
1
1
1
1
1
1
1
1
g
X
0
0
0
0
0
0
0
0
0
1
0
1
1
1
1
1
1
1
1
1
Retains Previous Switch Condition
NONE (Address and Enable Latches Cleared)
NONE
1
2
3
4
5
6
7
8
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X = Don’t Care
TIMING DIAGRAMS (ADG528F)
3V
3V
WR
RS
50%
50%
50%
0V
tRS
tOFF (RS)
tW
tS
tH
3V
A0, A1, A2
EN
VO
0.8VO
SWITCH
OUTPUT
2V
0.8V
0V
0V
Figure 1.
Figure 2.
Figure 1 shows the timing sequence for latching the switch
address and enable inputs. The latches are level sensitive; therefore, while WR is held low, the latches are transparent and the
switches respond to the address and enable inputs. This input
data is latched on the rising edge of WR.
REV. D
50%
0V
Figure 2 shows the Reset Pulsewidth, tRS, and the Reset Turnoff Time, tOFF (RS).
Note: All digital input signals rise and fall times are measured
from 10% to 90% of 3 V. tR = tF = 20 ns.
–3–
ADG508F/ADG509F/ADG528F
ADG508F/ADG509F PIN CONFIGURATIONS
ABSOLUTE MAXIMUM RATINGS*
(TA = +25°C unless otherwise noted)
DIP/SOIC
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 V
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +25 V
VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –25 V
VEN, VA Digital Input . . . . . . . – 0.3 V to VDD + 2 V or 20 mA,
Whichever Occurs First
VS, Analog Input Overvoltage with Power ON . . . . . VSS – 25 V
to VDD + 40 V
VS, Analog Input Overvoltage with Power OFF
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–40 V to +55 V
Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . 20 mA
Peak Current, S or D
(Pulsed at 1 ms, 10% Duty Cycle max) . . . . . . . . . . . 40 mA
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Plastic Package
θJA, Thermal Impedance
16-Lead . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117°C
18-Lead . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110°C
Lead Temperature, Soldering (10 sec) . . . . . . . . . . . . 260°C
SOIC Package
θJA, Thermal Impedance
Narrow Body . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77°C/W
Wide Body . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
PLCC Package
θJA, Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 90°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
DIP/SOIC
A0
1
16 A1
A0
1
16 A1
EN
2
15 A2
EN
2
15 GND
VSS
3
14 GND
VSS
3
S1
4
ADG508F
13 VDD
S1A
4
S2
5
TOP VIEW
(Not to Scale) 12 S5
S2A
5
13 S1B
TOP VIEW
(Not to Scale) 12 S2B
S3
6
11 S6
S3A
6
11 S3B
S4
7
10 S7
S4A
7
10 S4B
D
8
9
DA
8
9
S8
14 VDD
ADG509F
DB
ADG528F PIN CONFIGURATIONS
16 A2
4
ADG528F
15 GND
S1
5
S2
6
TOP VIEW
14 VDD
(Not to Scale)
13 S5
7
12 S6
S4
8
11 S7
D
9
10 S8
RS
A1
20 19
18 A2
EN 4
VSS 5
ADG528F
17 GND
S1 6
TOP VIEW
(Not to Scale)
16 VDD
S2 7
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S3
1
15 S5
S3 8
14 S6
9
10 11 12 13
S7
3
2
S8
EN
VSS
3
WR
17 A1
NC
18 RS
2
D
1
A0
S4
WR
NC
PLCC
A0
DIP
NC = NO CONNECT
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADG508F/ADG509F/ADG528F features proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
–4–
WARNING!
ESD SENSITIVE DEVICE
REV. D
ADG508F/ADG509F/ADG528F
TERMINOLOGY
Typical Performance Characteristics
Most Positive Power Supply Potential.
VSS
Most Negative Power Supply Potential.
2000
GND
Ground (0 V) Reference.
1750
RON
Ohmic Resistance between D and S.
1500
RON Drift
Change in RON when temperature changes
by one degree Celsius.
1250
RON – ⍀
VDD
Difference between the RON of any two channels.
IS (OFF)
Source leakage current when the switch is off.
750
ID (OFF)
Drain leakage current when the switch is off.
500
ID, IS (ON)
Channel leakage current when the switch is on.
250
VD (VS)
Analog Voltage on Terminals D, S.
CS (OFF)
Channel input capacitance for “OFF” condition.
CD (OFF)
Channel output capacitance for “OFF” condition.
CD, CS (ON)
“ON” Switch Capacitance.
CIN
Digital Input Capacitance.
tON (EN)
Delay time between the 50% and 90% points of
the digital input and switch “ON” condition.
tTRANSITION
Delay time between the 50% and 90% points
of the digital inputs and the switch “ON”
condition when switching from one address
state to another.
VDD = +10V
VSS = –10V
VDD = +15V
VSS = –15V
–10
–5
0
VD (VS) – V
5
10
15
TPC 1. On Resistance as a Function of VD (VS)
1m
VDD = 0V
VSS = 0V
VD = 0V
100␮
10␮
1␮
100n
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“OFF” time measured between 80% points of
both switches when switching from one
address state to another.
VINL
Maximum input voltage for Logic “0”.
VINH
Minimum input voltage for Logic “1”.
IINL (IINH)
Input current of the digital input.
Off Isolation
A measure of unwanted signal coupling
through an “OFF” channel.
Charge
Injection
A measure of the glitch impulse transferred
from the digital input to the analog output
during switching.
IDD
Positive Supply Current.
ISS
Negative Supply Current.
10n
OPERATING RANGE
1n
100p
10p
1p
–50 –40 –30 –20 –10
0
10
20
30
VIN – INPUT VOLTAGE – V
40
50
60
TPC 2. Input Leakage Current as a Function of VS
(Power Supplies OFF) During Overvoltage Conditions
1m
VDD = +15V
VSS = –15V
VD = 0V
100␮
I D – INPUT LEAKAGE – A
tOPEN
0
–15
IS – INPUT LEAKAGE – A
Delay time between the 50% and 90% points of
the digital input and switch “OFF” condition.
VDD = +5V
VSS = –5V
1000
RON Match
tOFF (EN)
TA = 25ⴗC
10␮
1␮
100n
10n
OPERATING RANGE
1n
100p
10p
1p
–50 –40 –30
–20 –10
0
10
20
30
40
50
60
VIN – INPUT VOLTAGE – V
TPC 3. Output Leakage Current as a Function of VS
(Power Supplies ON) During Overvoltage Conditions
REV. D
–5–
ADG508F/ADG509F/ADG528F
100
2000
1750
1500
RON – ⍀
1250
1000
750
85 C
500
125 C
VDD = +15V
VSS = –15V
VD = +10V
VS = –10V
10
LEAKAGE CURRENTS – nA
VDD = +15V
VSS = –15V
ID (OFF)
1
IS (OFF)
0.1
ID (ON)
250
25 C
0
–15
–10
–5
0
VD (VS) – V
5
10
0.01
25
15
TPC 4. On Resistance as a Function of VD (VS) for
Different Temperatures
65
75
85
95
TEMPERATURE – ⴗC
10␮
115
125
240
220
1␮
tON (EN)
200
100n
10n
OPERATING RANGE
180
tTRANSITION
160
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1n
140
100p
tOFF (EN)
120
10p
1p
–50 –40
–30 –20 –10
0
10
20 30
VIN – INPUT VOLTAGE – V
40
50
100
10
60
TPC 5. Input Leakage Current as a Function of VS
(Power Supplies ON) During Overvoltage Conditions
11
12
13
VSUPPLY – V
14
15
TPC 8. Switching Time vs. Power Supply
0.3
280
260
VDD = +15V
VSS = –15V
TA = 25ⴗC
240
IS (OFF)
VDD = +15V
VSS = –15V
VIN = +5V
tON (EN)
220
0.1
t – ns
ID (OFF)
0.0
200
tTRANSITION
180
160
ID (ON)
140
–0.1
120
–0.2
–14
105
VIN = 2V
VDD = +15V
VSS = –15V
VD = 0V
t – ns
IS – INPUT LEAKAGE – A
55
260
100␮
LEAKAGE CURRENTS – nA
45
TPC 7. Leakage Currents as a Function of Temperature
1m
0.2
35
–10
–6
–2
2
VS, VD – V
6
10
100
25
14
TPC 6. Leakage Currents as a Function of VD (VS)
tOFF (EN)
45
65
85
TEMPERATURE – ⴗC
105
125
TPC 9. Switching Time vs. Temperature
–6–
REV. D
ADG508F/ADG509F/ADG528F
threshold voltage (VTN). When a voltage more negative than VSS
is applied to the multiplexer, the p-channel MOSFET will turn
off since the analog input is more negative than the difference
between VSS and the p-channel threshold voltage (VTP). Since
VTN is nominally 1.5 V and VTP is typically 3 V, the analog
input range to the multiplexer is limited to –12 V to +13.5 V
when a ± 15 V power supply is used.
THEORY OF OPERATION
The ADG508F/ADG509F/ADG528F multiplexers are capable
of withstanding overvoltages from –40 V to +55 V, irrespective
of whether the power supplies are present or not. Each channel of
the multiplexer consists of an n-channel MOSFET, a p-channel
MOSFET, and an n-channel MOSFET, connected in series.
When the analog input exceeds the power supplies, one of the
MOSFETs will switch off, limiting the current to submicroamp
levels, thereby preventing the overvoltage from damaging any
circuitry following the multiplexer. Figure 3 illustrates the channel
architecture that enables these multiplexers to withstand
continuous overvoltages.
When the power supplies are present but the channel is off,
again either the p-channel MOSFET or one of the n-channel
MOSFETs will turn off when an overvoltage occurs.
Finally, when the power supplies are off, the gate of each
MOSFET will be at ground. A negative overvoltage switches
on the first n-channel MOSFET but the bias produced by the
overvoltage causes the p-channel MOSFET to remain turned
off. With a positive overvoltage, the first MOSFET in the
series will remain off since the gate to source voltage applied to
this MOSFET is negative.
When an analog input of VSS + 3 V to VDD – 1.5 V is applied to
the ADG508F/ADG509F/ADG528F, the multiplexer behaves
as a standard multiplexer, with specifications similar to a standard multiplexer, for example, the on-resistance is 400 Ω
maximum. However, when an overvoltage is applied to the
device, one of the three MOSFETs will turn off.
Figures 3 to 6 show the conditions of the three MOSFETs for
the various overvoltage situations. When the analog input applied
to an ON channel approaches the positive power supply line, the
n-channel MOSFET turns OFF since the voltage on the analog
input exceeds the difference between VDD and the n-channel
Q1
+55V
OVERVOLTAGE
Q2
During fault conditions, the leakage current into and out of the
ADG508F/ADG509F/ADG528F is limited to a few microamps.
This protects the multiplexer and succeeding circuitry from
over stresses as well as protecting the signal sources which
drive the multiplexer. Also, the other channels of the multiplexer will be undisturbed by the overvoltage and will continue
to operate normally.
Q3
+55V
OVERVOLTAGE
Q1
Q2
Q3
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n-CHANNEL
MOSFET IS
OFF
VDD
n-CHANNEL
MOSFET IS
OFF
VSS
Figure 5. +55 V Overvoltage with Power OFF
Figure 3. +55 V Overvoltage Input to the ON Channel
–40V
OVERVOLTAGE
n-CHANNEL
MOSFET IS
ON
VSS
Q1
Q2
VDD
–40V
OVERVOLTAGE
Q3
n-CHANNEL
MOSFET IS
ON
p-CHANNEL
MOSFET IS
OFF
Q2
Q3
p-CHANNEL
MOSFET IS
OFF
Figure 6. –40 V Overvoltage with Power OFF
Figure 4. –40 V Overvoltage on an OFF Channel with
Multiplexer Power ON
REV. D
Q1
–7–
ADG508F/ADG509F/ADG528F
Test Circuits
IDS
VDD
VSS
VDD
VSS
ID (ON)
D
S1
V1
A
S2
VD
S8
D
S
2.4V
EN
VS
VS
RON = V1 /IDS
Test Circuit 4. ID (ON)
Test Circuit 1. On Resistance
VDD
VSS
A
IS (OFF)
VDD
VDD
VSS
VDD
VSS
S1
D
S2
VSS
S8
S1
A
S2
VS
EN
D
VD
0.8V
VS
S8
0.8V
EN
VD
Test Circuit 5. Input Leakage Current
(with Overvoltage)
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Test Circuit 2. IS (OFF)
VDD
VSS
0V
0V
0V
VDD
VSS
A2
A1
VSS
VDD
A0
S1
RS
A
S8
VS
D
GND
VD
0.8V
EN
A
S8
EN
ID (OFF)
D
S2
S1
ADG528F*
WR
VS
* SIMILAR CONNECTION FOR ADG508F/ADG509F
Test Circuit 6. Input Leakage Current
(with Power Supplies OFF)
Test Circuit 3. ID (OFF)
VDD
VSS
3V
VDD
A2
VIN
50⍀
A1
EN
RS
S1
VS1
50%
50%
S2–S7
A0
2.4V
ADDRESS
DRIVE (VIN)
VSS
S8
VS8
ADG528F*
GND
D
WR
90%
VOUT
RL
1M⍀
CL
35pF
VOUT
90%
tTRANSITION
* SIMILAR CONNECTION FOR ADG508F/ADG509F
tTRANSITION
Test Circuit 7. Switching Time of Multiplexer, tTRANSITION
–8–
REV. D
ADG508F/ADG509F/ADG528F
VDD
VSS
3V
VIN
50⍀
VDD
A2
VSS
A1
S2–S7
A0
ADG528F*
S8
RS
2.4V
ADDRESS
DRIVE (VIN)
VS
S1
D
EN
VOUT
RL
1k⍀
WR
GND
VOUT
CL
35pF
80%
80%
tOPEN
* SIMILAR CONNECTION FOR ADG508F/ADG509F
Test Circuit 8. Break-Before-Make Delay, tOPEN
VDD
VSS
3V
VDD
A2
A1
S1
RS
50⍀
50%
50%
0V
tOFF (EN)
ADG528F*
VO
EN
VIN
VS
S2–S8
A0
2.4V
ENABLE
DRIVE (VIN)
VSS
D
GND
0.9VO
VOUT
RL
1k⍀
WR
CL
35pF
0.9VO
OUTPUT
0V
tON (EN)
* SIMILAR CONNECTION FOR ADG508F/ADG509F
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Test Circuit 9. Enable Delay, tON (EN), tOFF (EN)
VSS
VDD
3V
VDD
A2
S1
A1
A0
2.4V
0V
S2–S8
tON (WR)
EN
WR
VWR
50%
VS
ADG528F
VO
RS
VRS
WR
VSS
D
GND
VOUT
RL
1k⍀
CL
35pF
OUTPUT
0.2VO
0V
Test Circuit 10. Write Turn-On Time, tON (WR)
REV. D
–9–
ADG508F/ADG509F/ADG528F
VDD
VSS
3V
VSS
VDD
A2
RS
0V
S2–S8
A0
50%
50%
VS
S1
A1
tRS
tOFF (RS)
ADG528F
EN
2.4V
D
RS
RL
1k⍀
WR
GND
VIN
VO
VOUT
CL
35pF
0.8VO
SWITCH
OUTPUT
0V
Test Circuit 11. Reset Turn-Off Time, tOFF (RS)
VDD
VSS
VDD
A2
VSS
A1
A0
S
RS
RS
VIN
LOGIC
INPUT (VIN)
2.4V
ADG528F*
GND
0V
D
EN
VS
3V
VOUT
CL
1nF
⌬VOUT
VOUT
WR
Q INJ = CL x ⌬VOUT
* SIMILAR CONNECTION FOR ADG508F/ADG509F
www.BDTIC.com/ADI
Test Circuit 12. Charge Injection
VDD
VDD
A2
A1
A0
2.4V
S1
S8
VIN
ADG528F*
RS
VOUT
D
EN
GND WR VSS
RL
1k⍀
VSS
* SIMILAR CONNECTION FOR ADG508F/ADG509F
Test Circuit 13. OFF Isolation
–10–
REV. D
ADG508F/ADG509F/ADG528F
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
16-Lead Plastic (N-16)
16-Lead SOIC (R-16N)
(Narrow Body)
0.840 (21.34)
0.745 (18.92)
16
9
1
8
0.3937 (10.00)
0.3859 (9.80)
0.280 (7.11)
0.240 (6.10)
0.325 (8.25)
0.300 (7.62)
PIN 1
0.060 (1.52)
0.015 (0.38)
0.1574 (4.00)
0.1497 (3.80)
0.195 (4.95)
0.115 (2.93)
0.210 (5.33)
MAX
0.130
(3.30)
0.160 (4.06)
MIN
0.115 (2.93)
0.022 (0.558) 0.100 0.070 (1.77) SEATING
PLANE
(2.54)
0.045 (1.15)
0.014 (0.356)
BSC
PIN 1
16
9
1
8
0.050 (1.27)
BSC
0.015 (0.381)
0.008 (0.204)
0.0098 (0.25)
0.0040 (0.10)
0.2440 (6.20)
0.2284 (5.80)
0.0688 (1.75)
0.0532 (1.35)
8ⴗ
0.0192 (0.49) SEATING
0ⴗ 0.0500 (1.27)
0.0099 (0.25)
0.0138 (0.35) PLANE
0.0160 (0.41)
0.0075 (0.19)
16-Lead SOIC (R-16W)
(Wide Body)
0.4133 (10.50)
0.3977 (10.00)
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16
9
0.2992 (7.60)
0.2914 (7.40)
1
PIN 1
0.050 (1.27)
BSC
0.0118 (0.30)
0.0040 (0.10)
REV. D
0.4193 (10.65)
0.3937 (10.00)
8
0.1043 (2.65)
0.0926 (2.35)
8ⴗ
0.0192 (0.49) SEATING
0ⴗ
0.0125 (0.32)
0.0138 (0.35) PLANE
0.0091 (0.23)
–11–
0.0196 (0.50)
ⴛ 45ⴗ
0.0099 (0.25)
0.0291 (0.74)
ⴛ 45ⴗ
0.0098 (0.25)
0.0500 (1.27)
0.0157 (0.40)
ADG508F/ADG509F/ADG528F
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
18-Lead Plastic (N-18)
0.925 (23.49)
0.845 (21.47)
18
10
1
9
PIN 1
0.210
(5.33)
MAX
0.160 (4.06)
0.115 (2.93)
0.022 (0.558)
0.014 (0.356)
0.280 (7.11)
0.240 (6.10)
0.060 (1.52)
0.015 (0.38)
0.100
(2.54)
BSC
0.180 (4.57)
0.165 (4.19)
0.048 (1.21)
0.042 (1.07)
0.048 (1.21)
0.042 (1.07)
0.325 (8.25)
0.300 (7.62) 0.195 (4.95)
0.115 (2.93)
0.130
(3.30)
MIN
0.070 (1.77) SEATING
PLANE
0.045 (1.15)
0.056 (1.42)
0.042 (1.07)
19
18
PIN 1
IDENTIFIER
3
4
TOP VIEW
(PINS DOWN)
8
9
0.020
(0.50)
R
0.015 (0.381)
0.008 (0.204)
0.025 (0.63)
0.015 (0.38)
0.021 (0.53)
0.013 (0.33) 0.330 (8.38)
0.032 (0.81) 0.290 (7.37)
0.026 (0.66)
0.050
(1.27)
BSC
14
13
0.356 (9.04)
SQ
0.350 (8.89)
0.395 (10.02)
SQ
0.385 (9.78)
C00035c–0–4/01(D)
20-Lead PLCC (P-20A)
0.040 (1.01)
0.025 (0.64)
0.110 (2.79)
0.085 (2.16)
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Location
Page
Data Sheet changed from REV. C to REV. D.
Changes to Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Changes to Specifications table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
MAX RATINGS changed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Deleted 16-Lead Cerdip from Outline Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Deleted 18-Lead Cerdip from Outline Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
–12–
REV. D
PRINTED IN U.S.A.
ADG508F/ADG509F/ADG528F–Revision History