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Ultralow Distortion
Differential ADC Driver
ADA4938-1/ADA4938-2
16 –VS
15 –VS
13 –VS
12 PD
9 VOCM
06592-001
+VS 7
10 +OUT
+FB 4
+VS 8
11 –OUT
–IN 3
+VS 5
+IN 2
24
23
22
21
20
19
+IN1
–FB1
–VS1
–VS1
PD1
–OUT1
Figure 1. ADA4938-1 Functional Block Diagram
1
2
3
4
5
6
ADA4938-2
18
17
16
15
14
13
Figure 2. ADA4938-2 Functional Block Diagram
–50
G
G
G
G
–60
–70
The ADA4938 is a low noise, ultralow distortion, high speed
differential amplifier. It is an ideal choice for driving high
performance ADCs with resolutions up to 16 bits from dc to
27 MHz, or up to 12 bits from dc to 74 MHz. The output commonmode voltage is adjustable over a wide range, allowing the ADA4938
to match the input of the ADC. The internal common-mode
feedback loop also provides exceptional output balance as well
as suppression of even-order harmonic distortion products.
–80
SFDR (dBc)
GENERAL DESCRIPTION
The ADA4938 is fabricated using the Analog Devices, Inc.
proprietary third-generation, high voltage XFCB process, enabling
it to achieve very low levels of distortion with an input voltage
noise of only 2.6 nV/√Hz. The low dc offset and excellent dynamic
performance of the ADA4938 make it well suited for a wide
variety of data acquisition and signal processing applications.
06592-202
www.BDTIC.com/ADI
ADC drivers
Single-ended-to-differential converters
IF and baseband gain blocks
Differential buffers
Line drivers
= +2,
= +2,
= +2,
= +2,
VO, dm = 5V p-p
VO, dm = 3.2V p-p
VO, dm = 2V p-p
VO, dm = 1V p-p
–90
–100
–110
–120
–130
1
10
FREQUENCY (MHz)
100
06592-002
Full differential and single-ended-to-differential gain configurations
are easily realized with the ADA4938. A simple external feedback
network of four resistors determines the closed-loop gain of the
amplifier.
+OUT1
VOCM1
–VS2
–VS2
PD2
–OUT2
7
8
9
10
11
12
–IN1
+FB1
+VS1
+VS1
–FB2
+IN2
–IN2
+FB2
+VS2
+VS2
VOCM2
+OUT2
APPLICATIONS
ADA4938-1
–FB 1
+VS 6
Extremely low harmonic distortion
−106 dBc HD2 @ 10 MHz
−82 dBc HD2 @ 50 MHz
−109 dBc HD3 @ 10 MHz
−82 dBc HD3 @ 50 MHz
Low input voltage noise: 2.6 nV/√Hz
High speed
−3 dB bandwidth of 1000 MHz, G = +1
Slew rate: 4700 V/μs
0.1 dB gain flatness to 150 MHz
Fast overdrive recovery of 4 ns
1 mV typical offset voltage
Externally adjustable gain
Differential-to-differential or single-ended-to-differential
operation
Adjustable output common-mode voltage
Wide supply voltage range: +5 V to ±5 V
Single or dual amplifier configuration available
14 –VS
FUNCTIONAL BLOCK DIAGRAMS
FEATURES
Figure 3. SFDR vs. Frequency and Output Voltage
The ADA4938-1 (single amplifier) is available in a Pb-free,
3 mm × 3 mm, 16-lead LFCSP. The ADA4938-2 (dual
amplifier) is available in a Pb-free, 4 mm × 4 mm, 24-lead
LFCSP. The pinouts have been optimized to facilitate layout and
minimize distortion. The parts are specified to operate over the
extended industrial temperature range of −40°C to +85°C.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2007 Analog Devices, Inc. All rights reserved.
ADA4938-1/ADA4938-2
TABLE OF CONTENTS
Features .............................................................................................. 1
Theory of Operation ...................................................................... 19
Applications....................................................................................... 1
Analyzing an Application Circuit ............................................ 19
General Description ......................................................................... 1
Setting the Closed-Loop Gain .................................................. 19
Functional Block Diagrams............................................................. 1
Estimating the Output Noise Voltage ...................................... 19
Revision History ............................................................................... 2
The Impact of Mismatches in the Feedback Networks ......... 20
Specifications..................................................................................... 3
Calculating the Input Impedance of an
Application Circuit..................................................................... 20
Dual-Supply Operation ............................................................... 3
Single-Supply Operation ............................................................. 5
Absolute Maximum Ratings............................................................ 7
Thermal Resistance ...................................................................... 7
ESD Caution.................................................................................. 7
Pin Configurations and Function Descriptions ........................... 8
Typical Performance Characteristics ............................................. 9
Test Circuts ...................................................................................... 17
Operational Description................................................................ 18
Input Common-Mode Voltage Range in Single-Supply
Applications ................................................................................ 20
Terminating a Single-Ended Input .......................................... 21
Setting the Output Common-Mode Voltage .......................... 21
Layout, Grounding, and Bypassing.............................................. 23
High Performance ADC Driving ................................................. 24
Outline Dimensions ....................................................................... 25
Ordering Guide .......................................................................... 25
Definition of Terms.................................................................... 18
REVISION HISTORY
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11/07—Revision 0: Initial Version
Rev. 0 | Page 2 of 28
ADA4938-1/ADA4938-2
SPECIFICATIONS
DUAL-SUPPLY OPERATION
TA = 25°C, +VS = 5 V, −VS = −5 V, VOCM = 0 V, RT = 61.9 Ω, RG = RF = 200 Ω, G = +1, RL, dm = 1 kΩ, unless otherwise noted.
All specifications refer to single-ended input and differential output, unless otherwise noted. For gains other than G = 1, values for RF and
RG are shown in Table 11.
Table 1. ±DIN to ±OUT Performance
Parameter
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth
Bandwidth for 0.1 dB Flatness
Large Signal Bandwidth
Slew Rate
Overdrive Recovery Time
NOISE/HARMONIC PERFORMANCE
Second Harmonic
Third Harmonic
IMD
IP3
Input Voltage Noise
Noise Figure
Input Current Noise
Crosstalk (ADA4938-2)
INPUT CHARACTERISTICS
Offset Voltage
Conditions
Min
MHz
MHz
MHz
V/μs
ns
VOUT = 2 V p-p, 10 MHz
VOUT = 2 V p-p, 50 MHz
VOUT = 2 V p-p, 10 MHz
VOUT = 2 V p-p, 50 MHz
f1 = 30.0 MHz, f2 = 30.1 MHz
f = 30 MHz, RL, dm = 100 Ω
f = 10 MHz
G = +4, f = 10 MHz
f = 10 MHz
f = 100 MHz
−106
−82
−109
−82
89
45
2.6
15.8
4.8
−85
dBc
dBc
dBc
dBc
dBc
dBm
nV/√Hz
dB
pA/√Hz
dB
VOS, dm = VOUT, dm/2; VDIN+ = VDIN− = 0 V
TMIN to TMAX variation
1
±4
−13
−0.01
6
3
1
−VS + 0.3 to
+VS − 1.6
−75
−18
TMIN to TMAX variation
Differential
Common mode
Input Capacitance
Input Common-Mode Voltage
CMRR
OUTPUT CHARACTERISTICS
Output Voltage Swing
Unit
1000
150
800
4700
4
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Input Resistance
Max
VOUT = 0.1 V p-p
VOUT = 2 V p-p
VOUT = 2 V p-p
VOUT = 2 V p-p
VIN = 5 V to 0 V step, G = +2
Input Bias Current
Linear Output Current
Output Balance Error
Typ
∆VOUT, dm/∆VIN, cm; ∆VIN, cm = ±1 V, f = 1 MHz
Maximum ∆VOUT; single-ended output
Per amplifier
∆VOUT, cm/∆VOUT, dm; ∆VOUT, dm = 1 V; f = 10 MHz
Rev. 0 | Page 3 of 28
−VS + 1.2 to
+VS − 1.2
95
−60
4
mV
μV/°C
μA
μA/°C
MΩ
MΩ
pF
V
dB
V
mA
dB
ADA4938-1/ADA4938-2
Table 2. VOCM to ±OUT Performance
Parameter
VOCM DYNAMIC PERFORMANCE
−3 dB Bandwidth
Slew Rate
Input Voltage Noise (RTI)
VOCM INPUT CHARACTERISTICS
Input Voltage Range
Conditions
Input Resistance
Input Offset Voltage
Input Bias Current
VOCM CMRR
Gain
POWER SUPPLY
Operating Range
Quiescent Current
Typ
Max
Unit
VIN = −3.4 V to +3.4 V, 25% to 75%
230
1700
7.5
MHz
V/μs
nV/√Hz
V
VOS, cm = VOUT, cm; VDIN+ = VDIN− = 0 V
−VS + 1.3 to
+VS − 1.3
10
3
0.5
−81
1.00
∆VOUT, dm/∆VOCM; ∆VOCM = ±1 V
∆VOUT, cm/∆VOCM; ∆VOCM = ±1 V
0.95
4.5
Power Supply Rejection Ratio
POWER DOWN (PD)
PD Input Voltage
Turn-Off Time
Turn-On Time
PD Bias Current
Enabled
Disabled
Min
1.05
11
40
kΩ
mV
μA
dB
V/V
V
mA
μA/°C
mA
dB
Per amplifier
TMIN to TMAX variation
Powered down
∆VOUT, dm/∆VS; ∆VS = ±1 V
37
40
2.0
−80
Powered down
Enabled
≤2.5
≥3
1
200
V
V
μs
ns
1
−760
μA
μA
3.0
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PD = 5 V
PD = −5 V
OPERATING TEMPERATURE RANGE
−40
Rev. 0 | Page 4 of 28
+85
°C
ADA4938-1/ADA4938-2
SINGLE-SUPPLY OPERATION
TA = 25°C, +VS = 5 V, −VS = 0 V, VOCM = +VS/2, RT = 61.9 Ω, RG = RF = 200 Ω, G = +1, RL, dm = 1 kΩ, unless otherwise noted.
All specifications refer to single-ended input and differential output, unless otherwise noted. For gains other than G = 1, values for RF and
RG are shown in Table 11.
Table 3. ±DIN to ±OUT Performance
Parameter
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth
Bandwidth for 0.1 dB Flatness
Large Signal Bandwidth
Slew Rate
Overdrive Recovery Time
NOISE/HARMONIC PERFORMANCE
Second Harmonic
Third Harmonic
Input Voltage Noise
Noise Figure
Input Current Noise
Crosstalk (ADA4938-2)
INPUT CHARACTERISTICS
Offset Voltage
Input Bias Current
Input Resistance
Conditions
Min
Unit
1000
150
750
3900
4
MHz
MHz
MHz
V/μs
ns
VOUT = 2 V p-p, 10 MHz
VOUT = 2 V p-p, 50 MHz
VOUT = 2 V p-p, 10 MHz
VOUT = 2 V p-p, 50 MHz
f = 10 MHz
G = +4, f = 10 MHz
f = 10 MHz
f = 100 MHz
−110
−79
−100
−79
2.6
15.8
4.8
−85
dBc
dBc
dBc
dBc
nV/√Hz
dB
pA/√Hz
dB
VOS, dm = VOUT, dm/2; VDIN+ = VDIN− = VOCM = 2.5 V
TMIN to TMAX variation
1
±4
−13
−0.01
6
3
1
−VS + 0.3 to
+VS − 1.6
−80
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CMRR
OUTPUT CHARACTERISTICS
Output Voltage Swing
Max
VOUT = 0.1 V p-p
VOUT = 2 V p-p
VOUT = 2 V p-p
VOUT = 2 V p-p
VIN = 2.5 V to 0 V step, G = +2
−18
TMIN to TMAX variation
Differential
Common mode
Input Capacitance
Input Common-Mode Voltage
Linear Output Current
Output Balance Error
Typ
∆VOUT, dm/∆VIN, cm; ∆VIN, cm = ±1 V
Maximum ∆VOUT; single-ended output
Per amplifier
∆VOUT, cm/∆VOUT, dm; ∆VOUT, dm = 1 V
Rev. 0 | Page 5 of 28
−VS + 1.2 to
+VS − 1.2
95
−60
4
mV
μV/°C
μA
μA/°C
MΩ
MΩ
pF
V
dB
V
mA
dB
ADA4938-1/ADA4938-2
Table 4. VOCM to ±OUT Performance
Parameter
VOCM DYNAMIC PERFORMANCE
−3 dB Bandwidth
Slew Rate
Input Voltage Noise (RTI)
VOCM INPUT CHARACTERISTICS
Input Voltage Range
Conditions
Input Resistance
Input Offset Voltage
Input Bias Current
VOCM CMRR
Gain
POWER SUPPLY
Operating Range
Quiescent Current
Typ
Max
Unit
VIN = 1.6 V to 3.4 V, 25% to 75%
400
1700
7.5
MHz
V/μs
nV/√Hz
V
VOS, cm = VOUT, cm; VDIN+ = VDIN– = VOCM = 2.5 V
−VS + 1.3 to
+VS − 1.3
10
3
0.5
−89
1.00
∆VOUT, dm/∆VOCM; ∆VOCM = ±1 V
∆VOUT, cm/∆VOCM; ∆VOCM = ±1 V
0.95
4.5
Power Supply Rejection Ratio
POWER DOWN (PD)
PD Input Voltage
Turn-Off Time
Turn-On Time
PD Bias Current
Enabled
Disabled
Min
34
40
1.0
−80
TMIN to TMAX variation
Powered down
∆VOUT, dm/∆VS; ∆VS = ±1 V
Powered down
Enabled
1.05
11
36.5
1.7
OPERATING TEMPERATURE RANGE
−40
Rev. 0 | Page 6 of 28
V
mA
μA/°C
mA
dB
≤2.5
≥3
1
200
V
V
μs
ns
1
−260
μA
μA
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PD = 5 V
PD = 0 V
kΩ
mV
μA
dB
V/V
+85
°C
ADA4938-1/ADA4938-2
ABSOLUTE MAXIMUM RATINGS
Parameter
Supply Voltage
Power Dissipation
Storage Temperature Range
Operating Temperature Range
Lead Temperature (Soldering, 10 sec)
Junction Temperature
Rating
12 V
See Figure 4
−65°C to +125°C
−40°C to +85°C
300°C
150°C
Stresses above those listed under Absolute Maximum Rating
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the device (including exposed pad) soldered
to a high thermal conductivity 4-layer circuit board, as described in
EIA/JESD 51-7. The exposed pad is not electrically connected to
the device. It is typically soldered to a pad on the PCB that is
thermally and electrically connected to an internal ground plane.
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive. The quiescent power is the voltage
between the supply pins (VS) times the quiescent current (IS).
The power dissipated due to the load drive depends upon the
particular application. The power due to load drive is calculated
by multiplying the load current by the associated voltage drop
across the device. RMS voltages and currents must be used in
these calculations.
Airflow increases heat dissipation, which effectively reducing
θJA. In addition, more metal directly in contact with the package
leads/exposed pad from metal traces, through-holes, ground,
and power planes reduces the θJA.
Figure 4 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the 16-lead LFCSP
(95°C/W) and the 24-lead LFCSP (65°C/W) on a JEDEC standard
4-layer board.
3.5
MAXIMUM POWER DISSIPATION (W)
Table 5.
3.0
2.5
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Table 6. Thermal Resistance
Package Type
16-Lead LFCSP (Exposed Pad)
24-Lead LFCSP (Exposed Pad)
θJA
95
65
Unit
°C/W
°C/W
ADA4938-2
2.0
1.5
ADA4938-1
1.0
0.5
The maximum safe power dissipation in the ADA4938 package
is limited by the associated rise in junction temperature (TJ) on
the die. At approximately 150°C, which is the glass transition
temperature, the plastic changes its properties. Even temporarily
exceeding this temperature limit can change the stresses that the
package exerts on the die, permanently shifting the parametric
performance of the ADA4938. Exceeding a junction temperature of
150°C for an extended period can result in changes in the silicon
devices, potentially causing failure.
0
–40 –30 –20 –10
0
10
20
30
40
50
AMBIENT TEMPERATURE (°C)
60
70
80
90
06592-103
Maximum Power Dissipation
Figure 4. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
ESD CAUTION
Rev. 0 | Page 7 of 28
ADA4938-1/ADA4938-2
24
23
22
21
20
19
13 –VS
12 PD
TOP VIEW
(Not to Scale)
10 +OUT
+VS 5
ADA4938-2
TOP VIEW
(Not to Scale)
18
17
16
15
14
13
+OUT1
VOCM1
–VS2
–VS2
PD2
–OUT2
7
8
9
10
11
12
9 VOCM
PIN 1
INDICATOR
Figure 5. ADA4938-1 Pin Configuration
06592-206
–IN 3
+FB 4
+VS 8
11 –OUT
+VS 7
ADA4938-1
+VS 6
+IN 2
1
2
3
4
5
6
–IN2
+FB2
+VS2
+VS2
VOCM2
+OUT2
PIN 1
INDICATOR
–IN1
+FB1
+VS1
+VS1
–FB2
+IN2
06592-003
–FB 1
15 –VS
14 –VS
16 –VS
+IN1
–FB1
–VS1
–VS1
PD1
–OUT1
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 6. ADA4938-2 Pin Configuration
Table 7. ADA4938-1 Pin Function Descriptions
Table 8. ADA4938-2 Pin Function Descriptions
Pin No.
1
2
3
4
5 to 8
9
10
11
12
13 to 16
Pin No.
1
2
3, 4
5
6
7
8
9, 10
11
12
13
14
15, 16
17
18
19
20
21, 22
23
24
Mnemonic
−FB
+IN
−IN
+FB
+VS
VOCM
+OUT
−OUT
PD
−VS
Description
Negative Output Feedback Pin.
Positive Input Summing Node.
Negative Input Summing Node.
Positive Output Feedback Pin.
Positive Supply Voltage.
Output Common-Mode Voltage.
Positive Output for Load Connection.
Negative Output for Load Connection.
Power-Down Pin.
Negative Supply Voltage.
Mnemonic
−IN1
+FB1
+VS1
−FB2
+IN2
−IN2
+FB2
+VS2
VOCM2
+OUT2
−OUT2
PD2
−VS2
VOCM1
+OUT1
−OUT1
PD1
−VS1
−FB1
+IN1
Description
Negative Input Summing Node 1.
Positive Output Feedback Pin 1.
Positive Supply Voltage 1.
Negative Output Feedback Pin 2.
Positive Input Summing Node 2.
Negative Input Summing Node 2.
Positive Output Feedback Pin 2.
Positive Supply Voltage 2.
Output Common-Mode Voltage 2.
Positive Output 2.
Negative Output 2.
Power-Down Pin 2.
Negative Supply Voltage 2.
Output Common-Mode Voltage 1.
Positive Output 1.
Negative Output 1.
Power-Down Pin 1.
Negative Supply Voltage 1.
Negative Output Feedback Pin 1.
Positive Input Summing Node 1.
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Rev. 0 | Page 8 of 28
ADA4938-1/ADA4938-2
TYPICAL PERFORMANCE CHARACTERISTICS
3
0
0
–3
–6
–9
G
G
G
G
–12
10
100
1000
FREQUENCY (MHz)
= +1
= +2
= +3.16
= +5
1
10
100
1000
FREQUENCY (MHz)
Figure 10. Large Signal Frequency Response for Various Gains
3
3
0
0
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GAIN (dB)
–3
–6
–3
–6
–9
VS = +5V
VS = ±5V
10
100
1000
FREQUENCY (MHz)
–12
1
0
0
NORMALIZED GAIN (dB)
3
–3
–6
–3
–6
–9
–40°C
+25°C
+85°C
10
100
FREQUENCY (MHz)
Figure 9. Small Signal Frequency Response for
Various Temperatures, VOUT = 0.1 V p-p
1000
–40°C
+25°C
+85°C
–12
06592-107
1
1000
Figure 11. Large Signal Response for Various Supplies
3
–12
100
FREQUENCY (MHz)
Figure 8. Small Signal Response for Various Supplies, VOUT = 0.1 V p-p
–9
10
1
10
100
FREQUENCY (MHz)
1000
06592-110
1
06592-106
–12
VS = +5V
VS = ±5V
06592-109
–9
NORMALIZED GAIN (dB)
G
G
G
G
–12
Figure 7. Small Signal Frequency Response for Various Gains, VOUT = 0.1 V p-p
GAIN (dB)
–6
–9
= +1
= +2
= +3.16
= +5
1
–3
06592-108
NORMALIZED GAIN (dB)
3
06592-105
NORMALIZED GAIN (dB)
TA = 25°C, +VS = 5 V, −VS = −5 V, VOCM = 0 V, RT = 61.9 Ω, RG = RF = 200 Ω, G = +1, RL, dm = 1 kΩ, unless otherwise noted.
All measurements were performed with single-ended input and differential output, unless otherwise noted. For gains other than G = +1,
values for RF and RG are shown in Table 11.
Figure 12. Large Signal Frequency Response for Various Temperatures
Rev. 0 | Page 9 of 28
3
0
0
–3
–3
–6
–9
–12
–15
RL = 1kΩ
RL = 100Ω
RL = 200Ω
1
10
100
1000
1
0
NORMALIZED GAIN (dB)
0
–3
–6
1
–3
–6
–9
10
100
1000
FREQUENCY (MHz)
Figure 14. Small Signal Frequency Response for
Various Gains, VS = 5 V, VOUT = 0.1 V p-p
NORMALIZED GAIN (dB)
0
–3
–6
= +1
= +2
= +3.16
= +5
FREQUENCY (MHz)
1000
–3
–6
G
G
G
G
–12
06592-113
100
1000
0
–9
10
100
Figure 17. Large Signal Frequency Response for Various Gains, VS = 5 V
3
1
10
FREQUENCY (MHz)
3
–12
= +1
= +2
= +3.16
= +5
1
6
G
G
G
G
G
G
G
G
–12
6
–9
1000
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= +1
= +2
= +3.16
= +5
06592-112
–12
100
Figure 16. Large Signal Frequency Response for Various Loads
3
G
G
G
G
10
FREQUENCY (MHz)
3
–9
RL = 1kΩ
RL = 100Ω
RL = 200Ω
–21
Figure 13. Small Signal Frequency Response for
Various Loads, VOUT = 0.1 V p-p
NORMALIZED GAIN (dB)
–15
–18
FREQUENCY (MHz)
NORMALIZED GAIN (dB)
–12
06592-115
–21
–9
1
= +1
= +2
= +3.16
= +5
10
100
1000
FREQUENCY (MHz)
Figure 15. Small Signal Response for Various Gains, RF = 402 Ω, VOUT = 0.1 V p-p
Rev. 0 | Page 10 of 28
Figure 18. Large Signal Response for Various Gains, RF = 402 Ω
06592-116
–18
–6
06592-114
NORMALIZED GAIN (dB)
3
06592-111
NORMALIZED GAIN (dB)
ADA4938-1/ADA4938-2
6
3
3
0
–3
–6
G
G
G
G
–9
–12
= +1
= +2
= +3.16
= +5
1
–3
–6
G
G
G
G
–9
10
100
1000
FREQUENCY (MHz)
–12
10
100
1000
FREQUENCY (MHz)
Figure 22. Large Signal Frequency Response for Various Gains, RF = 402 Ω,
VS = 5 V
3
0
0
–3
–3
GAIN (dB)
3
–6
–6
www.BDTIC.com/ADI
–9
10
100
1000
FREQUENCY (MHz)
1
GAIN (dB)
100
1000
FREQUENCY (MHz)
06592-119
10
1000
Figure 23. VOUT, cm Large Signal Frequency Response
RL, dm = 1kΩ
RL, dm = 100Ω
RL, dm = 200Ω
1
100
FREQUENCY (MHz)
Figure 20. VOUT, cm Small Signal Frequency Response, VOUT = 0.1 V p-p
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.7
–0.8
–0.9
–1.0
10
06592-121
1
VS = +5V
VS = ±5V
–12
Figure 21. 0.1 dB Flatness Response for Various Loads, ADA4938-1,
VOUT = 0.1 V p-p
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
RL, dm = 1kΩ
RL, dm = 100Ω
RL, dm = 200Ω
1
10
100
1000
FREQUENCY (MHz)
Figure 24. 0.1 dB Flatness Response for Various Loads, ADA4938-2,
VOUT = 0.1 V p-p
Rev. 0 | Page 11 of 28
06592-122
VS = +5V
VS = ±5V
–12
06592-118
–9
NORMALIZED GAIN (dB)
= +1
= +2
= +3.16
= +5
1
Figure 19. Small Signal Frequency Response for Various Gains, RF = 402 Ω,
VS = 5 V, VOUT = 0.1 V p-p
GAIN (dB)
0
06592-120
NORMALIZED GAIN (dB)
6
06592-117
NORMALIZED GAIN (dB)
ADA4938-1/ADA4938-2
ADA4938-1/ADA4938-2
HD2,
HD3,
HD2,
HD3,
–50
–80
–90
–90
–110
–110
–120
06592-123
10
100
FREQUENCY (MHz)
0
–50
–60
–70
G
G
G
G
G
G
–40
= +1
= +1
= +2
= +2
= +5
= +5
–60
–90
5
6
7
8
9
RL
RL
RL
RL
RL
RL
= 1kΩ
= 1kΩ
= 200Ω
= 200Ω
= 100Ω
= 100Ω
–70
–80
–90
–110
10
100
–120
FREQUENCY (MHz)
1
100
FREQUENCY (MHz)
Figure 26. Harmonic Distortion vs. Frequency and Gain
HD2,
HD3,
HD2,
HD3,
10
06592-127
1
06592-124
–130
Figure 29. Harmonic Distortion vs. Frequency for Various Loads
–40
10MHz
10MHz
70MHz
70MHz
HD2,
HD3,
HD2,
HD3,
–50
10MHz
10MHz
70MHz
70MHz
–60
DISTORTION (dBc)
–70
–80
–90
–100
–70
–80
–90
–100
–110
–110
–130
–3.3 –2.7 –2.1 –1.5 –0.9 –0.3
0.3
0.9
1.5
2.1
2.7
VOCM (V)
3.3
06592-128
–120
Figure 27. Harmonic Distortion vs. VOCM and Frequency
–120
1.7
1.9
2.1
2.3
2.5
2.7
2.9
3.1
3.3
VOCM (V)
Figure 30. Harmonic Distortion vs. VOCM and Frequency, VS = 5 V
Rev. 0 | Page 12 of 28
06592-125
–60
4
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–120
–50
3
–100
–110
–40
HD2,
HD3,
HD2,
HD3,
HD2,
HD3,
–50
–80
–100
2
Figure 28. Harmonic Distortion vs. VOUT and Supply Voltage
DISTORTION (dBc)
HD2,
HD3,
HD2,
HD3,
HD2,
HD3,
1
VOUT, dm (V)
Figure 25. Harmonic Distortion vs. Frequency and Supply Voltage
DISTORTION (dBc)
–80
–100
–120
DISTORTION (dBc)
–70
–100
–40
+5V
+5V
±5V
±5V
–60
–70
1
HD2,
HD3,
HD2,
HD3,
–50
DISTORTION (dBc)
DISTORTION (dBc)
–60
–40
VS = +5V
VS = +5V
VS = ±5V
VS = ±5V
06592-126
–40
ADA4938-1/ADA4938-2
0
–10
–30
–40
PSRR (dB)
–50
–60
–70
–80
–90
–110
29.5
29.6
29.7
29.8
29.9
30.0
30.1
30.2
30.3
30.4
30.5
FREQUENCY (MHz)
06592-129
–100
1
10
100
1000
Figure 34. PSRR vs. Frequency
–20
0
–25
–5
–30
–10
–35
–15
RETURN LOSS (dB)
–40
–45
–50
–55
VS = ±5V
–60
–65
–20
–25
S22
–30
–35
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–40
VS = +5V
–70
S11
–45
–75
–85
0.1
1
10
100
1000
FREQUENCY (MHz)
–55
1
100
1000
FREQUENCY (MHz)
Figure 32. VIN CMRR vs. Frequency
Figure 35. Return Loss (S11, S22) vs. Frequency
–15
–40
RL = 1kΩ
RL = 200Ω
RL = 100Ω
RL = 200Ω
–20
10
06592-134
–50
–80
06592-130
VIN CMRR (dB)
+PSRR
FREQUENCY (MHz)
Figure 31. Intermodulation Distortion
–50
–25
–60
–30
SFDR (dBc)
–35
–40
–45
–70
–80
–90
–50
–100
–55
–110
–60
–65
1
10
100
FREQUENCY (MHz)
1000
06592-131
OUTPUT BALANCE (dB)
–PSRR
Figure 33. Output Balance vs. Frequency
–120
1
10
100
FREQUENCY (MHz)
Figure 36. SFDR vs. Frequency for Various Loads
Rev. 0 | Page 13 of 28
06592-135
DISTORTION (dBc)
–20
0
–5
–10
–15
–20
–25
–30
–35
–40
–45
–50
–55
–60
–65
–70
–75
–80
–85
0.1
06592-132
10
ADA4938-1/ADA4938-2
26
100
24
INPUT VOLTAGE NOISE (nV/ Hz)
G = +1
NOISE FIGURE (dB)
22
20
G = +2
18
G = +4
16
14
10
100
500
FREQUENCY (MHz)
1
10
06592-136
10
10
10k
100k
1M
10M
100M
Figure 40. Input Voltage Noise vs. Frequency
10
4.0
8
3.5
6
3.0
4
PD INPUT
VOLTAGE (V)
2.5
2
0
–2
2.0
1.5
1.0
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–4
0.5
–6
5
10
15
20
25
30
35
40
45
50
55
60
TIME (5ns/DIV)
06592-140
0
–0.5
06592-137
–10
SINGLE OUTPUT
0
VIN × 3.16
VOUT, dm
–8
TIME (200ns/DIV)
Figure 41. Power-Down Response Time
Figure 38. Overdrive Recovery Time (Pulse Input)
45
12
10
40
8
+85°C
+25°C
–40°C
35
6
CURRENT (mA)
4
VOLTAGE (V)
1k
FREQUENCY (Hz)
Figure 37. Noise Figure vs. Frequency
VOLTAGE (V)
100
06592-039
12
2
0
–2
–4
–6
30
25
20
15
10
–8
0
50
100
150
200
250
300
TIME (50ns/DIV)
350
400
450
500
0
2.0
06592-138
–12
Figure 39. Overdrive Amplitude Characteristics (Triangle Wave Input)
2.2
2.4
2.6
2.8
3.0
3.2
VOLTAGE (V)
3.4
3.6
3.8
4.0
06592-141
5
VIN × 3.16
VOUT, dm
–10
Figure 42. Supply Current vs. Power-Down Voltage and Temperature
Rev. 0 | Page 14 of 28
ADA4938-1/ADA4938-2
0.20
3.0
2.5
0.15
2.0
1.5
1.0
0.05
VOLTAGE (V)
0
–0.05
0.5
0
–0.5
–1.0
–1.5
–0.10
–2.0
–0.15
TIME (1ns/DIV)
–3.0
TIME (1ns/DIV)
Figure 46. Large Signal Transient Response
0.10
2.5
0.08
2.0
0.06
1.5
0.04
1.0
VOLTAGE (V)
0.02
0
–0.02
–0.04
0.5
0
–0.5
–1.0
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–0.06
–1.5
–0.08
–0.10
06592-043
–2.0
TIME (2ns/DIV)
–2.5
Figure 44. VOCM Small Signal Transient Response, VOUT = 0.1 V p-p
3
+85°C
+25°C
–40°C
ALL CURVES ARE
NORMALIZED TO VOCM = 0V
0
40
30
20
–3
VOCM = –3.7V
VOCM = –3.5V
VOCM = –3V
VOCM = 0V
VOCM = +3V
VOCM = +3.5V
VOCM = +3.7V
–6
–9
10
2.2
2.4
2.6
2.8
3.0
3.2
VOLTAGE (V)
3.4
3.6
3.8
4.0
–12
06592-144
0
2.0
TIME (2ns/DIV)
Figure 47. VOCM Large Signal Transient Response
CLOSED-LOOP GAIN (dB)
CURRENT (mA)
50
06592-046
VOLTAGE (V)
Figure 43. Small Signal Transient Response, VOUT = 0.1 V p-p
60
06592-145
06592-142
–2.5
–0.20
Figure 45. Supply Current vs. Power-Down Voltage and Temperature, VS = 5 V
1
10
100
FREQUENCY (MHz)
1000
06592-048
VOLTAGE (V)
0.10
Figure 48. VOUT, dm Small Signal Frequency Response for Various VOCM,
VOUT = 0.1 V p-p
Rev. 0 | Page 15 of 28
ADA4938-1/ADA4938-2
100
IP3 100Ω
45
40
06592-049
35
30
10
10
1
10
100
100
Figure 49. IP3 vs. Frequency
3
10k
100k
1M
10M
100M
Figure 51. Input Current Noise vs. Frequency
–40
ALL CURVES ARE
NORMALIZED TO VOCM = 0V
–50
–60
0
CROSSTALK (dB)
INPUT1, OUTPUT2
–3
–6
VOCM = –3.7V
VOCM = –3.5V
VOCM = –3V
VOCM = 0V
VOCM = +3V
VOCM = +3.5V
VOCM = +3.7V
–9
–12
1
10
–70
–80
–90
–100
INPUT2, OUTPUT1
–110
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–120
–130
100
FREQUENCY (MHz)
1000
–140
0.3
06592-50
CLOSED-LOOP GAIN (dB)
1k
FREQUENCY (Hz)
FREQUENCY (MHz)
1
10
100
FREQUENCY (MHz)
Figure 52. Crosstalk vs. Frequency for ADA4938-2
Figure 50. VOUT, dm Large Signal Frequency Response for Various VOCM
Rev. 0 | Page 16 of 28
1000
06592-888
IP3 (dBm)
50
06592-051
INPUT CURRENT NOISE (pA/ Hz)
55
ADA4938-1/ADA4938-2
TEST CIRCUTS
200Ω
+5V
50Ω
200Ω
VIN
VOCM
61.9Ω
ADA4938
1kΩ
200Ω
06592-246
27.5Ω
–5V
200Ω
Figure 53. Equivalent Basic Test Circuit
200Ω
+5V
50Ω
200Ω
VIN
50Ω
VOCM
61.9Ω
ADA4938
200Ω
50Ω
06592-247
27.5Ω
–5V
200Ω
Figure 54. Test Circuit for Output Balance
www.BDTIC.com/ADI
200Ω
+5V
VIN
FILTER
61.9Ω
0.1µF 412Ω
200Ω
VOCM
FILTER
ADA4938
0.1µF 412Ω
200Ω
27.5Ω
–5V
200Ω
Figure 55. Test Circuit for Distortion Measurements
Rev. 0 | Page 17 of 28
06592-248
50Ω
ADA4938-1/ADA4938-2
OPERATIONAL DESCRIPTION
Common-Mode Voltage
DEFINITION OF TERMS
–FB
RG
RF
The common-mode voltage is the average of two node voltages.
The output common-mode voltage is defined as
ADA4938
+IN
–OUT
VOCM
VOUT, cm = (V+OUT + V−OUT)/2
RL, dm VOUT, dm
RF
–IN
+OUT
+FB
Balance
06592-004
RG
Figure 56. Circuit Definitions
Differential Voltage
The differential voltage is the difference between two node
voltages. For example, the output differential voltage (or
equivalently, output differential-mode voltage) is defined as
VOUT, dm = (V+OUT − V−OUT)
where V+OUT and V−OUT refer to the voltages at the +OUT and
−OUT terminals with respect to a common reference.
Balance is a measure of how well differential signals are matched in
amplitude and are exactly 180° apart in phase. Balance is most
easily determined by placing a well-matched resistor divider
between the differential voltage nodes and comparing the
magnitude of the signal at the midpoint of the divider with
the magnitude of the differential signal. By this definition,
output balance is the magnitude of the output common-mode
voltage divided by the magnitude of the output differential
mode voltage.
Output Balance Error =
VOUT , cm
VOUT , dm
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Rev. 0 | Page 18 of 28
ADA4938-1/ADA4938-2
THEORY OF OPERATION
The ADA4938 differs from conventional op amps in that it has
two outputs whose voltages move in opposite directions. Like
an op amp, it relies on open-loop gain and negative feedback
to force these outputs to the desired voltages. The ADA4938
behaves much like a standard voltage feedback op amp and
makes it easier to perform single-ended-to-differential conversions,
common-mode level shifting, and amplifications of differential
signals. Also like an op amp, the ADA4938 has high input
impedance and low output impedance.
Two feedback loops are employed to control the differential and
common-mode output voltages. The differential feedback, set
with external resistors, controls only the differential output
voltage. The common-mode feedback controls only the commonmode output voltage. This architecture makes it easy to set the
output common-mode level to any arbitrary value. It is forced,
by internal common-mode feedback, to be equal to the voltage
applied to the VOCM input, without affecting the differential
output voltage.
The ADA4938 architecture results in outputs that are highly
balanced over a wide frequency range without requiring tightly
matched external components. The common-mode feedback
loop forces the signal component of the output commonmode voltage to zero, which results in nearly perfectly balanced
differential outputs that are identical in amplitude and are
exactly 180° apart in phase.
SETTING THE CLOSED-LOOP GAIN
The differential-mode gain of the circuit in Figure 56 can be
determined by
VOUT , dm
VIN , dm
=
RF
RG
This assumes the input resistors (RG) and feedback resistors (RF)
on each side are equal.
ESTIMATING THE OUTPUT NOISE VOLTAGE
The differential output noise of the ADA4938 can be estimated
using the noise model in Figure 57. The input-referred noise
voltage density, vnIN, is modeled as a differential input, and the
noise currents, inIN− and inIN+, appear between each input and
ground. The noise currents are assumed to be equal and produce a
voltage across the parallel combination of the gain and feedback
resistances. vnCM is the noise voltage density at the VOCM pin.
Each of the four resistors contributes (4kTR)1/2. Table 9 summarizes
the input noise sources, the multiplication factors, and the outputreferred noise density terms.
VnRG1
RG1
VnRF1
RF1
inIN+
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+
inIN–
VnIN
ADA4938
VnOD
ANALYZING AN APPLICATION CIRCUIT
VOCM
VnRG2
RG2
RF2
VnCM
VnRF2
06592-005
The ADA4938 uses open-loop gain and negative feedback to
force its differential and common-mode output voltages in such
a way as to minimize the differential and common-mode error
voltages. The differential error voltage is defined as the voltage
between the differential inputs labeled +IN and −IN (see
Figure 56). For most purposes, this voltage can be assumed
to be zero. Similarly, the difference between the actual output
common-mode voltage and the voltage applied to VOCM can also
be assumed to be zero. Starting from these two assumptions,
any application circuit can be analyzed.
Figure 57. ADA4938 Noise Model
Table 9. Output Noise Voltage Density Calculations
Input Noise Contribution
Differential Input
Inverting Input
Noninverting Input
VOCM Input
Gain Resistor, RG1
Gain Resistor, RG2
Feedback Resistor, RF1
Feedback Resistor, RF2
Input Noise Term
vnIN
inIN−
inIN+
vnCM
vnRG1
vnRG2
vnRF1
vnRF2
Input Noise
Voltage Density
vnIN
inIN− × (RG2||RF2)
inIN+ × (RG1||RF1)
vnCM
(4kTRG1)1/2
(4kTRG2)1/2
(4kTRF1)1/2
(4kTRF2)1/2
Rev. 0 | Page 19 of 28
Output
Multiplication Factor
GN
GN
GN
GN(β1 − β2)
GN(1 − β2)
GN(1 − β1)
1
1
Output Noise
Voltage Density Term
vnO1 = GN(vnIN)
vnO2 = GN[inIN− × (RG2||RF2)]
vnO3 = GN[inIN+ × (RG1||RF1)]
vnO4 = GN(β1 − β2)(vnCM)
vnO5 = GN(1 − β2)(4kTRG1)1/2
vnO6 = GN(1 − β1)(4kTRG2)1/2
vnO7 = (4kTRF1)1/2
vnO8 = (4kTRF2)1/2
ADA4938-1/ADA4938-2
Similar to the case of a conventional op amp, the output noise
voltage densities can be estimated by multiplying the inputreferred terms at +IN and −IN by the appropriate output factor,
where:
2
is the circuit noise gain.
GN =
(β1 + β2 )
RG1
RG2
β1 =
and β2 =
are the feedback factors.
RF1 + RG1
RF2 + RG2
CALCULATING THE INPUT IMPEDANCE OF AN
APPLICATION CIRCUIT
The effective input impedance of a circuit depends on whether
the amplifier is being driven by a single-ended or differential
signal source. For balanced differential input signals, as shown
in Figure 58, the input impedance (RIN, dm) between the inputs
(+DIN and −DIN) is simply RIN, dm = 2 × RG.
RF
ADA4938
When RF1/RG1 = RF2/RG2, β1 = β2 = β, and the noise gain
becomes
+DIN
1
R
=1+ F
β
RG
–DIN
Note that the output noise from VOCM goes to zero in this case.
The total differential output noise density, vnOD, is the root-sumsquare of the individual output noise terms.
v nOD =
+IN
VOCM
RG
VOUT, dm
–IN
06592-006
GN =
+VS
RG
RF
Figure 58. ADA4938 Configured for Balanced (Differential) Inputs
For an unbalanced, single-ended input signal (see Figure 59),
the input impedance is
8
2
∑ vnOi
i =1
THE IMPACT OF MISMATCHES IN THE FEEDBACK
NETWORKS
RIN , cm
As previously mentioned, even if the external feedback networks
(RF/RG) are mismatched, the internal common-mode feedback
loop still forces the outputs to remain balanced. The amplitudes
of the signals at each output remain equal and 180° out of phase.
The input-to-output, differential mode gain varies proportionately
to the feedback mismatch, but the output balance is unaffected.
⎛
⎞
⎜
⎟
R
G
⎟
=⎜
RF
⎜1−
⎟
⎜
⎟
(
)
2
R
R
×
+
F ⎠
G
⎝
RF
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In addition, if the dc levels of the input and output commonmode voltages are different, matching errors result in a small
differential-mode output offset voltage. When G = +1, with a
ground referenced input signal and the output common-mode
level set to 2.5 V, an output offset of as much as 25 mV (1% of
the difference in common-mode levels) can result if 1% tolerance
resistors are used. Resistors of 1% tolerance result in a worst-case
input CMRR of about 40 dB, a worst-case differential-mode
output offset of 25 mV due to 2.5 V level-shift, and no significant
degradation in output balance error.
VOCM
RT
ADA4938
VOUT, dm
RG
RS
RT
RF
06592-007
As well as causing a noise contribution from VOCM, ratio matching
errors in the external resistors result in a degradation of the
ability of the circuit to reject input common-mode signals, much
the same as for a four-resistor difference amplifier made from a
conventional op amp.
+VS
RG
RS
Figure 59. ADA4938 Configured for Unbalanced (Single-Ended) Input
The input impedance of the circuit is effectively higher than it
would be for a conventional op amp connected as an inverter
because a fraction of the differential output voltage appears at
the inputs as a common-mode signal, partially bootstrapping
the voltage across the input resistor RG.
INPUT COMMON-MODE VOLTAGE RANGE IN
SINGLE-SUPPLY APPLICATIONS
The ADA4938 is optimized for level-shifting, ground-referenced
input signals. As such, the center of the input common-mode
range is shifted approximately 1 V down from midsupply. The
input common-mode range at the summing nodes of the amplifier
is from 0.3 V above −VS to 1.6 V below +VS. To avoid clipping at
the outputs, the voltage swing at the +IN and −IN terminals must
be confined to these ranges.
Rev. 0 | Page 20 of 28
ADA4938-1/ADA4938-2
RF
TERMINATING A SINGLE-ENDED INPUT
200Ω
+VS
Using an example with an input source of 2 V, a source
resistance of 50 Ω, and an overall gain of 1 V/V, four simple
steps must be followed to terminate a single-ended input to the
ADA4938.
VTH
1.1V
RTH
RG
27.4Ω
200Ω
VOCM
1. The input impedance is calculated using the formula
RTS
27.4Ω
⎛
⎞ ⎛
⎞
⎜
⎟ ⎜
⎟
R
200
G
⎜
⎟
⎟ = 267 Ω
=
=⎜
200
RF
⎜
⎟ ⎜
⎟
1
−
−
1
⎜
2 × (200 + 200) ⎟⎠
2 × (RG + RF ) ⎟⎠ ⎜⎝
⎝
RF
RIN
267Ω
VS
2V
+VS
50Ω
200Ω
VOCM
200Ω
Figure 63. Balancing Gain Resistor RG
ADA4938
RL
VO
200Ω
200Ω
To get the overall gain back to 1 V/V (VO = VS = 2 V),
RF should be
b.
06592-081
–VS
RF
To make the output voltage VO = 1 V, RF is calculated
using
⎛ V × (RG + RTS ) ⎞ ⎛ 1× (200 + 27.4) ⎞
⎟=⎜
RF = ⎜⎜ O
⎟ = 207 Ω
⎟ ⎝
1.1
VTH
⎠
⎝
⎠
RG
⎛ V × (RG + RTS ) ⎞ ⎛ 2 × (200 + 27.4) ⎞
⎟=⎜
RF = ⎜⎜ O
⎟ = 414 Ω
⎟ ⎝
VTH
1.1
⎠
⎝
⎠
Figure 60. Single-Ended Input Impedance
2. To provide a 50 Ω termination for the source, the Resistor RT
is calculated such that RT || RIN = 50 Ω, or RT = 61.9 Ω.
www.BDTIC.com/ADI
RF
200Ω
+VS
50Ω
RS
VS
2V
RS
RG
50Ω
RT
61.9Ω
VS
2V
200Ω
VOCM
06592-084
–VS
RF
a.
RG
200Ω
4. Finally, the feedback resistor is recalculated to adjust the
output voltage to the desired level.
200Ω
RS
VO
RL 0.97V
ADA493x
RL
50Ω
RF
+VS
RG
RT
61.9Ω
200Ω
VOCM
ADA493x
RL
VO
RTS
27.4Ω
RG
200Ω
200Ω
–VS
RF
06592-082
–VS
RF
200Ω
VO
RG
06592-085
R IN
ADA493x
RG
Figure 64. Complete Single-Ended-to-Differential System
Figure 61. Adding Termination Resistor RT
SETTING THE OUTPUT COMMON-MODE VOLTAGE
3. To compensate for the imbalance of the gain resistors, a
correction resistor (RTS) is added in series with the inverting
input gain resistor RG. RTS is equal to the Thevenin equivalent
of the source resistance RS || RT.
The VOCM pin of the ADA4938 is internally biased at a voltage
approximately equal to the midsupply point (average value of
the voltages on V+ and V−). Relying on this internal bias results
in an output common-mode voltage that is within about 100 mV of
the expected value.
RS
RTH
RT
61.9Ω
VTH
1.1V
In cases where more accurate control of the output commonmode level is required, it is recommended that an external
source, or resistor divider (10 kΩ or greater resistors), be used.
27.4Ω
06592-083
VS
2V
50Ω
Figure 62. Calculating Thevenin Equivalent
RTS = RTH = RS || RT = 27.4 Ω. Note that VTH is not equal to
VS/2, which would be the case if the amplifier circuit did
not affect the termination.
It is also possible to connect the VOCM input to a common-mode
level (CML) output of an ADC. However, care must be taken to
assure that the output has sufficient drive capability. The input
impedance of the VOCM pin is approximately 10 kΩ. If multiple
ADA4938 devices share one reference output, it is recommended
that a buffer be used.
Rev. 0 | Page 21 of 28
ADA4938-1/ADA4938-2
Table 10 and Table 11 list several common gain settings, associated
resistor values, input impedances, and output noise densities for
both balanced and unbalanced input configurations. Also shown
are the input common-mode voltages under the given conditions
for different VOCM settings for both a 10 V single supply and
±5 V dual supplies.
Table 10. Differential Ground-Referenced Input, DC-Coupled; See Figure 58
Nominal
Gain (V/V)
1
2
3.16
5
RF (Ω)
200
402
402
402
RG (Ω)
200
200
127
80.6
RIN, dm (Ω)
400
400
254
161
Differential
Output
Noise Density
(nV/√Hz)
6.5
10.4
13.4
18.2
Common-Mode Level at +IN, −IN (V)
+VS = 5 V, −VS = −5 V
+VS = 10 V, −VS = 0 V
VOUT, dm = 2.0 V p-p
VOUT, dm = 2.0 V p-p
VOCM = 2.5 V
VOCM = 3.5 V
VOCM = 1.0 V
VOCM = 3.2 V
1.25
1.75
0.50
1.60
0.83
1.16
0.33
1.06
0.60
0.84
0.24
0.77
0.42
0.58
0.17
0.53
Table 11. Single-Ended Ground-Referenced Input, DC-Coupled, RS = 50 Ω; See Figure 59
Nominal
Gain (V/V)
1
2
3.16
5
1
2
RF
(Ω)
200
402
402
402
RG1
(Ω)
200
200
127
80.6
RT
(Ω)
60.4
60.4
66.5
76.8
RIN,se
(Ω)
267
300
205
138
RG2
(Ω) 1
226
226
158
110
Overall
Gain
(V/V) 2
0.9
1.8
2.5
3.6
Differential
Output
Noise
Density
(nV/√Hz)
6.2
9.8
11.8
14.7
Common-Mode Swing at +IN, −IN (V)
+VS = 10 V, −VS = 0 V
+VS = 5 V, −VS = −5 V
VOUT, dm = 2.0 V p-p
VOUT, dm = 2.0 V p-p
VOCM = 3.5 V
VOCM = 0 V
VOCM = 2.0 V
VOCM = 2.5 V
www.BDTIC.com/ADI
1.00 to 1.50
0.66 to 1.00
0.48 to 0.72
0.33 to 0.50
RG2 = RG1 + RTS.
Includes effects of termination match.
Rev. 0 | Page 22 of 28
1.50 to 2.00
1.00 to 1.33
0.72 to 0.96
0.50 to 0.67
−0.25 to +0.25
−0.17 to +0.17
−0.12 to +0.12
−0.08 to +0.08
0.75 to 1.25
0.50 to 0.83
0.36 to 0.60
0.25 to 0.42
ADA4938-1/ADA4938-2
LAYOUT, GROUNDING, AND BYPASSING
As a high speed device, the ADA4938 is sensitive to the
PCB environment in which it operates. Realizing its superior
performance requires attention to the details of high speed
PCB design.
The power supply pins should be bypassed as close to the device
as possible and directly to a nearby ground plane. High frequency
ceramic chip capacitors should be used. It is recommended that
two parallel bypass capacitors (1000 pF and 0.1 μF) be used for
each supply. The 1000 pF capacitor should be placed closer to
the device. Further away, low frequency bypassing should be
provided, using 10 μF tantalum capacitors from each supply
to ground.
The first requirement is a solid ground plane that covers as much of
the board area around the ADA4938 as possible. However, the
area near the feedback resistors (RF), gain resistors (RG), and the
input summing nodes should be cleared of all ground and power
planes (see Figure 65). Clearing the ground and power planes
minimizes any stray capacitance at these nodes and prevents
peaking of the response of the amplifier at high frequencies.
Signal routing should be short and direct to avoid parasitic
effects. Wherever complementary signals exist, a symmetrical
layout should be provided to maximize balanced performance.
When routing differential signals over a long distance, PCB
traces should be close together, and any differential wiring
should be twisted such that loop area is minimized. Doing this
reduces radiated energy and makes the circuit less susceptible
to interference.
The thermal resistance, θJA, is specified for the device, including
the exposed pad, soldered to a high thermal conductivity 4-layer
circuit board, as described in EIA/JESD 51-7. The exposed pad
is electrically isolated from the device; therefore, it may be
connected to a ground plane using vias. Examples of the thermal
attach pad and via structure for the ADA4938-1 are shown in
Figure 66 and Figure 67.
1.30
0.80
www.BDTIC.com/ADI
06592-008
06592-060
1.30 0.80
Figure 66. Recommended PCB Thermal Attach Pad (ADA4938-1)
(Dimensions in Millimeters)
Figure 65. Ground and Power Plane Voiding in Vicinity of RF and RG
1.30
TOP METAL
GROUND PLANE
0.30
PLATED
VIA HOLE
06592-061
POWER PLANE
BOTTOM METAL
Figure 67. Cross-Section of a 4-Layer PCB (ADA4938-1) Showing a Thermal Via Connection to the Buried Ground Plane (Dimensions in Millimeters)
Rev. 0 | Page 23 of 28
ADA4938-1/ADA4938-2
HIGH PERFORMANCE ADC DRIVING
The circuit in Figure 69 shows a simplified front-end connection
for an ADA4938 driving an AD9246, 14-bit, 125 MSPS ADC.
The AD9246 achieves its optimum performance when it is
driven differentially. The ADA4938 eliminates the need for a
transformer to drive the ADC, performs a single-ended-todifferential conversion, buffers the driving signal, and provides
appropriate level shifting for dc coupling.
The ADA4938 is ideally suited for dc-coupled baseband
applications. The circuit in Figure 68 shows a front-end connection
for an ADA4938 driving an AD9446, 16-bit, 80 MSPS ADC.
The AD9446 achieves its optimum performance when it is
driven differentially. The ADA4938 eliminates the need for a
transformer to drive the ADC, performs a single-ended-todifferential conversion, buffers the driving signal, and provides
appropriate level shifting for dc coupling.
The ADA4938 is configured with dual ±5 V supplies and a gain
of ~2 V/V for a single-ended input to differential output. The
76.8 Ω termination resistor, in parallel with the single-ended
input impedance of 137 Ω, provides a 50 Ω dc termination for the
source. The additional 30.1 Ω (120 Ω total) at the inverting input
balances the parallel dc impedance of the 50 Ω source and the
termination resistor driving the noninverting input.
The ADA4938 is configured with a single 10 V supply and unity
gain for a single-ended input to differential output. The 61.9 Ω
termination resistor, in parallel with the single-ended input
impedance of 267 Ω, provides a 50 Ω termination for the source.
The additional 26 Ω (226 Ω total) at the inverting input balances
the parallel impedance of the 50 Ω source and the termination
resistor driving the noninverting input.
The signal generator has a symmetric, ground-referenced
bipolar output. The VOCM pin of the ADA4938 is connected to
the CML pin of the AD9246 to set the output common-mode
level at the appropriate point. A portion of this is fed back to the
summing nodes, biasing −IN and +IN at 0.55 V. For a commonmode voltage of 0.9 V, each ADA4938 output swings between
0.4 V and 1.4 V, providing a 2 V p-p differential output.
The signal generator has a symmetric, ground-referenced bipolar
output. The VOCM pin of the ADA4938 is biased with an external
resistor divider to obtain the desired 3.5 V output commonmode. One-half of the common-mode voltage is fed back to the
summing nodes, biasing −IN and + IN at 1.75 V. For a commonmode voltage of 3.5 V, each ADA4938 output swings between
2.7 V and 4.3 V, providing a 3.2 V p-p differential output.
The output is dc-coupled to a single-pole, low-pass filter. The filter
reduces the noise bandwidth of the amplifier and provides some
level of isolation from the switched capacitor inputs of the ADC.
The AD9246 is set for a 2 V p-p full-scale input by connecting the
SENSE pin to AGND. The inputs of the AD9246 are biased at
1 V by connecting the CML output, as shown in Figure 69.
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The output of the amplifier is dc-coupled to the ADC through a
second-order, low-pass filter with a −3 dB frequency of 50 MHz.
The filter reduces the noise bandwidth of the amplifier and
isolates the driver outputs from the ADC inputs.
The AD9446 is configured for a 4.0 V p-p full-scale input by
setting R1 = R2 = 1 kΩ between the VREF pin and SENSE pin
in Figure 68.
10V
200Ω
5V (A) 3.3V (A) 3.3V (D)
10V
VOCM
61.9Ω
SIGNAL
GENERATOR
30nH
+
ADA4938
AVDD2 AVDD1 DRVDD
VIN+
BUFFER T/H
24.3Ω
47pF
ADC
24.3Ω
30nH
226Ω
AD9446
16
VIN–
CLOCK/
TIMING
200Ω
AGND
REF
SENSE
R1
VREF
06592-054
200Ω
50Ω
R2
Figure 68. ADA4938 Driving an AD9446, 16-Bit, 80 MSPS ADC
200Ω
50Ω
VIN
1.8V
+5V
76.8Ω
90Ω
VOCM
90Ω
33Ω
+
ADA4938
DRVDD
AD9246
10pF
VIN+
33Ω
D13 TO
D0
AGND SENSE CML
30.1Ω
–5V
06592-056
0.1µF
AVDD
VIN–
200Ω
Figure 69. ADA4938 Driving an AD9246, a 14-Bit, 125 MSPS ADC
Rev. 0 | Page 24 of 28
ADA4938-1/ADA4938-2
OUTLINE DIMENSIONS
3.00
BSC SQ
0.60 MAX
0.45
PIN 1
INDICATOR
0.50
0.40
0.30
13
12
2.75
BSC SQ
TOP
VIEW
9
(BOTTOM VIEW) 4
8
5
0.25 MIN
1.50 REF
0.80 MAX
0.65 TYP
12° MAX
1
EXPOSED
PAD
0.50
BSC
1.00
0.85
0.80
16
PIN 1
INDICATOR
*1.45
1.30 SQ
1.15
0.05 MAX
0.02 NOM
SEATING
PLANE
0.30
0.23
0.18
0.20 REF
*COMPLIANT TO JEDEC STANDARDS MO-220-VEED-2
EXCEPT FOR EXPOSED PAD DIMENSION.
Figure 70. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
3 mm × 3 mm Body
(CP-16-2)
Dimensions shown in millimeters
0.60 MAX
4.00
BSC SQ
0.60 MAX
www.BDTIC.com/ADI
PIN 1
INDICATOR
TOP
VIEW
PIN 1
INDICATOR
0.50
BSC
3.75
BSC SQ
12° MAX
SEATING
PLANE
0.80 MAX
0.65 TYP
0.30
0.23
0.18
2.25
2.10 SQ
1.95
EXPOSED
PAD
0.50
0.40
0.30
1.00
0.85
0.80
24 1
19
18
(BOTTOM VIEW)
13
12
7
6
0.25 MIN
2.50 REF
0.05 MAX
0.02 NOM
0.20 REF
COPLANARITY
0.08
COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-2
Figure 71. 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
4 mm × 4 mm Body, Very Thin Quad
(CP-24-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADA4938-1ACPZ-R2 1
ADA4938-1ACPZ-RL1
ADA4938-1ACPZ-R71
ADA4938-2ACPZ-R21
ADA4938-2ACPZ-RL1
ADA4938-2ACPZ-R71
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
16-Lead LFCSP_VQ
16-Lead LFCSP_VQ
16-Lead LFCSP_VQ
24-Lead LFCSP_VQ
24-Lead LFCSP_VQ
24-Lead LFCSP_VQ
Z = RoHS Compliant Part.
Rev. 0 | Page 25 of 28
Package Option
CP-16-2
CP-16-2
CP-16-2
CP-24-1
CP-24-1
CP-24-1
Ordering Quantity
5,000
1,500
250
5,000
1,500
250
Branding
H11
H11
H11
ADA4938-1/ADA4938-2
NOTES
www.BDTIC.com/ADI
Rev. 0 | Page 26 of 28
ADA4938-1/ADA4938-2
NOTES
www.BDTIC.com/ADI
Rev. 0 | Page 27 of 28
ADA4938-1/ADA4938-2
NOTES
www.BDTIC.com/ADI
©2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06592-0-11/07(0)
Rev. 0 | Page 28 of 28