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1 Amp/1.5 Amp/2 Amp Synchronous, Step-Down DC-to-DC Converters ADP2105/ADP2106/ADP2107 FEATURES GENERAL DESCRIPTION Extremely high 97% efficiency Ultralow quiescent current: 20 μA 1.2 MHz switching frequency 0.1 μA shutdown supply current Maximum load current ADP2105: 1 A ADP2106: 1.5 A ADP2107: 2 A Input voltage: 2.7 V to 5.5 V Output voltage: 0.8 V to VIN Maximum duty cycle: 100% Smoothly transitions into low dropout (LDO) mode Internal synchronous rectifier Small 16-lead 4 mm × 4 mm LFCSP_VQ package Optimized for small ceramic output capacitors Enable/shutdown logic input Undervoltage lockout Soft start The ADP2105/ADP2106/ADP2107 are low quiescent current, synchronous, step-down dc-to-dc converters in a compact 4 mm × 4 mm LFCSP_VQ package. At medium to high load currents, these devices use a current mode, constant frequency pulsewidth modulation (PWM) control scheme for excellent stability and transient response. To ensure the longest battery life in portable applications, the ADP2105/ADP2106/ADP2107 use a pulse frequency modulation (PFM) control scheme under light load conditions that reduces switching frequency to save power. APPLICATIONS The ADP2105/ADP2106/ADP2107 run from input voltages of 2.7 V to 5.5 V, allowing single Li+/Li− polymer cell, multiple alkaline/NiMH cells, PCMCIA, and other standard power sources. The output voltage of ADP2105/ADP2106/ADP2107 is adjustable from 0.8 V to the input voltage (indicated by ADJ), whereas the ADP2105/ADP2106/ADP2107 are available in preset output voltage options of 3.3 V, 1.8 V, 1.5 V, and 1.2 V (indicated by x.x V). Each of these variations is available in three maximum current levels: 1 A (ADP2105), 1.5 A (ADP2106), and 2 A (ADP2107). The power switch and synchronous rectifier are integrated for minimal external part count and high efficiency. During logic controlled shutdown, the input is disconnected from the output, and it draws less than 0.1 μA from the input source. Other key features include undervoltage lockout to prevent deep battery discharge and programmable soft start to limit inrush current at startup. www.BDTIC.com/ADI Mobile handsets PDAs and palmtop computers Telecommunication/networking equipment Set top boxes Audio/video consumer electronics TYPICAL OPERATING CIRCUIT 0.1μF VIN 10Ω 100 VIN = 3.3V INPUT VOLTAGE = 2.7V TO 5.5V VOUT = 2.5V VIN = 3.6V 95 10μF OFF 16 15 14 13 FB GND IN PWIN1 OUTPUT VOLTAGE = 2.5V LX2 12 1 EN 2μH 2 GND PGND 11 ADP2107-ADJ 85kΩ LX1 10 3 GND PWIN2 9 4 GND 5 70kΩ SS 40kΩ AGND NC 6 7 8 80 FB VIN VIN = 5V 85 4.7μF 10μF LOAD 0A TO 2A 75 1nF 0 200 400 600 800 1000 1200 1400 1600 1800 2000 LOAD CURRENT (mA) 120pF NC = NO CONNECT 06079-002 COMP 10μF 90 06079-001 ON EFFICIENCY (%) FB Figure 2. Efficiency vs. Load Current for the ADP2107 with VOUT = 2.5 V Figure 1. Circuit Configuration of ADP2107 with VOUT = 2.5 V Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006–2008 Analog Devices, Inc. All rights reserved. ADP2105/ADP2106/ADP2107 TABLE OF CONTENTS Features .............................................................................................. 1 External Component Selection ................................................ 16 Applications ....................................................................................... 1 Setting the Output Voltage ........................................................ 16 General Description ......................................................................... 1 Inductor Selection ...................................................................... 17 Typical Operating Circuit ................................................................ 1 Output Capacitor Selection....................................................... 18 Revision History ............................................................................... 2 Input Capacitor Selection .......................................................... 18 Functional Block Diagram .............................................................. 3 Input Filter................................................................................... 19 Specifications..................................................................................... 4 Soft Start Period.......................................................................... 19 Absolute Maximum Ratings............................................................ 6 Loop Compensation .................................................................. 19 Thermal Resistance ...................................................................... 6 Bode Plots .................................................................................... 20 Boundary Condition .................................................................... 6 Load Transient Response .......................................................... 21 ESD Caution .................................................................................. 6 Efficiency Considerations ......................................................... 22 Pin Configuration and Function Descriptions ............................. 7 Thermal Considerations............................................................ 22 Typical Performance Characteristics ............................................. 8 Design Example .............................................................................. 24 Theory of Operation ...................................................................... 14 External Component Recommendations .................................... 25 Control Scheme .......................................................................... 14 Circuit Board Layout Recommendations ................................... 27 PWM Mode Operation.............................................................. 14 Evaluation Board ............................................................................ 28 PFM Mode Operation................................................................ 14 Evaluation Board Schematic for ADP2107 (1.8 V) ............... 28 Pulse-Skipping Threshold ......................................................... 14 100% Duty Cycle Operation (LDO Mode) ............................. 14 Recommended PCB Board Layout (Evaluation Board Layout) ....................................................................................................... 28 Slope Compensation .................................................................. 15 Application Circuits ....................................................................... 30 Design Features ........................................................................... 15 Outline Dimensions ....................................................................... 33 Applications Information .............................................................. 16 Ordering Guide .......................................................................... 33 www.BDTIC.com/ADI REVISION HISTORY 9/08—Rev. B to Rev. C Changes to Table Summary Statement .......................................... 4 Changes to LX Minimum On-Time Parameter, Table 1 ............. 5 7/08—Rev. A to Rev. B Changes to General Description Section ...................................... 1 Changes to Figure 3 .......................................................................... 3 Changes to Table 1 ............................................................................ 4 Changes to Table 2 ............................................................................ 6 Changes to Figure 4 .......................................................................... 7 Changes to Table 4 ............................................................................ 7 Changes to Figure 26 ...................................................................... 11 Changes to Figure 31 Through Figure 34 .................................... 12 Changes to Figure 35 ...................................................................... 13 Changes to PMW Mode Operation Section and Pulse Skipping Threshold Section ........................................................................... 14 Changes to Slope Compensation Section .................................... 15 Changes to Setting the Output Voltage Section ........................ 16 Changes to Figure 37 ...................................................................... 16 Changes to Inductor Selection Section........................................ 17 Changes to Input Capacitor Selection Section ........................... 18 Changes to Figure 47 through Figure 52 ..................................... 21 Changes to Transition Losses Section and Thermal Considerations Section .................................................................. 22 Changes to Table 11 ....................................................................... 25 Changes to Circuit Board Layout Recommendations Section..27 Changes to Table 12 ....................................................................... 26 Changes to Figure 53...................................................................... 28 Changes to Figure 56 Through Figure 57.................................... 30 Changes to Figure 58 Through Figure 59.................................... 31 Changes to Outline Dimensions .................................................. 33 3/07—Rev. 0 to Rev. A Updated Format .................................................................. Universal Changes to Output Characteristics and LX (Switch Node) Characteristics Sections ...................................3 Changes to Typical Performance Characteristics Section ...........7 Changes to Load Transient Response Section ............................ 21 7/06—Revision 0: Initial Version Rev. C | Page 2 of 36 ADP2105/ADP2106/ADP2107 FUNCTIONAL BLOCK DIAGRAM COMP 5 SS 6 14 IN SOFT START 9 PWIN2 REFERENCE 0.8V CURRENT SENSE AMPLIFIER 13 PWIN1 FB 16 FB 16 GM ERROR AMP PWM/ PFM CONTROL AGND 7 GND 2 FOR PRESET VOLTAGE OPTIONS ONLY DRIVER AND ANTISHOOT THROUGH GND 3 GND 4 CURRENT LIMIT 10 LX1 12 LX2 SLOPE COMPENSATION NC 8 GND 15 OSCILLATOR ZERO CROSS COMPARATOR 11 PGND www.BDTIC.com/ADI Figure 3. Rev. C | Page 3 of 36 06079-037 THERMAL SHUTDOWN EN 1 ADP2105/ADP2106/ADP2107 SPECIFICATIONS VIN = 3.6 V @ TA = 25°C, unless otherwise noted. 1 Table 1. Parameter INPUT CHARACTERISTICS Input Voltage Range Undervoltage Lockout Threshold Min Typ 2.7 Max Unit Conditions 5.5 V V V V V mV −40°C ≤ TJ ≤ +125°C VIN rising VIN rising, −40°C ≤ TJ ≤ +125°C VIN falling VIN falling, −40°C ≤ TJ ≤ +125°C VIN falling V V V 2.4 2.2 2.6 2.2 2.0 Undervoltage Lockout Hysteresis 2 OUTPUT CHARACTERISTICS Output Regulation Voltage 2.5 200 3.267 3.3 3.3 3.201 1.782 1.236 V V V 0.33 0.3 VIN %/A %/A %/A %/V %/V V 3.3 V, load = 10 mA 3.3 V, VIN = 3.6 V to 5.5 V, no load to full load 3.3 V, VIN = 3.6 V to 5.5 V, no load to full load, −40°C ≤ TJ ≤ +125°C 1.8 V, load = 10 mA 1.8 V, VIN = 2.7 V to 5.5 V, no load to full load 1.8 V, VIN = 2.7 V to 5.5 V, no load to full load, −40°C ≤ TJ ≤ +125°C 1.5, load = 10 mA ADP210x-1.5 V, VIN = 2.7 V to 5.5 V, no load to full load ADP210x-1.5 V, VIN = 2.7 V to 5.5 V, no load to full load, −40°C ≤ TJ ≤ +125°C 1.2 V, load = 10 mA 1.2 V, VIN = 2.7 V to 5.5 V, no load to full load 1.2 V, VIN = 2.7 V to 5.5 V, no load to full load, −40°C ≤ TJ ≤ +125°C ADP2105 ADP2106 ADP2107 ADP2105, measured in servo loop ADP2106 and ADP2107, measured in servo loop ADJ V V μA μA μA μA μA μA μA μA μA ADJ ADJ, −40°C ≤ TJ ≤ +125°C ADJ, −40°C ≤ TJ ≤ +125°C 1.2 V output voltage 1.2 V output voltage, −40°C ≤ TJ ≤ +125°C 1.5 V output voltage 1.5 V output voltage, −40°C ≤ TJ ≤ +125°C 1.8 V output voltage 1.8 V output voltage, −40°C ≤ TJ ≤ +125°C 3.3 V output voltage 3.3 V output voltage, −40°C ≤ TJ ≤ +125°C 3.399 1.8 1.8 1.746 1.485 3.333 1.818 1.854 1.5 1.5 1.455 1.515 1.545 V V V V V V www.BDTIC.com/ADI 1.188 1.2 1.2 1.164 Load Regulation 0.4 0.5 0.6 0.1 0.1 Line Regulation 3 Output Voltage Range FEEDBACK CHARACTERISTICS FB Regulation Voltage FB Bias Current 0.8 1.212 0.8 0.784 −0.1 0.816 +0.1 3 6 4 8 5 10 10 20 Rev. C | Page 4 of 36 ADP2105/ADP2106/ADP2107 Parameter INPUT CURRENT CHARACTERISTICS IN Operating Current Min Typ Max Unit Conditions 30 μA μA μA 30 μA 1 μA ADP210x(ADJ), VFB = 0.9 V ADP210x(ADJ), VFB = 0.9 V, −40°C ≤ TJ ≤ +125°C ADP210x(x.x V) output voltage 10% above regulation voltage ADP210x(x.x V) output voltage 10% above regulation voltage, −40°C ≤ TJ ≤ +125°C VEN = 0 V 20 20 IN Shutdown Current4 LX (SWITCH) NODE CHARACTERISTICS LX On Resistance 4 0.1 190 165 mΩ mΩ mΩ mΩ 230 mΩ mΩ 140 mΩ mΩ 270 100 160 90 LX Leakage Current4, 5 LX Peak Current Limit5 0.1 2.9 2.6 1 3.3 2.25 2.0 2.6 μA A A A A A A ns P-channel switch, ADP2105 P-channel switch, ADP2105, −40°C ≤ TJ ≤ +125°C P-channel switch, ADP2106 and ADP2107 P-channel switch, ADP2106 and ADP2107, −40°C ≤ TJ ≤ +125°C N-channel synchronous rectifier, ADP2105 N-channel synchronous rectifier, ADP2105, −40°C ≤ TJ ≤ +125°C N-channel synchronous rectifier, ADP2106 and ADP2107 N-channel synchronous rectifier, ADP2106 and ADP2107, −40°C ≤ TJ ≤ +125°C VIN = 5.5 V, VLX = 0 V, 5.5 V P-channel switch, ADP2107 P-channel switch, ADP2107, −40°C ≤ TJ ≤ +125°C P-channel switch, ADP2106 P-channel switch, ADP2106, −40°C ≤ TJ ≤ +125°C P-channel switch, ADP2105 P-channel switch, ADP2105, −40°C ≤ TJ ≤ +125°C In PWM mode of operation, −40°C ≤ TJ ≤ +125°C V V μA μA MHz MHz μs VIN = 2.7 V to 5.5 V, −40°C ≤ TJ ≤ +125°C VIN = 2.7 V to 5.5 V, −40°C ≤ TJ ≤ +125°C VIN = 5.5 V, VEN = 0 V, 5.5 V VIN = 5.5 V, VEN = 0 V, 5.5 V, −40°C ≤ TJ ≤ +125°C VIN = 2.7 V to 5.5 V VIN = 2.7 V to 5.5 V, −40°C ≤ TJ ≤ +125°C CSS = 1 nF www.BDTIC.com/ADI 1.5 1.3 LX Minimum On-Time ENABLE CHARACTERISTICS EN Input High Voltage EN Input Low Voltage EN Input Leakage Current 1.8 110 2 0.4 −0.1 −1 OSCILLATOR FREQUENCY SOFT START PERIOD THERMAL CHARACTERISTICS Thermal Shutdown Threshold Thermal Shutdown Hysteresis COMPENSATOR TRANSCONDUCTANCE (gm) CURRENT SENSE AMPLIFIER GAIN (GCS)2 +1 1.2 1 750 1000 1.4 1200 50 °C °C μA/V 1.875 2.8125 3.625 A/V A/V A/V 140 40 1 ADP2105 ADP2106 ADP2107 All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). Typical values are at TA = 25°C. Guaranteed by design. The ADP2105/ADP2106/ADP2107 line regulation was measured in a servo loop on the automated test equipment that adjusts the feedback voltage to achieve a specific COMP voltage. 4 All LX (switch) node characteristics are guaranteed only when the LX1 pin and LX2 pin are tied together. 5 These specifications are guaranteed from −40°C to +85°C. 2 3 Rev. C | Page 5 of 36 ADP2105/ADP2106/ADP2107 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 2. Parameter IN, EN, SS, COMP, FB to AGND LX1, LX2 to PGND PWIN1, PWIN2 to PGND PGND to AGND GND to AGND PWIN1, PWIN2 to IN Operating Junction Temperature Range Storage Temperature Range Soldering Conditions Rating −0.3 V to +6 V −0.3 V to (VIN + 0.3 V) −0.3 V to +6 V −0.3 V to +0.3 V −0.3 V to +0.3 V −0.3 V to +0.3 V −40°C to +125°C −65°C to +150°C JEDEC J-STD-020 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 3. Thermal Resistance Package Type 16-Lead LFCSP_VQ/QFN Maximum Power Dissipation θJA 40 1 Unit °C/W W BOUNDARY CONDITION Natural convection, 4-layer board, exposed pad soldered to the PCB. ESD CAUTION www.BDTIC.com/ADI Rev. C | Page 6 of 36 ADP2105/ADP2106/ADP2107 13 PWIN1 14 IN 15 GND 16 FB PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN 1 INDICATOR 12 LX2 EN 1 11 PGND 10 LX1 9 PWIN2 NC = NO CONNECT 06079-003 NC 8 COMP 5 AGND 7 GND 4 TOP VIEW (Not to Scale) GND 2 SS 6 GND 3 ADP2105/ ADP2106/ ADP2107 Figure 4. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 Mnemonic EN 2, 3, 4, 15 GND 5 COMP 6 SS 7 AGND 8 9, 13 NC PWIN2, PWIN1 10, 12 LX1, LX2 11 PGND 14 IN 16 FB Description Enable Input. Drive EN high to turn on the device. Drive EN low to turn off the device and reduce the input current to 0.1 μA. Test Pins. These pins are used for internal testing and are not ground return pins. These pins are to be tied to the AGND plane as close as possible to the ADP2105/ADP2106/ADP2107. Feedback Loop Compensation Node. COMP is the output of the internal transconductance error amplifier. Place a series RC network from COMP to AGND to compensate the converter. See the Loop Compensation section. Soft Start Input. Place a capacitor from SS to AGND to set the soft start period. A 1 nF capacitor sets a 1 ms soft start period. Analog Ground. Connect the ground of the compensation components, the soft start capacitor, and the voltage divider on the FB pin to the AGND pin as close as possible to the ADP2105/ ADP2106/ADP2107. The AGND is also to be connected to the exposed pad of ADP2105/ADP2106/ADP2107. No Connect. This is not internally connected and can be connected to other pins or left unconnected. Power Source Inputs. The source of the PFET high-side switch. Bypass each PWIN pin to the nearest PGND plane with a 4.7 μF or greater capacitor as close as possible to the ADP2105/ADP2106/ ADP2107. See the Input Capacitor Selection section. Switch Outputs. The drain of the P-channel power switch and N-channel synchronous rectifier. These pins are to be tied together and connected to the output LC filter between LX and the output voltage. Power Ground. Connect the ground return of all input and output capacitors to the PGND pin using a power ground plane as close as possible to the ADP2105/ADP2106/ADP2107. The PGND is then to be connected to the exposed pad of the ADP2105/ADP2106/ADP2107. Power Input. The power source for the ADP2105/ADP2106/ADP2107 internal circuitry. Connect IN and PWIN1 with a 10 Ω resistor as close as possible to the ADP2105/ADP2106/ADP2107. Bypass IN to AGND with a 0.1 μF or greater capacitor. See the Input Filter section. Output Voltage Sense or Feedback Input. For fixed output versions, connect to the output voltage. For adjustable versions, FB is the input to the error amplifier. Drive FB through a resistive voltage divider to set the output voltage. The FB regulation voltage is 0.8 V. www.BDTIC.com/ADI Rev. C | Page 7 of 36 ADP2105/ADP2106/ADP2107 TYPICAL PERFORMANCE CHARACTERISTICS 100 100 95 95 VIN = 3.6V EFFICIENCY (%) 80 VIN = 4.2V 75 VIN = 5.5V INDUCTOR: SD14, 2.5µH DCR: 60mΩ TA = 25°C 1 VIN = 4.2V VIN = 5.5V 80 75 65 60 85 10 70 65 1000 100 INDUCTOR: SD3814, 3.3µH DCR: 93mΩ TA = 25°C 1 10 LOAD CURRENT (mA) 1000 100 LOAD CURRENT (mA) Figure 5. Efficiency—ADP2105 (1.2 V Output) Figure 8. Efficiency—ADP2105 (1.8 V Output) 100 100 VIN = 3.6V 95 95 90 90 VIN = 5.5V VIN = 4.2V VIN = 2.7V VIN = 3.6V 85 EFFICIENCY (%) EFFICIENCY (%) 06079-086 70 VIN = 2.7V VIN = 3.6V 90 VIN = 2.7V 85 06079-084 EFFICIENCY (%) 90 85 80 80 VIN = 4.2V 75 70 www.BDTIC.com/ADI 75 VIN = 5.5V 65 70 1 10 1 10 Figure 6. Efficiency—ADP2105 (3.3 V Output) 10k Figure 9. Efficiency—ADP2106 (1.2 V Output) 100 100 VIN = 3.6V 95 90 95 90 VIN = 2.7V 85 EFFICIENCY (%) 85 VIN = 4.2V 80 75 VIN = 5.5V 70 65 VIN = 5.5V 80 VIN = 4.2V 75 70 65 60 60 INDUCTOR: D62LCB, 2µH DCR: 28mΩ TA = 25°C 55 1 10 100 1k 06079-062 EFFICIENCY (%) 1k LOAD CURRENT (mA) LOAD CURRENT (mA) 50 100 06079-008 50 1000 100 INDUCTOR: D62LCB, 2µH DCR: 28mΩ TA = 25°C 55 VIN = 3.6V INDUCTOR: D62LCB, 3.3µH DCR: 47mΩ TA = 25°C 55 50 10k LOAD CURRENT (mA) 1 10 100 1k LOAD CURRENT (mA) Figure 7. Efficiency—ADP2106 (1.8 V Output) Figure 10. Efficiency—ADP2106 (3.3 V Output) Rev. C | Page 8 of 36 06079-053 60 06079-085 60 INDUCTOR: CDRH5D18, 4.1μH DCR: 43mΩ TA = 25°C 65 10k ADP2105/ADP2106/ADP2107 100 100 95 95 90 VIN = 2.7V 85 EFFICIENCY (%) 80 VIN = 4.2V 75 70 VIN = 5.5V 65 VIN = 4.2V 80 VIN = 5.5V 75 70 65 60 50 1 10 100 06079-010 55 50 10k 1k INDUCTOR: D62LCB, 1.5µH DCR: 21mΩ TA = 25°C 55 1 10 LOAD CURRENT (mA) Figure 14. Efficiency—ADP2107 (1.8 V) 1.23 100 95 1.22 VIN = 5.5V VIN = 4.2V 75 70 65 2.7V, +25°C 3.6V, +25°C 5.5V, +25°C 2.7V, +125°C 3.6V, +125°C 5.5V, +125°C 1.21 1.20 1.19 www.BDTIC.com/ADI 60 INDUCTOR: CDRH5D28, 2.5µH DCR: 13mΩ TA = 25°C 55 50 2.7V, –40°C 3.6V, –40°C 5.5V, –40°C VIN = 3.6V 1 10 100 1.18 06079-054 EFFICIENCY (%) OUTPUT VOLTAGE (V) 90 80 10k 1k LOAD CURRENT (mA) Figure 11. Efficiency—ADP2107 (1.2 V) 85 100 06079-063 60 INDUCTOR: SD12, 1.2µH DCR: 37mΩ TA = 25°C 1.17 0.01 10k 1k 0.1 1 06079-082 EFFICIENCY (%) VIN = 2.7V 90 VIN = 3.6V 85 VIN = 3.6V 10 100 1k 10k LOAD CURRENT (mA) LOAD CURRENT (mA) Figure 12. Efficiency—ADP2107 (3.3 V) Figure 15. Output Voltage Accuracy—ADP2107 (1.2 V) 1.85 3.38 3.36 3.6V, –40°C 5.5V, –40°C 3.6V, +25°C 5.5V, +25°C 3.6V, +125°C 5.5V, +125°C OUTPUT VOLTAGE (V) 1.81 1.79 3.34 3.32 3.30 3.28 3.26 1.77 1.75 0.1 1 2.7V, +25°C 3.6V, +25°C 5.5V, +25°C 10 2.7V, +125°C 3.6V, +125°C 5.5V, +125°C 100 1k 3.24 3.22 0.01 10k LOAD CURRENT (mA) 06079-081 2.7V, –40°C 3.6V, –40°C 5.5V, –40°C 06079-064 OUTPUT VOLTAGE (V) 1.83 0.1 1 10 100 1k LOAD CURRENT (mA) Figure 13. Output Voltage Accuracy—ADP2107 (1.8 V) Figure 16. Output Voltage Accuracy—ADP2107 (3.3 V) Rev. C | Page 9 of 36 10k ADP2105/ADP2106/ADP2107 10k 190 SWITCH ON RESISTANCE (mΩ) 1k +25°C –40°C 10 1 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4 4.8 PMOS POWER SWITCH 150 140 130 120 NMOS SYNCHRONOUS RECTIFIER 110 06079-016 +125°C 160 100 2.7 5.2 06079-093 100 170 3.0 3.3 INPUT VOLTAGE (V) Figure 17. Quiescent Current vs. Input Voltage SWITCH ON RESISTANCE (mΩ) FEEDBACK VOLTAGE (V) 5.4 PMOS POWER SWITCH 0.800 0.799 0.798 100 80 NMOS SYNCHRONOUS RECTIFIER 60 40 www.BDTIC.com/ADI 0.797 06079-017 0.796 –20 0 20 40 60 80 100 20 0 2.7 120 125 TA = 25°C 3.0 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 INPUT VOLTAGE (V) TEMPERATURE (°C) Figure 21. Switch On Resistance vs. Input Voltage—ADP2106 and ADP2107 Figure 18. Feedback Voltage vs. Temperature 1260 1.75 1.70 1250 1.60 1.55 ADP2105 (1A) 1.50 1.45 1.40 1.30 TA = 25°C 3.0 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 06079-073 1.35 5.7 1240 1230 +125°C 1220 +25°C –40°C 1210 1200 1190 2.7 06079-021 SWITCHING FREQUENCY (kHz) 1.65 PEAK CURRENT LIMIT (A) 5.1 120 0.801 1.25 2.7 4.8 Figure 20. Switch On Resistance vs. Input Voltage—ADP2105 0.802 0.795 –40 3.6 3.9 4.2 4.5 INPUT VOLTAGE (V) 06079-018 QUIESCENT CURRENT (µA) 180 3.0 3.3 3.6 3.9 4.2 4.5 4.8 5.1 INPUT VOLTAGE (V) INPUT VOLTAGE (V) Figure 22. Switching Frequency vs. Input Voltage Figure 19. Peak Current Limit of ADP2105 Rev. C | Page 10 of 36 5.4 ADP2105/ADP2106/ADP2107 2.35 LX (SWITCH) NODE 2.30 3 ADP2106 (1.5A) 2.20 2.15 INDUCTOR CURRENT 2.05 2.00 1 1.95 OUTPUT VOLTAGE 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 06079-074 TA = 25°C 3.0 CH1 1V CH3 5V 5.7 INPUT VOLTAGE (V) Figure 23. Peak Current Limit of ADP2106 ADP2107 (2A) 2.80 2.75 2.70 2.65 PULSE-SKIPPING THRESHOLD CURRENT (mA) 2.85 120 105 90 VOUT = 1.2V 75 60 45 VOUT = 1.8V VOUT = 2.5V www.BDTIC.com/ADI 2.60 2.55 TA = 25°C 3.0 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 06079-071 PEAK CURRENT LIMIT (A) 2.90 30 15 0 2.7 5.7 3.0 3.3 3.6 3.9 TA = 25°C 4.2 4.5 4.8 5.1 5.4 5.7 INPUT VOLTAGE (V) INPUT VOLTAGE (V) Figure 27. Pulse-Skipping Threshold vs. Input Voltage for ADP2105 Figure 24. Peak Current Limit of ADP2107 195 135 120 105 VOUT = 1.2V 90 75 60 VOUT = 2.5V VOUT = 1.8V 15 TA = 25°C 3.0 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 06079-067 30 5.7 PULSE-SKIPPING THRESHOLD CURRENT (mA) 150 0 2.7 1.78V 135 2.95 45 A CH1 Figure 26. Short -Circuit Response at Output 3.00 2.50 2.7 M 10µs T 45.8% CH4 1AΩ 06079-066 1.85 2.7 4 06079-072 1.90 PULSE-SKIPPING THRESHOLD CURRENT (mA) Δ: 260mV @: 3.26V 2.10 180 VOUT = 1.2V 165 150 135 VOUT = 1.8V 120 105 90 VOUT = 2.5V 75 60 45 30 15 0 2.7 TA = 25°C 3.0 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 06079-068 PEAK CURRENT LIMIT (A) 2.25 5.7 INPUT VOLTAGE (V) INPUT VOLTAGE (V) Figure 28. Pulse-Skipping Threshold vs. Input Voltage for ADP2107 Figure 25. Pulse-Skipping Threshold vs. Input Voltage for ADP2106 Rev. C | Page 11 of 36 ADP2105/ADP2106/ADP2107 190 170 160 3 PMOS POWER SWITCH 150 LX (SWITCH) NODE 140 1 130 120 OUTPUT VOLTAGE (AC-COUPLED) NMOS SYNCHRONOUS RECTIFIER 4 06079-093 110 100 2.7 3.0 3.3 3.6 3.9 4.2 4.5 INPUT VOLTAGE (V) 4.8 5.1 06079-033 SWITCH ON RESISTANCE (mΩ) 180 INDUCTOR CURRENT CH1 50mV CH3 2V 5.4 CH4 200mAΩ M 400ns T 17.4% A CH3 3.88V Figure 32. DCM Mode of Operation at Light Load (100 mA) Figure 29. Switch On Resistance vs. Temperature—ADP2105 140 LX (SWITCH) NODE SWITCH ON RESISTANCE (mΩ) 120 PMOS POWER SWITCH 100 3 80 NMOS SYNCHRONOUS RECTIFIER 60 1 www.BDTIC.com/ADI 0 –40 06079-083 20 –20 0 20 40 60 80 100 06079-034 OUTPUT VOLTAGE (AC-COUPLED) 40 INDUCTOR CURRENT 4 CH1 20mV CH3 2V 120 JUNCTION TEMPERATURE (°C) Figure 30. Switch On Resistance vs. Temperature—ADP2106 and ADP2107 CH4 1AΩ M 2µs T 13.4% A CH3 1.84V Figure 33. Minimum Off Time Control at Dropout LX (SWITCH) NODE LX (SWITCH) NODE 3 3 1 1 OUTPUT VOLTAGE (AC-COUPLED) OUTPUT VOLTAGE (AC-COUPLED) CH4 200mAΩ M 2µs T 6% A CH3 06079-031 INDUCTOR CURRENT CH1 50mV CH3 2V INDUCTOR CURRENT 06079-030 4 4 3.88V CH1 20mV CH3 2V Figure 31. PFM Mode of Operation at Very Light Load (10 mA) CH4 1AΩ M 1µs T 17.4% A CH3 3.88V Figure 34. PWM Mode of Operation at Medium/Heavy Load (1.5 A) Rev. C | Page 12 of 36 ADP2105/ADP2106/ADP2107 LX (SWITCH) NODE ENABLE VOLTAGE 3 3 OUTPUT VOLTAGE CHANNEL 3 FREQUENCY = 336.6kHz Δ: 2.86A @: 2.86A 1 INDUCTOR CURRENT INDUCTOR CURRENT OUTPUT VOLTAGE 1 CH1 1V CH3 5V CH4 1AΩ M 4µs T 45% A CH3 1.8V Figure 35. Current Limit Behavior of ADP2107 (Frequency Foldback) 06079-035 4 06079-032 4 CH1 1V CH3 5V CH4 500mAΩ M 400µs T 20.2% A CH1 1.84V Figure 36. Startup and Shutdown Waveform (CSS = 1 nF → SS Time = 1 ms) www.BDTIC.com/ADI Rev. C | Page 13 of 36 ADP2105/ADP2106/ADP2107 THEORY OF OPERATION The ADP2105/ADP2106/ADP2107 are step-down, dc-to-dc converters that use a fixed frequency, peak current mode architecture with an integrated high-side switch and low-side synchronous rectifier. The high 1.2 MHz switching frequency and tiny 16-lead, 4 mm × 4 mm LFCSP_VQ package allow for a small stepdown dc-to-dc converter solution. The integrated high-side switch (P-channel MOSFET) and synchronous rectifier (N-channel MOSFET) yield high efficiency at medium to heavy loads. Light load efficiency is improved by smoothly transitioning to variable frequency PFM mode. The ADP2105/ADP2106/ADP2107 (ADJ) operate with an input voltage from 2.7 V to 5.5 V and regulate an output voltage down to 0.8 V. The ADP2105/ADP2106/ADP2107 are also available with preset output voltage options of 3.3 V, 1.8 V, 1.5 V, and 1.2 V. CONTROL SCHEME The ADP2105/ADP2106/ADP2107 operate with a fixed frequency, peak current mode PWM control architecture at medium to high loads for high efficiency, but shift to a variable frequency PFM control scheme at light loads for lower quiescent current. When operating in fixed frequency PWM mode, the duty cycle of the integrated switches is adjusted to regulate the output voltage, but when operating in PFM mode at light loads, the switching frequency is adjusted to regulate the output voltage. PFM MODE OPERATION The ADP2105/ADP2106/ADP2107 smoothly transition to the variable frequency PFM mode of operation when the load current decreases below the pulse skipping threshold current, switching only as necessary to maintain the output voltage within regulation. When the output voltage dips below regulation, the ADP2105/ ADP2106/ADP2107 enter PWM mode for a few oscillator cycles to increase the output voltage back to regulation. During the wait time between bursts, both power switches are off, and the output capacitor supplies all the load current. Because the output voltage dips and recovers occasionally, the output voltage ripple in this mode is larger than the ripple in the PWM mode of operation. PULSE-SKIPPING THRESHOLD The output current at which the ADP2105/ADP2106/ADP2107 transition from variable frequency PFM control to fixed frequency PWM control is called the pulse-skipping threshold. The pulseskipping threshold is optimized for excellent efficiency over all load currents. The variation of pulse-skipping threshold with input voltage and output voltage is shown in Figure 25, Figure 27, and Figure 28. 100% DUTY CYCLE OPERATION (LDO MODE) As the input voltage drops, approaching the output voltage, the ADP2105/ADP2106/ADP2107 smoothly transition to 100% duty cycle, maintaining the P-channel MOSFET switch-on continuously. This allows the ADP2105/ADP2106/ADP2107 to regulate the output voltage until the drop in input voltage forces the Pchannel MOSFET switch to enter dropout, as shown in the following equation: www.BDTIC.com/ADI The ADP2105/ADP2106/ADP2107 operate in the PWM mode only when the load current is greater than the pulse-skipping threshold current. At load currents below this value, the converter smoothly transitions to the PFM mode of operation. PWM MODE OPERATION In PWM mode, the ADP2105/ADP2106/ADP2107 operate at a fixed frequency of 1.2 MHz set by an internal oscillator. At the start of each oscillator cycle, the P-channel MOSFET switch is turned on, putting a positive voltage across the inductor. Current in the inductor increases until the current sense signal crosses the peak inductor current level that turns off the P-channel MOSFET switch and turns on the N-channel MOSFET synchronous rectifier. This puts a negative voltage across the inductor, causing the inductor current to decrease. The synchronous rectifier stays on for the remainder of the cycle, unless the inductor current reaches zero, which causes the zero-crossing comparator to turn off the N-channel MOSFET. The peak inductor current is set by the voltage on the COMP pin. The COMP pin is the output of a transconductance error amplifier that compares the feedback voltage with an internal 0.8 V reference. VIN(MIN) = IOUT × (RDS(ON) − P + DCRIND) + VOUT(NOM) The ADP2105/ADP2106/ADP2107 achieve 100% duty cycle operation by stretching the P-channel MOSFET switch-on time if the inductor current does not reach the peak inductor current level by the end of the clock cycle. When this happens, the oscillator remains off until the inductor current reaches the peak inductor current level, at which time the switch is turned off and the synchronous rectifier is turned on for a fixed off time. At the end of the fixed off time, another cycle is initiated. As the ADP2105/ADP2106/ADP2107 approach dropout, the switching frequency decreases gradually to smoothly transition to 100% duty cycle operation. Rev. C | Page 14 of 36 ADP2105/ADP2106/ADP2107 SLOPE COMPENSATION Short-Circuit Protection Slope compensation stabilizes the internal current control loop of the ADP2105/ADP2106/ADP2107 when operating beyond 50% duty cycle to prevent subharmonic oscillations. It is implemented by summing a fixed, scaled voltage ramp to the current sense signal during the on-time of the P-channel MOSFET switch. The ADP2105/ADP2106/ADP2107 include frequency foldback to prevent output current runaway on a hard short. When the voltage at the feedback pin falls below 0.3 V, indicating the possibility of a hard short at the output, the switching frequency is reduced to 1/4 of the internal oscillator frequency. The reduction in the switching frequency results in more time for the inductor to discharge, preventing a runaway of output current. The slope compensation ramp value determines the minimum inductor that can be used to prevent subharmonic oscillations at a given output voltage. For slope compensation ramp values, see Table 5. For more information see the Inductor Selection section. Table 5. Slope Compensation Ramp Values Part ADP2105 ADP2106 ADP2107 Slope Compensation Ramp Values 0.72 A/μs 1.07 A/μs 1.38 A/μs Undervoltage Lockout (UVLO) To protect against deep battery discharge, UVLO circuitry is integrated on the ADP2105/ADP2106/ADP2107. If the input voltage drops below the 2.2 V UVLO threshold, the ADP2105/ADP2106/ADP2107 shut down, and both the power switch and synchronous rectifier turn off. When the voltage again rises above the UVLO threshold, the soft start period is initiated, and the part is enabled. Thermal Protection DESIGN FEATURES Drive EN high to turn on the ADP2105/ADP2106/ADP2107. Drive EN low to turn off the ADP2105/ADP2106/ADP2107, reducing the input current below 0.1 μA. To force the ADP2105/ADP2106/ADP2107 to automatically start when input power is applied, connect EN to IN. When shut down, the ADP2105/ADP2106/ADP2107 discharge the soft start capacitor, causing a new soft start cycle every time they are re-enabled. In the event that the ADP2105/ADP2106/ADP2107 junction temperatures rise above 140°C, the thermal shutdown circuit turns off the converter. Extreme junction temperatures can be the result of high current operation, poor circuit board design, and/or high ambient temperature. A 40°C hysteresis is included so that when thermal shutdown occurs, the ADP2105/ADP2106/ ADP2107 do not return to operation until the on-chip temperature drops below 100°C. When coming out of thermal shutdown, soft start is initiated. Synchronous Rectification Soft Start In addition to the P-channel MOSFET switch, the ADP2105/ ADP2106/ADP2107 include an integrated N-channel MOSFET synchronous rectifier. The synchronous rectifier improves efficiency, especially at low output voltage, and reduces cost and board space by eliminating the need for an external rectifier. The ADP2105/ADP2106/ADP2107 include soft start circuitry to limit the output voltage rise time to reduce inrush current at startup. To set the soft start period, connect the soft start capacitor (CSS) from SS to AGND. When the ADP2105/ADP2106/ADP2107 are disabled, or if the input voltage is below the undervoltage lockout threshold, CSS is internally discharged. When the ADP2105/ADP2106/ADP2107 are enabled, CSS is charged through an internal 0.8 μA current source, causing the voltage at SS to rise linearly. The output voltage rises linearly with the voltage at SS. Enable/Shutdown www.BDTIC.com/ADI Current Limit The ADP2105/ADP2106/ADP2107 have protection circuitry to limit the direction and amount of current flowing through the power switch and synchronous rectifier. The positive current limit on the power switch limits the amount of current that can flow from the input to the output, and the negative current limit on the synchronous rectifier prevents the inductor current from reversing direction and flowing out of the load. Rev. C | Page 15 of 36 ADP2105/ADP2106/ADP2107 APPLICATIONS INFORMATION into account when calculating resistor values. The FB bias current can be ignored for a higher divider string current, but this degrades efficiency at very light loads. EXTERNAL COMPONENT SELECTION The external component selection for the ADP2105/ADP2106/ ADP2107 application circuits shown in Figure 37 and Figure 38 depend on input voltage, output voltage, and load current requirements. Additionally, trade-offs between performance parameters like efficiency and transient response can be made by varying the choice of external components. To limit output voltage accuracy degradation due to FB bias current to less than 0.05% (0.5% maximum), ensure that the divider string current is greater than 20 μA. To calculate the desired resistor values, first determine the value of the bottom divider string resistor (RBOT) using the following equation: SETTING THE OUTPUT VOLTAGE RBOT = The output voltage of ADP2105/ADP2106/ADP2107(ADJ) is externally set by a resistive voltage divider from the output voltage to FB. The ratio of the resistive voltage divider sets the output voltage, and the absolute value of those resistors sets the divider string current. For lower divider string currents, the small 10 nA (0.1 μA maximum) FB bias current is to be taken 0.1μF where: VFB = 0.8 V, the internal reference. ISTRING is the resistor divider string current. VIN 10Ω VFB I STRING INPUT VOLTAGE = 2.7V TO 5.5V CIN1 VOUT 16 15 FB ON OFF 1 14 13 GND IN PWIN1 LX2 12 EN OUTPUT VOLTAGE = 1.2V, 1.5V, 1.8V, 3.3V L 2 GND ADP2105/ ADP2106/ ADP2107 VOUT PGND 11 www.BDTIC.com/ADI 3 GND 4 GND COUT LX1 10 PWIN2 9 COMP SS 5 6 VIN CIN2 AGND NC 7 LOAD 8 CSS RCOMP 06079-065 CCOMP NC = NO CONNECT Figure 37. Typical Applications Circuit for Fixed Output Voltage Options of ADP2105/ADP2106/ADP2107(x.x V) 0.1μF VIN 10Ω INPUT VOLTAGE = 2.7V TO 5.5V CIN1 FB OFF 16 15 14 13 FB GND IN PWIN1 LX2 12 1 EN 2 GND 3 GND 4 GND OUTPUT VOLTAGE = 0.8V TO VIN L ADP2105/ ADP2106/ ADP2107 SS 5 6 RTOP LX1 10 PWIN2 9 COMP RCOMP PGND 11 VIN AGND NC 7 COUT LOAD FB CIN2 RBOT 8 CSS CCOMP NC = NO CONNECT 06079-038 ON Figure 38. Typical Applications Circuit for Adjustable Output Voltage Option of ADP2105/ADP2106/ADP2107(ADJ) Rev. C | Page 16 of 36 ADP2105/ADP2106/ADP2107 When RBOT is determined, calculate the value of the top resistor (RTOP) by using the following equation: Ensure that the maximum rms current of the inductor is greater than the maximum load current and that the saturation current of the inductor is greater than the peak current limit of the converter used in the application. ⎡V − VFB ⎤ RTOP = RBOT ⎢ OUT ⎥ ⎣ VFB ⎦ The ADP2105/ADP2106/ADP2107(x.x V) include the resistive voltage divider internally, reducing the external circuitry required. For improved load regulation, connect the FB to the output voltage as close as possible to the load. INDUCTOR SELECTION The high switching frequency of ADP2105/ADP2106/ADP2107 allows for minimal output voltage ripple even with small inductors. The sizing of the inductor is a trade-off between efficiency and transient response. A small inductor leads to larger inductor current ripple that provides excellent transient response but degrades efficiency. Due to the high switching frequency of ADP2105/ADP2106/ADP2107, shielded ferrite core inductors are recommended for their low core losses and low electromagnetic interference (EMI). As a guideline, the inductor peak-to-peak current ripple (ΔIL) is typically set to 1/3 of the maximum load current for optimal transient response and efficiency, as shown in the following equations: V × (V IN − VOUT ) I LOAD (MAX ) ΔI L = OUT ≈ V IN × f SW × L 3 ⇒ LIDEAL = Table 6. Minimum Inductor Value for Common Output Voltage Options for the ADP2105 (1 A) VOUT 1.2 V 1.5 V 1.8 V 2.5 V 3.3 V 2.7 V 1.67 μH 1.68 μH 2.02 μH 2.80 μH 3.70 μH 3.6 V 2.00 μH 2.19 μH 2.25 μH 2.80 μH 3.70 μH where fSW is the switching frequency (1.2 MHz). The ADP2105/ADP2106/ADP2107 use slope compensation in the current control loop to prevent subharmonic oscillations when operating beyond 50% duty cycle. The fixed slope compensation limits the minimum inductor value as a function of output voltage. For the ADP2105 L > (1.12 μH/V) × VOUT 5.5 V 2.35 μH 2.73 μH 3.03 μH 3.41 μH 3.70 μH Table 7. Minimum Inductor Value for Common Output Voltage Options for the ADP2106 (1.5 A) VOUT 1.2 V 1.5 V 1.8 V 2.5 V 3.3 V 2.7 V 1.11 μH 1.25 μH 1.49 μH 2.08 μH 2.74 μH 3.6 V 2.33 μH 1.46 μH 1.50 μH 2.08 μH 2.74 μH VIN 4.2 V 2.43 μH 1.61 μH 1.71 μH 2.08 μH 2.74 μH 5.5 V 1.56 μH 1.82 μH 2.02 μH 2.27 μH 2.74 μH Table 8. Minimum Inductor Value for Common Output Voltage Options for the ADP2107 (2 A) www.BDTIC.com/ADI 2.5 × VOUT × (VIN − VOUT ) μH VIN × I LOAD ( MAX ) VIN 4.2 V 2.14 μH 2.41 μH 2.57 μH 2.80 μH 3.70 μH VOUT 1.2 V 1.5 V 1.8 V 2.5 V 3.3 V 2.7 V 0.83 μH 0.99 μH 1.19 μH 1.65 μH 2.18 μH 3.6 V 1.00 μH 1.09 μH 1.19 μH 1.65 μH 2.18 μH VIN 4.2 V 1.07 μH 1.21 μH 1.29 μH 1.65 μH 2.18 μH 5.5 V 1.17 μH 1.36 μH 1.51 μH 1.70 μH 2.18 μH Table 9. Inductor Recommendations for the ADP2105/ ADP2106/ADP2107 For the ADP2106 L > (0.83 μH/V) × VOUT Vendor Sumida For the ADP2107 L > (0.66 μH/V) × VOUT Toko Inductors 4.7 μH or larger are not recommended because they may cause instability in discontinuous conduction mode under light load conditions. It is also important that the inductor be capable of handling the maximum peak inductor current (IPK) determined by the following equation: Coilcraft Cooper Bussmann ⎛ ΔI ⎞ I PK = I LOAD( MAX ) + ⎜ L ⎟ ⎝ 2 ⎠ Rev. C | Page 17 of 36 Small-Sized Inductors (< 5 mm × 5 mm) CDRH2D14, 3D16, 3D28 1069AS-DB3018, 1098AS-DE2812, 1070AS-DB3020 LPS3015, LPS4012, DO3314 SD3110, SD3112, SD3114, SD3118, SD3812, SD3814 Large-Sized Inductors (> 5 mm × 5 mm) CDRH4D18, 4D22, 4D28, 5D18, 6D12 D52LC, D518LC, D62LCB DO1605T SD10, SD12, SD14, SD52 ADP2105/ADP2106/ADP2107 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 20 0 –20 1 –40 2 3 –60 –80 0 2 4 06079-060 –100 14.7µF 0805 X5R MURATA GRM21BR61A475K 210µF 0805 X5R MURATA GRM21BR61A106K 322µF 0805 X5R MURATA GRM21BR60J226M 6 VOLTAGE (VDC) Figure 40. Percentage Drop-In Capacitance vs. DC Bias for Ceramic Capacitors (Information Provided by Murata Corporation) For example, to get 20 μF output capacitance at an output voltage of 2.5 V, based on Figure 40, as well as to give some margin for temperature variance, a 22 μF and a 10 μF capacitor are to be used in parallel to ensure that the output capacitance is sufficient under all conditions for stable behavior. www.BDTIC.com/ADI Table 10. Recommended Input and Output Capacitor Selection for the ADP2105/ADP2106/ADP2107 06079-070 OVERSHOOT OF OUTPUT VOLTAGE (%) The output capacitor selection affects both the output voltage ripple and the loop dynamics of the converter. For a given loop crossover frequency (the frequency at which the loop gain drops to 0 dB), the maximum voltage transient excursion (overshoot) is inversely proportional to the value of the output capacitor. Therefore, larger output capacitors result in improved load transient response. To minimize the effects of the dc-to-dc converter switching, the crossover frequency of the compensation loop should be less than 1/10 of the switching frequency. Higher crossover frequency leads to faster settling time for a load transient response, but it can also cause ringing due to poor phase margin. Lower crossover frequency helps to provide stable operation but needs large output capacitors to achieve competitive overshoot specifications. Therefore, the optimal crossover frequency for the control loop of ADP2105/ADP2106/ADP2107 is 80 kHz, 1/15 of the switching frequency. For a crossover frequency of 80 kHz, Figure 39 shows the maximum output voltage excursion during a 1 A load transient, as the product of the output voltage and the output capacitor is varied. Choose the output capacitor based on the desired load transient response and target output voltage. When choosing output capacitors, it is also important to account for the loss of capacitance due to output voltage dc bias. Figure 40 shows the loss of capacitance due to output voltage dc bias for three X5R MLCC capacitors from Murata. CAPACITANCE CHANGE (%) OUTPUT CAPACITOR SELECTION 20 25 30 35 40 45 50 55 60 65 70 OUTPUT CAPACITOR × OUTPUT VOLTAGE (μC) Figure 39. Percentage Overshoot for a 1 A Load Transient Response vs. Output Capacitor × Output Voltage For example, if the desired 1 A load transient response (overshoot) is 5% for an output voltage of 2.5 V, then from Figure 39 Output Capacitor × Output Voltage = 50 μC ⇒ Output Capacitor = 50 μ C 2 .5 ≈ 20 μ F The ADP2105/ADP2106/ADP2107 have been designed for operation with small ceramic output capacitors that have low ESR and ESL. Therefore, they are comfortably able to meet tight output voltage ripple specifications. X5R or X7R dielectrics are recommended with a voltage rating of 6.3 V or 10 V. Y5V and Z5U dielectrics are not recommended, due to their poor temperature and dc bias characteristics. Table 10 shows a list of recommended MLCC capacitors from Murata and Taiyo Yuden. Capacitor 4.7 μF, 10 V X5R 0805 10 μF, 10 V X5R 0805 22 μF, 6.3 V X5R 0805 Vendor Murata Taiyo Yuden GRM21BR61A475K LMK212BJ475KG GRM21BR61A106K LMK212BJ106KG GRM21BR60J226M JMK212BJ226MG INPUT CAPACITOR SELECTION The input capacitor reduces input voltage ripple caused by the switch currents on the PWIN pins. Place the input capacitors as close as possible to the PWIN pins. Select an input capacitor capable of withstanding the rms input current for the maximum load current in your application. For the ADP2105, it is recommended that each PWIN pin be bypassed with a 4.7 μF or larger input capacitor. For the ADP2106, bypass each PWIN pin with a 10 μF and a 4.7 μF capacitor, and for the ADP2107, bypass each PWIN pin with a 10 μF capacitor. As with the output capacitor, a low ESR ceramic capacitor is recommended to minimize input voltage ripple. X5R or X7R dielectrics are recommended, with a voltage rating of 6.3 V or 10 V. Y5V and Z5U dielectrics are not recommended due to their poor temperature and dc bias characteristics. Refer to Table 10 for input capacitor recommendations. Rev. C | Page 18 of 36 ADP2105/ADP2106/ADP2107 INPUT FILTER The IN pin is the power source for the ADP2105/ADP2106/ ADP2107 internal circuitry, including the voltage reference and current sense amplifier that are sensitive to power supply noise. To prevent high frequency switching noise on the PWIN pins from corrupting the internal circuitry of the ADP2105/ADP2106/ ADP2107, a low-pass RC filter should be placed between the IN pin and the PWIN1 pin. The suggested input filter consists of a small 0.1 μF ceramic capacitor placed between IN and AGND and a 10 Ω resistor placed between IN and PWIN1. This forms a 150 kHz low-pass filter between PWIN1 and IN that prevents any high frequency noise on PWIN1 from coupling into the IN pin. SOFT START PERIOD To set the soft start period, connect a soft start capacitor (CSS) from SS to AGND. The soft start period varies linearly with the size of the soft start capacitor, as shown in the following equation: TSS = CSS × 109 ms The transconductance error amplifier drives the compensation network that consists of a resistor (RCOMP) and capacitor (CCOMP) connected in series to form a pole and a zero, as shown in the following equation: ⎛ 1 ZCOMP (s) = ⎜⎜ RCOMP + sC COMP ⎝ ⎞ ⎛ 1 + sRCOMP CCOMP ⎟=⎜ ⎟ ⎜ sCCOMP ⎠ ⎝ At the crossover frequency, the gain of the open loop transfer function is unity. For the compensation network impedance at the crossover frequency, this yields the following equation: ⎛ (2π )FCROSS ⎞⎛ COUTVOUT ⎟⎜ ZCOMP (FCROSS ) = ⎜ ⎜ G G ⎟⎜ V m CS REF ⎝ ⎠⎝ ⎞ ⎟ ⎟ ⎠ where: FCROSS = 80 kHz, the crossover frequency of the loop. COUTVOUT is determined from the Output Capacitor Selection section. To ensure that there is sufficient phase margin at the crossover frequency, place the compensator zero at 1/4 of the crossover frequency, as shown in the following equation: For a soft start period of 1 ms, a 1 nF capacitor must be connected between SS and AGND. LOOP COMPENSATION The ADP2105/ADP2106/ADP2107 utilize a transconductance error amplifier to compensate the external voltage loop. The open loop transfer function at angular frequency (s) is given by F (2 π)⎛⎜ CROSS ⎝ 4 ⎞R ⎟ COMP CCOMP = 1 ⎠ Solving the three equations in this section simultaneously yields the value for the compensation resistor and compensation capacitor, as shown in the following equation: www.BDTIC.com/ADI ⎛Z (s) ⎞⎛ V H (s) = GmGCS ⎜⎜ COMP ⎟⎟⎜⎜ REF ⎝ sCOUT ⎠⎝ VOUT ⎞ ⎟ ⎟ ⎠ ⎞ ⎟ ⎟ ⎠ where: VREF is the internal reference voltage (0.8 V). VOUT is the nominal output voltage. ZCOMP(s) is the impedance of the compensation network at the angular frequency. COUT is the output capacitor. gm is the transconductance of the error amplifier (50 μA/V nominal). GCS is the effective transconductance of the current loop. GCS = 1.875 A/V for the ADP2105. GCS = 2.8125 A/V for the ADP2106. GCS = 3.625 A/V for the ADP2107. Rev. C | Page 19 of 36 ⎛ (2 π)FCROSS RCOMP = 0.8 ⎜⎜ ⎝ GmGCS CCOMP = 2 πFCROSS RCOMP ⎞⎛ COUT VOUT ⎟⎜ ⎟⎜ V REF ⎠⎝ ⎞ ⎟ ⎟ ⎠ ADP2105/ADP2106/ADP2107 BODE PLOTS 60 60 ADP2106 ADP2105 50 50 180 0 CROSSOVER OUTPUT VOLTAGE = 1.8V FREQUENCY = 87kHz –10 INPUT VOLTAGE = 5.5V LOAD CURRENT = 1A –20 INDUCTOR = 2.2µH (LPS4012) OUTPUT CAPACITOR = 22µF + 22µF –30 COMPENSATION RESISTOR = 180kΩ COMPENSATION CAPACITOR = 56pF –40 10 100 1 FREQUENCY (kHz) 20 10 135 180 CROSSOVER OUTPUT VOLTAGE = 1.2V –10 FREQUENCY = 79kHz INPUT VOLTAGE = 5.5V LOAD CURRENT = 1A –20 INDUCTOR = 3.3µH (SD3814) OUTPUT CAPACITOR = 22µF + 22µF + 4.7µF –30 COMPENSATION RESISTOR = 267kΩ COMPENSATION CAPACITOR = 39pF –40 1 10 100 FREQUENCY (kHz) 300 NOTES 1. EXTERNAL COMPONENTS WERE CHOSEN FOR A 5% OVERSHOOT FOR A 1A LOAD TRANSIENT. Figure 44. ADP2105 Bode Plot at VIN = 5.5 V, VOUT = 1.2 V and Load = 1 A Figure 41. ADP2106 Bode Plot at VIN = 5.5 V, VOUT = 1.8 V and Load = 1 A 60 60 90 LOOP PHASE 0 300 NOTES 1. EXTERNAL COMPONENTS WERE CHOSEN FOR A 5% OVERSHOOT FOR A 1A LOAD TRANSIENT. 45 PHASE MARGIN = 49° 06079-058 135 LOOP PHASE LOOP GAIN (dB) 10 90 06079-055 LOOP GAIN (dB) PHASE MARGIN = 48° 30 LOOP PHASE (Degrees) 45 30 20 0 LOOP GAIN 0 LOOP GAIN LOOP PHASE (Degrees) 40 40 ADP2106 ADP2107 50 50 0 135 10 Figure 45. ADP2107 Bode Plot at VIN = 5 V, VOUT = 2.5 V and Load = 1 A 60 45 0 90 135 180 CROSSOVER OUTPUT VOLTAGE = 1.2V FREQUENCY = 71kHz –10 INPUT VOLTAGE = 3.6V LOAD CURRENT = 1A –20 INDUCTOR = 3.3µH (SD3814) OUTPUT CAPACITOR = 22µF + 22µF + 4.7µF –30 COMPENSATION RESISTOR = 267kΩ COMPENSATION CAPACITOR = 39pF –40 1 10 100 FREQUENCY (kHz) 300 NOTES 1. EXTERNAL COMPONENTS WERE CHOSEN FOR A 5% OVERSHOOT FOR A 1A LOAD TRANSIENT. Figure 43. ADP2105 Bode Plot at VIN = 3.6 V, VOUT = 1.2 V, and Load = 1 A 0 LOOP GAIN 30 LOOP GAIN (dB) 30 40 LOOP PHASE (Degrees) 0 06079-057 LOOP GAIN (dB) LOOP GAIN 40 LOOP PHASE ADP2107 50 50 10 300 NOTES 1. EXTERNAL COMPONENTS WERE CHOSEN FOR A 10% OVERSHOOT FOR A 1A LOAD TRANSIENT. ADP2105 PHASE MARGIN = 51° 180 CROSSOVER OUTPUT VOLTAGE = 2.5V –10 INPUT VOLTAGE = 5V FREQUENCY = 76kHz LOAD CURRENT = 1A –20 INDUCTOR = 2µH (D62LCB) OUTPUT CAPACITOR = 10µF + 4.7µF –30 COMPENSATION RESISTOR = 70kΩ COMPENSATION CAPACITOR = 120pF –40 1 10 100 FREQUENCY (kHz) 300 Figure 42. ADP2106 Bode Plot at VIN = 3.6 V, VOUT = 1.8 V, and Load = 1 A 20 135 0 06079-059 CROSSOVER OUTPUT VOLTAGE = 1.8V –10 INPUT VOLTAGE = 3.6V FREQUENCY = 83kHz LOAD CURRENT = 1A –20 INDUCTOR = 2.2µH (LPS4012) OUTPUT CAPACITOR = 22µF + 22µF –30 COMPENSATION RESISTOR = 180kΩ COMPENSATION CAPACITOR = 56pF –40 10 100 1 FREQUENCY (kHz) NOTES 1. EXTERNAL COMPONENTS WERE CHOSEN FOR A 5% OVERSHOOT FOR A 1A LOAD TRANSIENT. 60 90 LOOP PHASE www.BDTIC.com/ADI 180 0 20 45 PHASE MARGIN = 70° 20 10 LOOP PHASE 0 90 135 180 CROSSOVER OUTPUT VOLTAGE = 3.3V –10 INPUT VOLTAGE = 5V FREQUENCY = 67kHz LOAD CURRENT = 1A –20 INDUCTOR = 2.5µH (CDRH5D28) OUTPUT CAPACITOR = 10µF + 4.7µF –30 COMPENSATION RESISTOR = 70kΩ COMPENSATION CAPACITOR = 120pF –40 1 10 100 FREQUENCY (kHz) LOOP PHASE (Degrees) LOOP PHASE 45 PHASE MARGIN = 65° 300 NOTES 1. EXTERNAL COMPONENTS WERE CHOSEN FOR A 10% OVERSHOOT FOR A 1A LOAD TRANSIENT. Figure 46. ADP2107 Bode Plot at VIN = 5 V, VOUT = 3.3 V, and Load = 1 A Rev. C | Page 20 of 36 06079-069 10 90 06079-056 LOOP GAIN (dB) PHASE MARGIN = 52° 20 LOOP GAIN (dB) 45 30 0 LOOP GAIN 30 LOOP PHASE (Degrees) LOOP GAIN LOOP PHASE (Degrees) 40 40 ADP2105/ADP2106/ADP2107 LOAD TRANSIENT RESPONSE T T OUTPUT CURRENT OUTPUT CURRENT 3 3 OUTPUT VOLTAGE (AC-COUPLED) OUTPUT VOLTAGE (AC-COUPLED) 2 2 1 1 LX NODE (SWITCH NODE) LX NODE (SWITCH NODE) M 20.0µs T 10.00% A CH3 700mA CH3 700mA Figure 50. 1 A Load Transient Response for ADP2105-1.2 with External Components Chosen for 10% Overshoot Figure 47. 1 A Load Transient Response for ADP2105-1.2 with External Components Chosen for 5% Overshoot T A OUTPUT CAPACITOR: 22µF + 4.7µF INDUCTOR: SD14, 2.5µH COMPENSATION RESISTOR: 135kΩ COMPENSATION CAPACITOR: 82pF 06079-087 OUTPUT CAPACITOR: 22µF + 22µF + 4.7µF INDUCTOR: SD14, 2.5µH COMPENSATION RESISTOR: 270kΩ COMPENSATION CAPACITOR: 39pF M 20.0µs T 10.00% 06079-090 CH1 2.00V CH2 100mV~ CH3 1.00A Ω CH1 2.00V CH2 100mV~ CH3 1.00A Ω T OUTPUT CURRENT OUTPUT CURRENT 3 3 OUTPUT VOLTAGE (AC-COUPLED) 2 2 OUTPUT VOLTAGE (AC-COUPLED) www.BDTIC.com/ADI 1 1 LX NODE (SWITCH NODE) LX NODE (SWITCH NODE) M 20.0µs T 10.00% A CH3 700mA CH3 700mA Figure 51. 1 A Load Transient Response for ADP2105-1.8 with External Components Chosen for 10% Overshoot Figure 48. 1 A Load Transient Response for ADP2105-1.8 with External Components Chosen for 5% Overshoot T A OUTPUT CAPACITOR: 10µF + 10µF INDUCTOR: SD3814, 3.3µH COMPENSATION RESISTOR: 135kΩ COMPENSATION CAPACITOR: 82pF 06079-088 OUTPUT CAPACITOR: 22µF + 22µF INDUCTOR: SD3814, 3.3µH COMPENSATION RESISTOR: 270kΩ COMPENSATION CAPACITOR: 39pF M 20.0µs T 10.00% 06079-091 CH1 2.00V CH2 100mV~ CH3 1.00A Ω CH1 2.00V CH2 100mV~ CH3 1.00A Ω T OUTPUT CURRENT OUTPUT CURRENT 3 3 OUTPUT VOLTAGE (AC-COUPLED) OUTPUT VOLTAGE (AC-COUPLED) 2 2 1 1 LX NODE (SWITCH NODE) M 20.0µs T 10.00% A CH3 700mA OUTPUT CAPACITOR: 22µF + 4.7µF INDUCTOR: CDRH5D18, 4.1µH COMPENSATION RESISTOR: 270kΩ COMPENSATION CAPACITOR: 39pF M 20.0µs T 10.00% A CH3 700mA OUTPUT CAPACITOR: 10µF + 4.7µF INDUCTOR: CDRH5D18, 4.1µH COMPENSATION RESISTOR: 135kΩ COMPENSATION CAPACITOR: 82pF 06079-089 CH1 2.00V CH2 200mV~ CH3 1.00A Ω CH1 2.00V CH2 200mV~ CH3 1.00A Ω Figure 52. 1 A Load Transient Response for ADP2105-3.3 with External Components Chosen for 10% Overshoot Figure 49. 1 A Load Transient Response for ADP2105-3.3 with External Components Chosen for 5% Overshoot Rev. C | Page 21 of 36 06079-092 LX NODE (SWITCH NODE) ADP2105/ADP2106/ADP2107 EFFICIENCY CONSIDERATIONS Transition Losses Efficiency is the ratio of output power to input power. The high efficiency of the ADP2105/ADP2106/ADP2107 has two distinct advantages. First, only a small amount of power is lost in the dcto-dc converter package that reduces thermal constraints. Second, the high efficiency delivers the maximum output power for the given input power, extending battery life in portable applications. Transition losses occur because the P-channel MOSFET power switch cannot turn on or turn off instantaneously. At the middle of an LX (switch) node transition, the power switch is providing all the inductor current, while the source to drain voltage of the power switch is half the input voltage, resulting in power loss. Transition losses increase with load current and input voltage and occur twice for each switching cycle. There are four major sources of power loss in dc-to-dc converters like the ADP2105/ADP2106/ADP2107: • • • • The amount of power loss can be calculated by PTRAN = Power switch conduction losses Inductor losses Switching losses Transition losses V IN × I OUT × (t ON + t OFF ) × f SW 2 where tON and tOFF are the rise time and fall time of the LX (switch) node, and are both approximately 3 ns. THERMAL CONSIDERATIONS Power Switch Conduction Losses Power switch conduction losses are caused by the flow of output current through the P-channel power switch and the N-channel synchronous rectifier, which have internal resistances (RDS(ON)) associated with them. The amount of power loss can be approximated by PSW − COND = [RDS(ON) − P × D + RDS(ON) − N × (1 − D)] × IOUT2 where D = VOUT/VIN. The internal resistance of the power switches increases with temperature but decreases with higher input voltage. Figure 20 and Figure 21 show the change in RDS(ON) vs. input voltage, whereas Figure 29 and Figure 30 show the change in RDS(ON) vs. temperature for both power devices. In most applications, the ADP2105/ADP2106/ADP2107 do not dissipate a lot of heat due to their high efficiency. However, in applications with high ambient temperature, low supply voltage, and high duty cycle, the heat dissipated in the package is large enough that it can cause the junction temperature of the die to exceed the maximum junction temperature of 125°C. Once the junction temperature exceeds 140°C, the converter goes into thermal shutdown. To prevent any permanent damage it recovers only after the junction temperature has decreased below 100°C. Therefore, thermal analysis for the chosen application solution is very important to guarantee reliable performance over all conditions. www.BDTIC.com/ADI Inductor Losses Inductor conduction losses are caused by the flow of current through the inductor, which has an internal resistance (DCR) associated with it. Larger sized inductors have smaller DCR, which can improve inductor conduction losses. Inductor core losses are related to the magnetic permeability of the core material. Because the ADP2105/ADP2106/ADP2107 are high switching frequency dc-to-dc converters, shielded ferrite core material is recommended for its low core losses and low EMI. The total amount of inductor power loss can be calculated by PL = DCR × IOUT2 + Core Losses Switching Losses Switching losses are associated with the current drawn by the driver to turn on and turn off the power devices at the switching frequency. Each time a power device gate is turned on and turned off, the driver transfers a charge ΔQ from the input supply to the gate and then from the gate to ground. The amount of power loss can by calculated by PSW = (CGATE − P + CGATE − N) × VIN2 × fSW The junction temperature of the die is the sum of the ambient temperature of the environment and the temperature rise of the package due to the power dissipation, as shown in the following equation: TJ = TA + TR where: TJ is the junction temperature. TA is the ambient temperature. TR is the rise in temperature of the package due to the power dissipation in the package. The rise in temperature of the package is directly proportional to the power dissipation in the package. The proportionality constant for this relationship is defined as the thermal resistance from the junction of the die to the ambient temperature, as shown in the following equation: TR = θJA × PD where: TR is the rise in temperature of the package. PD is the power dissipation in the package. θJA is the thermal resistance from the junction of the die to the ambient temperature of the package. where: (CGATE − P + CGATE − N) ≈ 600 pF. fSW = 1.2 MHz, the switching frequency. Rev. C | Page 22 of 36 ADP2105/ADP2106/ADP2107 For example, in an application where the ADP2107(1.8 V) is used with an input voltage of 3.6 V, a load current of 2 A, and a maximum ambient temperature of 85°C, at a load current of 2 A, the most significant contributor of power dissipation in the dc-todc converter package is the conduction loss of the power switches. Using the graph of switch on resistance vs. temperature (see Figure 30), as well as the equation of power loss given in the Power Switch Conduction Losses section, the power dissipation in the package can be calculated by the following: PSW − COND = [RDS(ON) − P × D + RDS(ON) − N × (1 − D)] × IOUT2 = The θJA for the LFCSP_VQ package is 40°C/W, as shown in Table 3. Therefore, the rise in temperature of the package due to power dissipation is TR = θJA × PD = 40°C/W × 0.40 W = 16°C The junction temperature of the converter is TJ = TA + TR = 85°C + 16°C = 101°C Because the junction temperature of the converter is below the maximum junction temperature of 125°C, this application operates reliably from a thermal point of view. [109 mΩ × 0.5 + 90 mΩ × 0.5] × (2 A)2 ≈ 400 mW www.BDTIC.com/ADI Rev. C | Page 23 of 36 ADP2105/ADP2106/ADP2107 DESIGN EXAMPLE Consider an application with the following specifications: 4. Input Voltage = 3.6 V to 4.2 V. Output Voltage = 2 V. Typical Output Current = 600 mA. Maximum Output Current = 1.2 A. Soft Start Time = 2 ms. Overshoot ≤ 100 mV under all load transient conditions. 1. 2. 3. 5. Choose the dc-to-dc converter that satisfies the maximum output current requirement. Because the maximum output current for this application is 1.2 A, the ADP2106 with a maximum output current of 1.5 A is ideal for this application. See whether the output voltage desired is available as a fixed output voltage option. Because 2 V is not one of the fixed output voltage options available, choose the adjustable version of ADP2106. The first step in external component selection for an adjustable version converter is to calculate the resistance of the resistive voltage divider that sets the output voltage. R BOT = VFB I STRING = 0.8 V 20 μA Output Capacitor × Output Voltage = 60 μC ⇒ Output Capacitor = 6. = 40 kΩ ⎡ 2 V − 0.8 V ⎤ ⎡V − V FB ⎤ RTOP = R BOT ⎢ OUT ⎥ = 60 kΩ ⎥ = 40 kΩ × ⎢ VFB ⎣ ⎦ ⎣⎢ 0.8 V ⎦⎥ Calculate the minimum inductor value as follows: The closest standard inductor value is 2.2 μH. The maximum rms current of the inductor is to be greater than 1.2 A, and the saturation current of the inductor is to be greater than 2 A. One inductor that meets these criteria is the LPS40122.2 μH from Coilcraft. Choose the output capacitor based on the transient response requirements. The worst-case load transient is 1.2 A, for which the overshoot must be less than 100 mV, which is 5% of the output voltage. For a 1 A load transient, the overshoot must be less than 4% of the output voltage, then from Figure 39: 7. 60 μC 2. 0 V ≈ 30 μF Taking into account the loss of capacitance due to dc bias, as shown in Figure 40, two 22 μF X5R MLCC capacitors from Murata (GRM21BR60J226M) are sufficient for this application. Because the ADP2106 is being used in this application, the input capacitors are 10 μF and 4.7 μF X5R Murata capacitors (GRM21BR61A106K and GRM21BR61A475K). The input filter consists of a small 0.1 μF ceramic capacitor placed between IN and AGND and a 10 Ω resistor placed between IN and PWIN1. Choose a soft start capacitor of 2 nF to achieve a soft start time of 2 ms. Calculate the compensation resistor and capacitor as follows: www.BDTIC.com/ADI For the ADP2106: L > (0.83 μH/V) × VOUT ⇒ L > 0.83 μH/V × 2 V ⇒ L > 1.66 μH Next, calculate the ideal inductor value that sets the inductor peak-to-peak current ripple (ΔIL) to 1/3 of the maximum load current at the maximum input voltage as follows: L IDEAL = 8. 9. 2.5 × VOUT × (V IN − VOUT ) μH = V IN × I LOAD ( MAX ) ⎛ (2 π)FCROSS RCOMP = 0.8 ⎜⎜ ⎝ GmGCS Rev. C | Page 24 of 36 ⎞ ⎟= ⎟ ⎠ ⎛ ⎞⎛ 30 μF × 2 V ⎞ (2 π) × 80 kHz ⎟⎜ ⎟ = 215 kΩ 0.8 ⎜ ⎜ 50 μA / V × 2.8125 A / V ⎟⎜ 0.8 V ⎟ ⎝ ⎠⎝ ⎠ C COMP = 2.5 × 2 × (4.2 − 2) μH = 2.18 μH 4 . 2 × 1 .2 ⎞⎛ COUT VOUT ⎟⎜ ⎟⎜ V REF ⎠⎝ 2 2 = = 39 pF πFCROSS RCOMP π × 80 kHz × 215 kΩ ADP2105/ADP2106/ADP2107 EXTERNAL COMPONENT RECOMMENDATIONS For popular output voltage options at 80 kHz crossover frequency with 10% overshoot for a 1 A load transient (refer to Figure 37 and Figure 38). Table 11. Recommended External Components Part ADP2105(ADJ) ADP2105(ADJ) ADP2105(ADJ) ADP2105(ADJ) ADP2105(ADJ) ADP2105(ADJ) ADP2106(ADJ) ADP2106(ADJ) ADP2106(ADJ) ADP2106(ADJ) ADP2106(ADJ) ADP2106(ADJ) ADP2107(ADJ) ADP2107(ADJ) ADP2107(ADJ) ADP2107(ADJ) ADP2107(ADJ) ADP2107(ADJ) ADP2105-1.2 ADP2105-1.5 ADP2105-1.8 ADP2105-3.3 ADP2106-1.2 ADP2106-1.5 ADP2106-1.8 ADP2106-3.3 ADP2107-1.2 ADP2107-1.5 ADP2107-1.8 ADP2107-3.3 VOUT (V) 0.9 1.2 1.5 1.8 2.5 3.3 0.9 1.2 1.5 1.8 2.5 3.3 0.9 1.2 1.5 1.8 2.5 3.3 1.2 1.5 1.8 3.3 1.2 1.5 1.8 3.3 1.2 1.5 1.8 3.3 CIN1 1 (μF) 4.7 4.7 4.7 4.7 4.7 4.7 4.7 4.7 4.7 4.7 4.7 4.7 10 10 10 10 10 10 4.7 4.7 4.7 4.7 4.7 4.7 4.7 4.7 10 10 10 10 CIN21 (μF) 4.7 4.7 4.7 4.7 4.7 4.7 10 10 10 10 10 10 10 10 10 10 10 10 4.7 4.7 4.7 4.7 10 10 10 10 10 10 10 10 COUT 2 (μF) 22 + 10 22 + 4.7 10 + 10 10 + 10 10 + 4.7 10 + 4.7 22 + 10 22 + 4.7 10 + 10 10 + 10 10 + 4.7 10 + 4.7 22 + 10 22 + 4.7 10 + 10 10 + 10 10 + 4.7 10 + 4.7 22 + 4.7 10 + 10 10 + 10 10 + 4.7 22 + 4.7 10 + 10 10 + 10 10 + 4.7 22 + 4.7 10 + 10 10 + 10 10 + 4.7 L (μH) 2.0 2.5 3.0 3.3 3.6 4.1 1.5 1.8 2.0 2.2 2.5 3.0 1.2 1.5 1.5 1.8 1.8 2.5 2.5 3.0 3.3 4.1 1.8 2.0 2.2 3.0 1.5 1.5 1.8 2.5 RCOMP (kΩ) 135 135 135 135 135 135 90 90 90 90 90 90 70 70 70 70 70 70 135 135 135 135 90 90 90 90 70 70 70 70 CCOMP (pF) 82 82 82 82 82 82 100 100 100 100 100 100 120 120 120 120 120 120 82 82 82 82 100 100 100 100 120 120 120 120 www.BDTIC.com/ADI 1 RTOP 3 (kΩ) 5 20 35 50 85 125 5 20 35 50 85 125 5 20 35 50 85 125 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A RBOT3 (kΩ) 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 4.7 μF 0805 X5R 10 V Murata—GRM21BR61A475KA73L. 10 μF 0805 X5R 10 V Murata—GRM21BR61A106KE19L. 4.7 μF 0805 X5R 10 V Murata—GRM21BR61A475KA73L. 10 μF 0805 X5R 10 V Murata—GRM21BR61A106KE19L. 22 μF 0805 X5R 6.3 V Murata—GRM21BR60J226ME39L. 3 0.5% accuracy resistor. 2 Rev. C | Page 25 of 36 ADP2105/ADP2106/ADP2107 For popular output voltage options at 80 kHz crossover frequency with 5% overshoot for a 1 A load transient (refer to Figure 37 and Figure 38). Table 12. Recommended External Components Part ADP2105(ADJ) ADP2105(ADJ) ADP2105(ADJ) ADP2105(ADJ) ADP2105(ADJ) ADP2105(ADJ) ADP2106(ADJ) ADP2106(ADJ) ADP2106(ADJ) ADP2106(ADJ) ADP2106(ADJ) ADP2106(ADJ) ADP2107(ADJ) ADP2107(ADJ) ADP2107(ADJ) ADP2107(ADJ) ADP2107(ADJ) ADP2107(ADJ) ADP2105-1.2 ADP2105-1.5 ADP2105-1.8 ADP2105-3.3 ADP2106-1.2 ADP2106-1.5 ADP2106-1.8 ADP2106-3.3 ADP2107-1.2 ADP2107-1.5 ADP2107-1.8 ADP2107-3.3 VOUT (V) 0.9 1.2 1.5 1.8 2.5 3.3 0.9 1.2 1.5 1.8 2.5 3.3 0.9 1.2 1.5 1.8 2.5 3.3 1.2 1.5 1.8 3.3 1.2 1.5 1.8 3.3 1.2 1.5 1.8 3.3 CIN1 1 (μF) 4.7 4.7 4.7 4.7 4.7 4.7 4.7 4.7 4.7 4.7 4.7 4.7 10 10 10 10 10 10 4.7 4.7 4.7 4.7 4.7 4.7 4.7 4.7 10 10 10 10 CIN21 (μF) 4.7 4.7 4.7 4.7 4.7 4.7 10 10 10 10 10 10 10 10 10 10 10 10 4.7 4.7 4.7 4.7 10 10 10 10 10 10 10 10 COUT 2 (μF) 22 + 22 + 22 22 + 22 + 4.7 22 + 22 22 + 22 22 + 10 22 + 4.7 22 + 22 + 22 22 + 22 + 4.7 22 + 22 22 + 22 22 + 10 22 + 4.7 22 + 22 + 22 22 + 22 + 4.7 22 + 22 22 + 22 22 + 10 22 + 4.7 22 + 22 + 4.7 22 + 22 22 + 22 22 + 4.7 22 + 22 + 4.7 22 + 22 22 + 22 22 + 4.7 22 + 22 + 4.7 22 + 22 22 + 22 22 + 4.7 L (μH) 2.0 2.5 3.0 3.3 3.6 4.1 1.5 1.8 2.0 2.2 2.5 3.0 1.2 1.5 1.5 1.8 1.8 2.5 2.5 3.0 3.3 4.1 1.8 2.0 2.2 3.0 1.5 1.5 1.8 2.5 RCOMP (kΩ) 270 270 270 270 270 270 180 180 180 180 180 180 140 140 140 140 140 140 270 270 270 270 180 180 180 180 140 140 140 140 CCOMP (pF) 39 39 39 39 39 39 56 56 56 56 56 56 68 68 68 68 68 68 39 39 39 39 56 56 56 56 68 68 68 68 www.BDTIC.com/ADI 1 RTOP 3 (kΩ) 5 20 35 50 85 125 5 20 35 50 85 125 5 20 35 50 85 125 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A RBOT 3(kΩ) 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 4.7μF 0805 X5R 10V Murata—GRM21BR61A475KA73L. 10μF 0805 X5R 10V Murata—GRM21BR61A106KE19L. 4.7μF 0805 X5R 10V Murata—GRM21BR61A475KA73L. 10μF 0805 X5R 10V Murata—GRM21BR61A106KE19L. 22μF 0805 X5R 6.3V Murata—GRM21BR60J226ME39L. 3 0.5% accuracy resistor. 2 Rev. C | Page 26 of 36 ADP2105/ADP2106/ADP2107 CIRCUIT BOARD LAYOUT RECOMMENDATIONS Good circuit board layout is essential to obtaining the best performance from the ADP2105/ADP2106/ADP2107. Poor circuit layout degrades the output ripple, as well as the electromagnetic interference (EMI) and electromagnetic compatibility (EMC) performance. • Make the high current path from the PGND pin through L and COUT back to the PGND plane as short as possible. To accomplish this, ensure that the PGND pin is tied to the PGND plane as close as possible to the input and output capacitors. Figure 54 and Figure 55 show the ideal circuit board layout for the ADP2105/ADP2106/ADP2107 to achieve the highest performance. Refer to the following guidelines if adjustments to the suggested layout are needed: • The feedback resistor divider network is to be placed as close as possible to the FB pin to prevent noise pickup. The length of trace connecting the top of the feedback resistor divider to the output is to be as short as possible while keeping away from the high current traces and the LX (switch) node that can lead to noise pickup. An analog ground plane is to be placed on either side of the FB trace to reduce noise pickup. For the low fixed voltage options (1.2 V and 1.5 V), poor routing of the OUT_SENSE trace can lead to noise pickup, adversely affecting load regulation. This can be fixed by placing a 1 nF bypass capacitor close to the FB pin. • The placement and routing of the compensation components are critical for proper behavior of the ADP2105/ADP2106/ ADP2107. The compensation components are to be placed as close to the COMP pin as possible. It is advisable to use 0402-sized compensation components for closer placement, leading to smaller parasitics. Surround the compensation components with an analog ground plane to prevent noise pickup. The metal layer under the compensation components is to be the analog ground plane. • Use separate analog and power ground planes. Connect the ground reference of sensitive analog circuitry (such as compensation and output voltage divider components) to analog ground; connect the ground reference of power components (such as input and output capacitors) to power ground. In addition, connect both the ground planes to the exposed pad of the ADP2105/ADP2106/ADP2107. • For each PWIN pin, place an input capacitor as close to the PWIN pin as possible and connect the other end to the closest power ground plane. • Place the 0.1 μF, 10 Ω low-pass input filter between the IN pin and the PWIN1 pin, as close to the IN pin as possible. • Ensure that the high current loops are as short and as wide as possible. Make the high current path from CIN through L, COUT, and the PGND plane back to CIN as short as possible. To accomplish this, ensure that the input and output capacitors share a common PGND plane. www.BDTIC.com/ADI Rev. C | Page 27 of 36 ADP2105/ADP2106/ADP2107 EVALUATION BOARD EVALUATION BOARD SCHEMATIC FOR ADP2107 (1.8 V) C7 0.1µF VCC R3 10Ω C1 10µF1 OUT J1 U1 GND 16 15 FB GND IN 1 EN 2 GND INPUT VOLTAGE = 2.7V TO 5.5V VIN VCC 14 13 PWIN1 LX2 12 EN PGND 11 ADP2107-1.8 1 LX1 10 GND 3 L12 2µH PWIN2 9 GND 4 OUT 6 7 8 C4 22µF1 C3 22µF1 GND R5 NS R1 140kΩ C6 68pF R4 0Ω C2 10µF1 COMP SS AGND PADDLE NC 5 OUTPUT VOLTAGE = 1.8V, 2A VOUT 2 VCC 1 MURATA X5R 0805 10μF: GRM21BR61A106KE19L 22μF: GRM21BR60J226ME39L 2 2μH INDUCTOR D62LCB TOKO C5 1nF NC = NO CONNECT 06079-044 R2 100kΩ Figure 53. Evaluation Board Schematic of the ADP2107-1.8 (Bold Traces are High Current Paths) www.BDTIC.com/ADI RECOMMENDED PCB LAYOUT (EVALUATION BOARD LAYOUT) JUMPER TO ENABLE ENABLE GROUND VIN 100kΩ PULL-DOWN GROUND INPUT INPUT CAPACITOR POWER GROUND PLANE PLACE THE FEEDBACK RESISTORS AS CLOSE TO THE FB PIN AS POSSIBLE. RTOP RBOT CONNECT THE GROUND RETURN OF ALL POWER COMPONENTS SUCH AS INPUT AND OUTPUT CAPACITORS TO THE POWER GROUND PLANE. OUTPUT CAPACITOR CIN COUT LX OUTPUT PGND ADP2105/ADP2106/ADP2107 VOUT LX RCOMP CIN CCOMP PLACE THE COMPENSATION COMPONENTS AS CLOSE TO THE COMP PIN AS POSSIBLE. INDUCTOR (L) COUT OUTPUT CAPACITOR CSS ANALOG GROUND PLANE POWER GROUND INPUT CAPACITOR 06079-045 CONNECT THE GROUND RETURN OF ALL SENSITIVE ANALOG CIRCUITRY SUCH AS COMPENSATION AND OUTPUT VOLTAGE DIVIDER TO THE ANALOG GROUND PLANE. Figure 54. Recommended Layout of Top Layer of ADP2105/ADP2106/ADP2107 Rev. C | Page 28 of 36 ADP2105/ADP2106/ADP2107 ENABLE VIN GND GND ANALOG GROUND PLANE POWER GROUND PLANE INPUT VOLTAGE PLANE CONNECTING THE TWO PWIN PINS AS CLOSE AS POSSIBLE. VIN VOUT CONNECT THE PGND PIN TO THE POWER GROUND PLANE AS CLOSE TO THE ADP2105/ADP2106/ADP2107 AS POSSIBLE. FEEDBACK TRACE: THIS TRACE CONNECTS THE TOP OF THE RESISTIVE VOLTAGE DIVIDER ON THE FB PIN TO THE OUTPUT. PLACE THIS TRACE AS FAR AWAY FROM THE LX NODE AND HIGH CURRENT TRACES AS POSSIBLE TO PREVENT NOISE PICKUP. www.BDTIC.com/ADI Figure 55. Recommended Layout of Bottom Layer of ADP2105/ADP2106/ADP2107 Rev. C | Page 29 of 36 06079-046 CONNECT THE EXPOSED PAD OF THE ADP2105/ADP2106/ADP2107 TO A LARGE GROUND PLANE TO AID POWER DISSIPATION. ADP2105/ADP2106/ADP2107 APPLICATION CIRCUITS 0.1μF VIN 10Ω INPUT VOLTAGE = 5V 10μF1 VOUT OFF 16 15 FB GND IN 14 13 PWIN1 LX2 12 1 EN 2 GND 2.5μH2 PGND 11 ADP2107-3.3 3 GND LX1 10 4 GND PWIN2 9 COMP SS 5 6 10μF1 8 1nF 70kΩ OUTPUT VOLTAGE = 3.3V 4.7μF1 LOAD 0A TO 2A VIN AGND NC 7 VOUT 10μF1 1 MURATA X5R 0805 10μF: GRM21BR61A106KE19L 4.7μF: GRM21BR61A475KA73L 2 SUMIDA CDRH5D28: 2.5μH NOTES 1. NC = NO CONNECT. 2. EXTERNAL COMPONENTS WERE CHOSEN FOR A 10% OVERSHOOT FOR A 1A LOAD TRANSIENT. 120pF 06079-047 ON Figure 56. Application Circuit—VIN = 5 V, VOUT = 3.3 V, Load = 0 A to 2 A 0.1μF VIN 10Ω INPUT VOLTAGE = 3.6V 10μF1 VOUT ON 16 15 FB GND IN 14 13 PWIN1 www.BDTIC.com/ADI LX2 12 1 EN 1.5μH2 PGND 11 2 GND 22μF1 ADP2107-1.5 3 GND LX1 10 4 GND PWIN2 9 COMP SS 5 6 140kΩ 68pF AGND NC 1nF 7 8 VOUT OUTPUT VOLTAGE = 1.5V 22μF1 LOAD 0A TO 2A VIN 10μF1 1 MURATA X5R 0805 10μF: GRM21BR61A106KE19L 22μF: GRM21BR60J226ME39L 2 TOKO D62LCB OR COILCRAFT LPS4012 NOTES 1. NC = NO CONNECT. 2. EXTERNAL COMPONENTS WERE CHOSEN FOR A 5% OVERSHOOT FOR A 1A LOAD TRANSIENT. Figure 57. Application Circuit—VIN = 3.6 V, VOUT = 1.5 V, Load = 0 A to 2 A Rev. C | Page 30 of 36 06079-048 OFF ADP2105/ADP2106/ADP2107 0.1μF VIN 10Ω INPUT VOLTAGE = 2.7V TO 4.2V 4.7μF1 VOUT 16 15 FB GND IN 14 13 PWIN1 LX2 12 1 EN OFF 2.7μH2 PGND 11 2 GND ADP2105-1.8 3 GND LX1 10 4 GND PWIN2 9 COMP SS 5 6 4.7μF1 LOAD 0A TO 1A 1 MURATA X5R 0805 4.7μF: GRM21BR61A475KA73L 22μF: GRM21BR60J226ME39L 8 2 TOKO 1098AS-DE2812: 2.7μH 1nF 270kΩ OUTPUT VOLTAGE = 1.8V 22μF1 VIN AGND NC 7 VOUT 22μF1 NOTES 1. NC = NO CONNECT. 2. EXTERNAL COMPONENTS WERE CHOSEN FOR A 5% OVERSHOOT FOR A 1A LOAD TRANSIENT. 39pF 06079-049 ON Figure 58. Application Circuit—VIN = Li-Ion Battery, VOUT = 1.8 V, Load = 0 A to 1 A 0.1μF VIN 10Ω INPUT VOLTAGE = 2.7V TO 4.2V 4.7μF1 VOUT ON OFF 1 16 15 FB GND IN 14 13 PWIN1 LX2 12 EN 2.4μH2 VOUT OUTPUT VOLTAGE = 1.2V www.BDTIC.com/ADI PGND 11 GND 22μF1 ADP2105-1.2 3 GND LX1 10 4 GND PWIN2 9 COMP SS 5 6 135kΩ 82pF AGND NC 1nF 7 8 4.7μF1 LOAD 0A TO 1A VIN 4.7μF1 1 MURATA X5R 0805 4.7μF: GRM21BR61A475KA73L 22μF: GRM21BR60J226ME39L 2 TOKO 1069AS-DB3018HCT OR TOKO 1070AS-DB3020HCT NOTES 1. NC = NO CONNECT. 2. EXTERNAL COMPONENTS WERE CHOSEN FOR A 10% OVERSHOOT FOR A 1A LOAD TRANSIENT. Figure 59. Application Circuit—VIN = Li-Ion Battery, VOUT = 1.2 V, Load = 0 A to 1 A Rev. C | Page 31 of 36 06079-050 2 ADP2105/ADP2106/ADP2107 0.1μF VIN 10Ω INPUT VOLTAGE = 5V 10μF1 FB OFF 16 15 14 13 FB GND IN PWIN1 LX2 12 1 EN 2 GND 2.5μH2 ADP2106-ADJ 85kΩ 3 GND LX1 10 4 GND PWIN2 9 COMP SS 5 6 180kΩ 56pF OUTPUT VOLTAGE = 2.5V PGND 11 AGND NC 1nF 7 10μF1 22μF1 LOAD 0A TO 1.5A FB VIN 40kΩ 4.7μF1 8 1 MURATA X5R 0805 4.7μF: GRM21BR61A475KA73L 10μF: GRM21BR61A106KE19L 22μF: GRM21BR60J226ME39L 2 COILTRONICS SD14: 2.5μH NOTES 1. NC = NO CONNECT. 2. EXTERNAL COMPONENTS WERE CHOSEN FOR A 5% OVERSHOOT FOR A 1A LOAD TRANSIENT. 06079-051 ON Figure 60. Application Circuit—VIN = 5 V, VOUT = 2.5 V, Load = 0 A to 1.5 A www.BDTIC.com/ADI Rev. C | Page 32 of 36 ADP2105/ADP2106/ADP2107 OUTLINE DIMENSIONS 4.00 BSC SQ 0.60 MAX 0.60 MAX 13 12° MAX 1.00 0.85 0.80 0.65 BSC TOP VIEW 12 0.50 0.40 0.30 0.80 MAX 0.65 TYP (BOTTOM VIEW) 9 8 5 4 0.25 MIN 1.95 BSC 0.05 MAX 0.02 NOM SEATING PLANE 2.50 2.35 SQ 2.20 EXPOSED PAD 3.75 BSC SQ 0.35 0.30 0.25 PIN 1 INDICATOR 1 0.20 REF COPLANARITY 0.08 THE EXPOSED PAD ON THE BOTTOM OF THE LFCSP PACKAGE MUST BE SOLDERED TO PCB GROUND FOR PROPER HEAT DISSIPATION AND ALSO FOR NOISE AND MECHANICAL STRENGTH BENEFITS. COMPLIANT TO JEDEC STANDARDS MO-220-VGGC 010606-0 PIN 1 INDICATOR 16 Figure 61. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm × 4 mm Body, Very Thin Quad (CP-16-10) Dimensions shown in millimeters ORDERING GUIDE Model ADP2105ACPZ-1.2-R7 1 ADP2105ACPZ-1.5-R71 ADP2105ACPZ-1.8-R71 ADP2105ACPZ-3.3-R71 ADP2105ACPZ-R71 ADP2106ACPZ-1.2-R71 ADP2106ACPZ-1.5-R71 ADP2106ACPZ-1.8-R71 ADP2106ACPZ-3.3-R71 ADP2106ACPZ-R71 ADP2107ACPZ-1.2-R71 ADP2107ACPZ-1.5-R71 ADP2107ACPZ-1.8-R71 ADP2107ACPZ-3.3-R71 ADP2107ACPZ-R71 ADP2105-1.8-EVALZ1 ADP2105-EVALZ1 ADP2106-1.8-EVALZ1 ADP2106-EVALZ1 ADP2107-1.8-EVALZ1 ADP2107-EVALZ1 1 Output Current 1A 1A 1A 1A 1A 1.5 A 1.5 A 1.5 A 1.5 A 1.5 A 2A 2A 2A 2A 2A Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C Output Voltage 1.2 V 1.5 V 1.8 V 3.3 V ADJ 1.2 V 1.5 V 1.8 V 3.3 V ADJ 1.2 V 1.5 V 1.8 V 3.3 V ADJ 1.8 V Adjustable, but set to 2.5 V 1.8 V Adjustable, but set to 2.5 V 1.8 V Adjustable, but set to 2.5 V Package Description 16-Lead LFCSP_VQ 16-Lead LFCSP_VQ 16-Lead LFCSP_VQ 16-Lead LFCSP_VQ 16-Lead LFCSP_VQ 16-Lead LFCSP_VQ 16-Lead LFCSP_VQ 16-Lead LFCSP_VQ 16-Lead LFCSP_VQ 16-Lead LFCSP_VQ 16-Lead LFCSP_VQ 16-Lead LFCSP_VQ 16-Lead LFCSP_VQ 16-Lead LFCSP_VQ 16-Lead LFCSP_VQ Evaluation Board Evaluation Board Evaluation Board Evaluation Board Evaluation Board Evaluation Board www.BDTIC.com/ADI Z = RoHS Compliant Part. Rev. C | Page 33 of 36 Package Option CP-16-10 CP-16-10 CP-16-10 CP-16-10 CP-16-10 CP-16-10 CP-16-10 CP-16-10 CP-16-10 CP-16-10 CP-16-10 CP-16-10 CP-16-10 CP-16-10 CP-16-10 ADP2105/ADP2106/ADP2107 NOTES www.BDTIC.com/ADI Rev. C | Page 34 of 36 ADP2105/ADP2106/ADP2107 NOTES www.BDTIC.com/ADI Rev. C | Page 35 of 36 ADP2105/ADP2106/ADP2107 NOTES www.BDTIC.com/ADI ©2006–2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06079-0-9/08(C) Rev. C | Page 36 of 36