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TPS54620
TPS54620
ZHCS004–2009
5月
www.ti.com.cn
www.ti.com ........................................................................................................................................................................................................ SLVS949
– MAY 年
2009
输出，同步降压转换器
17V Input,17V
6A输入，
Output,6A
Synchronous
Step Down Switcher
TM
带集成场效应管
，采用
With Integrated
FET
in 3.5mm
x 3.5mm
Package(SWIFT™)
(FET)
3.5mm
x 3.5mm
SWIFT 系列封装
特点
FEATURES
• • 针对过压及欠压的电源良好性输出
Good Output)
Power Good Output Monitor(Power
for Undervoltage
监控
& Overvoltage
1
Integrated
/ 19mŸ
MOSFETs
26mΩ26mŸ
/ 19mΩ
MOSFET
•• 集成的
Split Power1.6V
Rail:
1.6VPVIN
to 17V
on PVIN
至17V
引脚输入
•• 分离电源轨：
2
• • 可调输入欠压锁定
Adjustable Input Undervoltage Lockout
软件工具
• • 支持
SwitcherPro™
Supported
by SwitcherPro™
Software Tool
200kHz to200kHz
1.6MHz
Switching Frequency
至1.6MHz
•• 开关频率从
Synchronizes to External Clock
•• 同步于外部时钟
0.8V ±1%0.8V
Voltage
Reference Over Temperature
，温度影响下变化范围为
±1%
•• 参考电压为
的关断静态电流
Low2uA
2uA
Shutdown Quiscent Current
•• 仅为
Monotonic Start-Up into Prebiased Outputs
•• 单调启动至预偏执输出
℃至to
℃工作时结温范围
150150°C
•• –40
–40°C
Operating Junction
•
Temperature
Range
可调慢启动
/电源排序
•
Adjustable Slow Start/Power Sequencing
，以获取
• • 敬请访问
www.ti.com.cn/swift
For SWIFT™
Documentation
and SWIFT™文档及
软件工具
SwitcherPro™,
visit http://www.ti.com/swift
SwitcherPro™
应用
APPLICATIONS
• • 高密度分布式电源系统
High Density Distributed Power Systems
• • 高性能负载点稳压设计
High Peformance Point of Load Regulation
Broadband, Networking and Optical
• • 宽带，网络及光纤通信基础设施
Communications Infrastructure
描述
DESCRIPTION
3.5mm x 3.5mm
QFN3.5mm TPS54620
6A
The TPS54620 in thermally
enhanced
x 3.5mm QFN package is a 17V
full featured
17V, 6A synchronous step
率、集成了高边
开关的小型化设计进行了优化。通过电流模式控制减少元件数量，以及通过选择更高的开关频率
/低边
MOSFET
down converter
which
is optimized
for small designs through high efficiency and integrating the high-side and
low-side MOSFETs. Further space savings are achieved through current mode control, which reduces
来减少电感器的占用面积，从而更进一步的节省了空间。
component count, and by selecting a high switching frequency, reducing the inductor's footprint.
采用耐热增强型
封装的
，是一个功能齐全的
、
的同步降压转换器，专门针对高效
引脚，其操作既支持独立电源供电模式又支持跟踪模式。通过正确的配置使能
SS/TR
The 输出的电压启动斜线上升受控于
output voltage startup ramp is
controlled
by the SS/TR pin which allows operation as either a stand alone
power
supply
or
in
tracking
situations.
Power
sequencing
is also possible by correctly configuring the enable and
引脚，能够实现电源排序。
(Enable)引脚及开漏电源良好(open drain power good)
the open drain power good pins.
高边场效应管的逐周期电流限制，能在过载情况下保护器件不受损害；而用以防止电流失控的低边源电流
current)
Cycle
by cycle current limiting on the high-side fet protects the device in overload situations and is(source
enhanced
by
a
low-side
sourcing
current
limit
which
prevents
current
runaway.
There
is
also
a
low-side
sinking
current
limit
限制，又增强了高边场效应管的逐周期电流限制。还有一个低边吸收电流(sinking current)限制，能够关闭低边MOSFET，以防
which turns off the low-side MOSFET to prevent excessive reverse current. Thermal shutdown disables the part
止过多的反向电流流入。当核心温度(die temperature)升至过高时，热关断电路(thermal shutdown)将关闭该部分。
when die temperature rises too high.
WHITE SPACE
SIMPLIFIED SCHEMATIC
100
Cin
8�V
95
Cboot
90
VOUT
Lo
EN
PH
Co
PWRGD
R1
VSENSE
SS/TR
RT/CLK
COMP
Css
Rrt C2
R3
纵坐标：效率
– %
Efficiency�-�%
PVIN
VIN
TPS54620
BOOT
VIN
85
17�V
12�V
80
75
70
65
R2
GND
60
PowerPAD
55
VOUT =�3.3�V
Fsw�=�480�kHz
50
C1
0
1
2
3
4
Load�Current�A
横坐标：负载电流
5
6
–A
1
请注意，关于德州仪器半导体产品的可用性、标准质保期和关键应用的重要通知以及免责声明，
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
将出现在本数据手册的末尾部分。
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SWIFT,
PowerPAD
are trademarks of Texas Instruments.
SWIFT, PowerPAD是德州仪器的注册商标。
2
www.BDTIC.com/TI
PRODUCTION
DATA information is current as of publication date.
生产数据信息与出版日期一样，都是近期的。产
Products conform to specifications per the terms of the Texas
品符合德州仪器标准质保服务每一条款的规定。
Instruments
standard warranty. Production processing does not
necessarily
include testing of all parameters.
产品的生产过程不可能包括测试所有的参数。
Copyright © 2009, Texas
Instruments Incorporated
版权所有：德州仪器
© 2009
TPS54620
TPS54620
年5月 ........................................................................................................................................................................................................
ZHCS004–2009
www.ti.com.cn
SLVS949
www.ti.com
SLVS949 –
– MAY
MAY 2009
2009 ........................................................................................................................................................................................................
www.ti.com
These
devices
built-in
ESD
这些器件仅具有有限的内置
保护。当存放或对其进行操作时，引线应短接在一起或将器件放置在导电泡沫中，
ESD
These
devices have
have limited
limited
built-in
ESD protection.
protection. The
The leads
leads should
should be
be shorted
shorted together
together or
or the
the device
device placed
placed in
in conductive
conductive foam
foam
during
storage
or
handling
to
prevent
electrostatic
damage
to
the
MOS
gates.
during
storage
or
handling
to
prevent
electrostatic
damage
to
the
MOS
gates.
以防止静电对MOS管门电路的破坏。
(1)
(1)
ORDERING INFORMATION
INFORMATION
(1)
ORDERING
订购须知
(1)
(1)
(1)
(2)
(2)
(2)
(2)
T
PACKAGE
PART
TJJ
PACKAGE
PART NUMBER
NUMBER (2)
封装类型
元件编号(2)
TJ
–40°C to
to 150°C
150°C
14 Pin
Pin QFN
QFN
TPS54620RGY
–40°C
14
TPS54620RGY
–40℃至150℃
14引脚QFN封装
TPS54620RGY
For
For the
the most
most current
current package
package and
and ordering
ordering information,
information, see
see the
the Package
Package Option
Option Addendum
Addendum at
at the
the end
end of
of this
this document,
document, or
or see
see the
the TI
TI
如想获得最新的封装及订购信息，请参见本文档末尾部分的封装选择增编，或访问
web
TI网站：www.ti.com.cn。
web site
site at
at www.ti.com.
www.ti.com.
The
RGY
package
is
also
available
taped
and
reeled.
Add
an
R
suffix
to
the
device
type
(i.e.,
TPS54620RGYR).
See
applications
我们也提供可捆扎与卷绕
的RGY
）。详情请参见数
The RGY package is also
available
taped
and封装，以器件类型后面所添加的字母
reeled. Add an R suffix to the device
type (i.e., TPS54620RGYR).
See applications
(taped
and reeled)
R后缀作为标识（例如，
TPS54620RGYR
section of
of data
data sheet
sheet for
for layout
layout information
information
section
据手册应用部分的布置信息。
(1)
(1)
ABSOLUTE
绝对最大额定值
ABSOLUTE MAXIMUM
MAXIMUM RATINGS
RATINGS (1)
over
在工作温度范围（除非另有说明）
over operating
operating temperature
temperature range
range (unless
(unless otherwise
otherwise noted)
noted)
VALUE
VALUE
–0.3
–0.3 to
to 20
20
–0.3
–0.3 to
to 20
20
VIN
VIN
PVIN
PVIN
EN
EN
BOOT
BOOT
Input
输入电压
Input Voltage
Voltage
–0.3
–0.3 to
to 3
3
–0.3 to
to 27
27
–0.3
–0.3
–0.3 to
to 3
3
VSENSE
VSENSE
COMP
COMP
Output
Output Voltage
Voltage
输出电压
PWRGD
PWRGD
SS/TR
SS/TR
–0.3
–0.3 to
to 3
3
–0.3
–0.3 to
to 6
6
–0.3
to
–0.3 to 3
3
RT/CLK
RT/CLK
BOOT-PH
BOOT-PH
–0.3
–0.3 to
to 6
6
0 to
to 7
7
0
PH
PH
PH
PH 10ns
10ns Transient
Transient
–1
–1
–3
–3
Vdiff(GND
to PowerPAD)
PowerPAD)
的GND)
Vdiff(GND
to
Vdiff
(PowerPAD
Current
Current
Current
Current
PH
PH
PVIN
PVIN
Sink
Sink Current
Current
吸收电流
20
20
20
20
–0.2 to
to 0.2
0.2
–0.2
±100
±100
RT/CLK
RT/CLK
PH
PH
Source
源电流
Source Current
Current
to
to
to
to
Limit
Limit
Limit
Limit
Current Limit
Limit
Current
±200
±200
COMP
COMP
PWRGD
PWRGD
Electrostatic
Discharge
(HBM)
QSS
009-105- (JESD22-A114A)
(JESD22-A114A)
静电放电（
模式） QSS
Electrostatic
Discharge
(HBM)
QSS(JESD22
009-105
HBM
009-105
A114A)
Electrostatic
Discharge
(CDM)
QSS
009-147
(JESD22-C101B.01)
静电放电（
模式）
Electrostatic
DischargeQSS
(CDM)
QSS(JESD22-C101B.01)
009-147 (JESD22-C101B.01)
CDM
009-147
Operating
Operating Junction
Junction Temperature
Temperature
工作时结温范围
Storage Temperature
Temperature
贮藏温度范围
Storage
UNIT
UNIT
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
µA
A
A
A
A
A
A
–0.1
–0.1 to
to 5
5
2
2
µA
µA
mA
mA
kV
kV
500
500
–40
–40 to
to 150
150
–65 to
to 150
150
–65
V
V
°C
°C
°C
°C
(1) 注意：一旦超过所列出的绝对最大额定值，将有可能对器件造成永久性损坏。所列出的数据仅仅是需要强调额定值，而在这些条件下或者超出了必
Stresses beyond
beyond those
those listed
listed under
under absolute
absolute maximum
maximum ratings
ratings may
may cause
cause permanent
permanent damage
damage to
to the
the device.
device. These
These are
are stress
stress ratings
ratings
(1)
Stresses
(1)
only,
only, and
and functional
functional operation
operation of
of the
the device
device at
at these
these or
or any
any other
other conditions
conditions beyond
beyond those
those indicated
indicated under
under recommended
recommended operating
operating
要的推荐运行条件的任何其它条件下，器件的功能性运行情况则没有明确说明。如果长期工作在绝对最大额定值的条件下，可能会对器件的可靠性
conditions
conditions is
is not
not implied.
implied. Exposure
Exposure to
to absolute-maximum-rated
absolute-maximum-rated conditions
conditions for
for extended
extended periods
periods may
may affect
affect device
device reliability.
reliability.
产生影响。
2
2
2
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Submit
Submit Documentation
Documentation Feedback
Feedback
Copyright
Texas
© 2009
Copyright ©
© 2009,
2009, 版权所有：德州仪器
Texas Instruments
Instruments Incorporated
Incorporated
产品文件夹链接：
Product
Folder
:TPS54620
TPS54620
Product
Folder Link(s)
Link(s)
:TPS54620
TPS54620
TPS54620
ZHCS004–2009年5月
www.ti.com.cn
www.ti.com ........................................................................................................................................................................................................ SLVS949 – MAY 2009
(3)
(1) (1)
(2)(2)(3)
封装功耗值
PACKAGE
(PACKAGEDISSIPATION
DISSIPATIONRATINGS
RATINGS)
THERMAL
IMPEDANCE
热阻抗
JUNCTION TO AMBIENT
结到环境
封装类型PACKAGE
RGY
RGY
ψJT 热特性
THERMAL CHARACTERISTIC
JUNCTION TO TOP
结到顶层
32℃/W 32°C/W
5°C/W
5℃ / W
(1) Maximum power dissipation may be limited by overcurrent protection
(1) 最大功耗值会受到过流保护的限制
(2) Power rating at a specific ambient temperature TA should be determined with a junction temperature of 150°C. This is the point where
的热处理应努力将结温保持在
150℃的结温度所决定。正是从这一点开始，畸变将大幅增加。对于
150℃或at or below
(2) 在特定的环境温度
TA下，额定功率由
distortion
starts to substantially
increase. Thermal management of the PCB should PCB
strive
to keep the junction temperature
以下，以获得最佳性能和长期的可靠性。如需更多信息，敬请参见本数据手册应用部分中的功耗估计。
150°C for best performance and long-term reliability. See power dissipation estimate in application section of this data sheet for more
(3) 测试板条件： information.
(3) 2.5
Test
board
conditions:
英寸，
a. 2.5英寸×
4层，厚度：
0.062英寸
a. 2.5 inches × 2.5 inches, 4 layers, thickness: 0.062 inch
板
b. 2盎司铜迹线，位于上层
PCB
b. 2 oz. copper traces located on the top of the PCB
c. 2盎司铜面参考地，在内部的
2层及底层
c. 2 oz. copper ground
planes on the 2 internal layers and bottom layer
d. 4 thermal vias located under the device package
d. 4热通道，位于器件封装的下面
电气特性
ELECTRICAL CHARACTERISTICS
TJ = –40°C to 150°C, VIN = 4.5V to 17V, PVIN = 1.6V to 17V (unless otherwise noted)
TJ = –40℃至150℃，VIN = DESCRIPTION
4.5V至17V，PVIN = 1.6V至17V（除非另有说明）
CONDITIONS
SUPPLY描述
VOLTAGE (VIN AND PVIN PINS)
条件
供电电压（VIN
及PVIN
引脚） input voltage
PVIN
operating
PVIN输入工作电压
VIN operating input voltage
VIN输入工作电压
VIN internal UVLO threshold
门限internal UVLO hysterisis
VIN内部UVLOVIN
磁滞shutdown supply Current
VIN内部UVLOVIN
MIN
MIN
1.6
VIN rising
4.0
上升
Falling
使能门限
Input current
下落
EN = 1.1 V
输入电流
Hysteresis current
EN = 1.1 V
EN = 1.3 V
磁滞电流
VOLTAGE REFERENCE
EN = 1.3 V
V
V
17
V
17 4.0
V
4.5
4.5 150
V
800
1.21 1.10
1.261.17
1.17
1.15
1.15
3.4
0 A ” Iout ” 6 A
MOSFET
5
µA
µA 800
µA
1.21
1.10
1.26
V
V
µA
µA
µA
µA
0.792
0.792
V
mV
µA
600
3.4
0 A ≤ Iout ≤ 6 A
High-side switch resistance
高边开关电阻High-side switch resistance (1)
高边开关电阻Low-side
(1)
Switch Resistance (1)
17
17
5 600
Rising
Enable threshold
Voltage reference
UNIT
2 mV
2
UNIT
MAX
150
EN = 0 V
使能门限
MOSFET
4.5
4.5
VIN上升
使能及UVLO（
EN引脚）
Enable
threshold
参考电压
MAX
1.6
VIN过热保护电流
= 0V
VIN operating – non switching supplyEN
current
VSENSE = 810 mV
VIN运行—非开关电源电流
VSENSE = 810 mV
ENABLE AND UVLO (EN PIN)
参考电压
TYP
TYP
0.800
0.800
0.808
BOOT-PH = 3 V
0.808
V
V
60
mŸ
BOOT-PH = 3BOOT-PH
V
=6V
32
60 26 mΩ 40
32
mŸ
BOOT-PH = 6VIN
V = 12 V
26
40 19 mΩ 30
mŸ
19
30
低边开关电阻ERROR
(1)
VIN = 12 V
AMPLIFIER
误差信号放大器
Error amplifier Transconductance (gm)
–2 µA < ICOMP < 2 µA, V(COMP) = 1 V
误差信号放大器跨导
µA
(gm)
–2
< ICOMP
< 2 µA,=V(COMP)
Error amplifier
dc gain
VSENSE
0.8 V = 1 V
误差信号放大器直流增益
VSENSE = 0.8V(COMP)
V
Error amplifier source/sink
= 1 V, 100 mV input overdrive1000
误差信号放大器拉电流
/灌电流threshold
Start switching
V(COMP) = 1 V, 100 mV输入过载
13001000
3100 µMhos
V/V
3100
±110 V / V
µA
±110
0.25
µA
V
V
A/V
16
16
High-side switch current limit threshold
高边开关电流限制门限
Low-side switch sourcing current limit
低边开关拉电流限制
Low-side switch sinking current limit
A /V
8
电流限制
8
11
7
10
2.3
低边开关灌电流限制
(1) Measured at pins
(1) 在管脚处测量得到
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版权所有：德州仪器
Copyright©©2009
2009, Texas Instruments Incorporated
µMhos
1300
0.25
启动开关门限COMP to Iswitch gm
跨导
COMP至Iswitch
CURRENT
LIMIT
mΩ
7
11
A
10
A
A
2.3
A
A
A
3
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产品文件夹链接：TPS54620
Product Folder Link(s) :TPS54620
3
TPS54620
ZHCS004–2009年5月
www.ti.com.cn
电气特性（续）
TJ = –40℃至150℃，VIN = 4.5V至17V，PVIN = 1.6V至17V（除非另有说明）
描述
条件
MIN
TYP
MAX
UNIT
160
175
℃
10
℃
热关断
热关断
热关断磁滞
时基电阻及外部时钟（RT/CLK引脚）
最小开关频率
Rrt = 240 kΩ (1%)
180
200
220
kHz
开关频率
Rrt = 100 kΩ (1%)
400
480
560
kHz
最大开关频率
Rrt = 29 kΩ (1%)
1440
1600
1760
kHz
20
最小脉冲宽度
RT/CLK高电平门限
ns
2
RT/CLK低电平门限
0.8
RT/CLK下降沿至PH上升沿的延时
V
当RT电阻串联连接、频率为500kHz时测量得到
开关频率范围（RT模式设定点及PLL模式）
V
66
200
ns
1600
kHz
135
ns
PH（PH引脚）
最小开通时间
温度为25℃、IPH = 2A、VIN从90%至90%时测量得到
94
最小关闭时间
BOOT-PH ≤ 3 V
0
ns
BOOT（BOOT引脚）
BOOT-PH UVLO
2.1
3
V
60
mV
慢启动及跟踪（SS/TR引脚）
SS充电电流
µA
2.3
SS/TR与VSENSE的匹配
V(SS/TR) = 0.4 V
29
电源良好性（PWRGD引脚）
VSENSE下降沿（出错）
91
% Vref
VSENSE上升沿（良好）
94
% Vref
VSENSE上升沿（出错）
109
% Vref
VSENSE下降沿（良好）
106
输出高漏泄
VSENSE = Vref, V(PWRGD) = 5.5 V
30
输出低漏泄
I(PWRGD) = 2 mA
有效输出时VIN的最小值
100 µA时V(PWRGD) < 0.5V
VSENSE门限
0.6
对于PWRGD的最小SS/TR电压值
4
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% Vref
100
nA
0.3
V
1
V
1.4
V
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DEVICE器件信息
INFORMATION
引脚分配
PIN ASSIGNMENTS
顶视图 )
RGY
(Top�View
RGY
RT /CLK
1
PWRGD
14
GND 2
13 BOOT
GND 3
12 PH
PVIN 4
PowerPAD
(15)
11 PH
10 EN
PVIN 5
VIN 6
9 SS /TR
7
VSENSE
8
COMP
PIN FUNCTIONS
PIN
NAME
RT/CLK
GND
DESCRIPTION
引脚功能
No.
名称
1
引脚
2, 3
PVIN
RT/CLK
VIN
GND
VSENSE
PVIN
COMP
VIN
VSENSE
SS/TR
COMP
4, 5
SS/TR
EN
10
PH
EN
BOOT
PH
11, 12
6
7
8
9
13
BOOT
PWRGD
PWRGD
14
PowerPAD
PowerPAD
15
Automatically selects between RT mode and CLK mode. An external timing resistor adjusts the switching
frequency of the device; In CLK mode, the device synchronizes to an external clock.
描述
编号
Return
for control circuitry and low-side power MOSFET.
自动在
模式与
CLK模式间进行选择。通过一个外部的时基电阻可对器件的开关频率进行调整；在
Power1input. Supplies
theRT
power
switches
of the power converter.
CLK模式下，器件将同步于一个外部时钟。
Supplies the control circuitry of the power converter.
控制电路与低边MOSFET电路的回路。
2, 3
Inverting input of the gm error amplifier.
电源输入。为转换器的电源开关供电。
4, 5
Error amplifier output,
and input to the output switch current comparator. Connect frequency compensation to this
为转换器的控制电路供电。
6
pin.
7
gm误差信号放大器的倒向输入。
Slow-start and tracking. An external capacitor connected to this pin sets the internal voltage reference rise time.
误差信号放大器的输出，同时也是输出开关电流比较电路的输入。可将频率补偿电路连接至该引脚。
8
The voltage on this pin overrides the internal reference. It can be used for tracking and sequencing.
慢启动及跟踪。通过一个连接至该引脚的外部电容设置内部参考电压的上升时间。该引脚上的电压优
Enable9 pin. Float to先于内部参考电压，它能够被跟踪及排序。
enable. Adjust the input undervoltage lockout with two resistors.
The switch
node. 使能引脚。浮动使能。通过两个电阻器调节输入欠压锁定。
10
开关节点。
A bootstrap
between BOOT and PH. The voltage on this cap carries the gate drive voltage for the
11, 12 cap is required
high-side
13 MOSFET.在BOOT与PH之间需要一个自举电容器。该导线上的电压为高边MOSFET的触发驱动电压。
Power Good fault pin.
Asserts low if output voltage is low due to thermal shutdown, dropout, over-voltage, EN
电源良好性判断引脚。由于热关断、压差、过压、使能关断或处于慢启动状态时导致的输出电压为低
14 or during电平时，该引脚也为低电平。
shutdown
slow start.
15 pad of the封装的散热焊盘及信号地。它必须以正确的方式进行焊接。
Thermal
package and signal ground. It must be soldered down for proper operation.
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原理框图
FUNCTIONAL
BLOCK DIAGRAM
PWRGD
VIN
EN
Shutdown
Ip
Ih
Enable
Comparator
Thermal
Shutdown
PVIN PVIN
UVLO
Shutdown
UV
Shutdown
Logic
Logic
Enable
Threshold
OV
Boot
Charge
Current
Sense
Minimum�Clamp
Pulse�Skip
ERROR
AMPLIFIER
VSENSE
BOOT
Boot
UVLO
SS/TR
HS�MOSFET
Current
Comparator
Voltage
Reference
Power�Stage
& Deadtime
Control
Logic
PH
PH
Slope
Compensation
VIN
Overload�Recovery
and
Clamp
Oscillator
with�PLL
Regulator
LS�MOSFET
Current�Limit
Current
Sense
GND
GND
COMP
6
6
RT/CLK
POWERPAD
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– MAY 年
2009
典型特征
TYPICAL CHARACTERISTICS
特性曲线
CHARACTERISTIC CURVES
高边Rdson
与温度关系曲线
HIGH-SIDE
Rdson
vs TEMPERATURE
低边Rdson
LOW-SIDE
Rdson与温度关系曲线
vs TEMPERATURE
30
VIN = 12 V
开通时阻抗
RDS(on)
Resistance
mΩ
RDS(on) −– On
– m−Ω
开通时阻抗
RDS(on) −– On
– m−Ω
RDS(on)
Resistance
mΩ
40
35
30
25
20
−50
−25
0
25
50
75
100
125
VIN = 12 V
27
24
21
18
15
−50
150
−25
fO −fO
Oscillator
Frequency
– 振荡器频率
– kHz− kHz
–V −V
ref – 参考电压
Vref −VVoltage
Resistance
0.801
0.799
0.797
0
25
50
75
100
125
485
480
475
470
−50
150
−25
50
75
100
Figure
图4 4.
En Pin
Hysterisis Current
− µA
En引脚磁滞电流
– µA
EN = 0 V
TJ = 150°C
TJ = −40°C
2
1
9
12
150
PIN HYSTERISIS
CURRENT vs TEMPERATURE
引脚磁滞电流与温度关系曲线
3.50
6
125
J
SHUTDOWN
QUIESCENT CURRENT vs INPUT VOLTAGE
关断静态电流与输入电压关系曲线
关断静态电流
25
Figure
图3 3.
J
IsdShutdown
–
– µA
Isd −
Quescent
− µA
0
TJ − Junction
Temperature
T - 结温度
- ℃ − °C
TJ = 25°C
150
RT = 100 kΩ
TJ − Junction
Temperature
T – 结温度
– ℃ − °C
3
125
OSCILLATOR
FREQUENCY vs TEMPERATURE
振荡器频率与温度关系曲线
490
3
100
Figure
图2 2.
0.803
0
75
J
VOLTAGE
REFERENCE vs TEMPERATURE
参考电压与温度关系曲线
4
50
Figure
图1 1.
0.805
−25
25
TJ − Junction
Temperature
T - 结温度
- ℃ − °C
J
0.795
−50
0
TJ − Junction
Temperature
T – 结温度
– ℃ − °C
15
18
VIN = 12 V
EN = 1.3 V
3.45
3.40
3.35
3.30
−50
−25
0
25
50
75
100
VV
Voltage
−V
I −–Input
输电电压
–V
TJ − Junction
Temperature
T - 结温度
- ℃ − °C
Figure
图 5.
Figure
图 6.
I
125
150
J
5
6
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典型特征（续） (continued)
TYPICAL CHARACTERISTICS
引脚UVLO门限值与温度关系曲线
引脚上拉电流与温度关系曲线
PIN PULLUP CURRENT vs TEMPERATURE
1.220
VIN = 12 V
EN = 1.1 V
En引脚UVLO门限值 – V
En Pin UVLO Threshold − V
IP − En Pin On Pullup − uA
IP En引脚开通时上拉电流 uA
1.20
PIN UVLO THRESHOLD vs TEMPERATURE
1.15
1.10
−50
−25
0
25
50
75
100
125
1.215
1.210
1.205
1.200
−50
150
0
25
125
150
SLOW START
CHARGE CURRENT vs TEMPERATURE
慢启动充电电流与温度关系曲线
2.5
800
ISS – 慢启动充电电流 – µA
TJ = −40°C
700
TJ = −25°C
TJ = 150°C
600
500
3
6
12
9
2.4
2.3
2.2
2.1
−50
15
−25
0
25
PWRGD门限电流 – µA
0.03
0.02
25
50
125
150
门限值与温度关系曲线
PWRGD
THRESHOLD
vs TEMPERATURE
PWRGD
PWRGD Threshold Current − µA
0.04
0
100
图1010.
Figure
120
−25
75
TJ – 结温度 – ℃
偏置电压与温度关系曲线
(SS/TR
OFFSET
vs TEMPERATURE
(SS/TR- VSENSE)
- VSENSE)
0.01
−50
50
TJ − Junction Temperature − °C
0.05
(SS/TR - Vsense) Offset − V
100
Figure
图8 8.
图9 9.
Figure
(SS/TR - Vsense) 偏置电压 – V
75
TJ − Junction
Temperature
TJ – 结温度
– ℃ − °C
输入电压
VIV−I –Input
Voltage– −V V
75
100
125
150
VIN = 12 V
VSENSE Rising
110
VSENSE Falling
100
VSENSE Rising
90
80
−50
TJ − Junction
Temperature
结温度
℃ − °C
VSENSE Falling
−25
0
25
50
75
100
125
150
TJ − Junction
Temperature
结温度
℃ − °C
TJ –
–
Figure
11.
图11
8
8
50
Figure
图7 7.
ISS − Slow Start Charge Current − µA
非转换时工作静态电流 – µA
Non-Switching Operating Quiescent Current − µA
−25
TJ − Junction
Temperature
TJ – 结温度
–Deg − Deg
NON-SWITCHING OPERATING QUIESCENT CURRENT
(VIN) vs INPUT
VOLTAGE
非转换时工作静态电流
与输入电压关系曲线
(VIN)
400
VIN = 12 V
TJ –
–
Figure
12.
图12
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典型特征（续） (continued)
TYPICAL CHARACTERISTICS
HIGH-SIDE CURRENT LIMIT THRESHOLD vs INPUT
高边电流限制门限值与输入电压关系曲线
VOLTAGE
最小可控开通时间与温度关系曲线
MINIMUM CONTROLLABLE
ON TIME vs TEMPERATURE
120
ns − ns
Minimum Controllable On–Time
12
11
最小可控开通时间
IcI IcI
− Current
Limit Threshold
– 电流限制门限值
– A− A
13
10
TJ = −40°C
9
TJ = 25°C
8
TJ = 150°C
7
6
5
1
5
9
13
VIN = 12 V
IOUT = 2A
110
100
90
80
70
−50
17
−25
50
75
100
TJ − Junction
Temperature
T – 结温度
– ℃ − °C
Figure
图1313.
Figure
图1414.
125
150
J
MINIMUM CONTROLLABLE DUTY RATIO vs JUNCTION
TEMPERATURE
最小可控负荷比与结温度关系曲线
BOOT-PH
UVLOUVLO
THRESHOLD
vs TEMPERATURE
门限值与温度关系曲线
BOOT-PH
2.2
6.0
门限值 – V− V
BOO-PH
BOO-PHUVLO
UVLO Threshold
Dmin −Dmin
Minimum
Controllable Duty
Ratio − %
– 最小可控负荷比
–%
25
VI −VInput
Voltage
– 结温度
– V− V
I
5.0
4.0
3.0
−50
0
RT = 100 kΩ
VIN =12 V
IOUT = 2 A
−25
0
25
50
75
100
125
150
2.1
2.0
−50
−25
0
25
50
75
100
125
150
TJ − Junction Temperature − °C
TJ − Junction
Temperature
T – 结温度
– Deg − Deg
VI – 结温度 – ℃
Figure
图 16.
J
Figure
图 15.
15
16
OVERVIEW
概述
The device is a 17-V, 6-A, synchronous step-down (buck) converter with two integrated n-channel MOSFETs. To
improve
performance
during line and load transients the device implements a constant frequency, peak current
该器件是
17V、6A、带两个集成了n通道的MOSFET的同步降压转换器。为了提高电源及负载瞬态变化过程中的性能，该器
mode control which also simplifies external frequency compensation. The wide switching frequency of 200 kHz to
件采用了一个恒定频率、峰值电流的模式控制，这也简化了外部频率补偿。从
这样一个比较宽泛的开关频
kHz到1600
1600 kHz allows for efficiency and size optimization when selecting 200
the output
filterkHz
components.
The switching
frequency is adjusted using a resistor to ground on the RT/CLK pin. The device
also
has
an
internal
phase lock
率，可以在选择输出滤波器的部件时确保效率及尺寸上的最优化。开关频率的调节是通过
引脚上接地电阻实现的。该器
RT/CLK
loop (PLL) controlled by the RT/CLK pin that can be used to synchronize the switching cycle to the falling edge
件还具有一个由RT/CLK引脚所控制的内部锁相环(PLL)，可用于使开关周期与一个外部系统时钟的下降沿保持同步。
of an external system clock.
The该器件设计用于安全的单调启动预偏执负载。默认的启动是当
device has been designed for safe monotonic startup into
loads. The
start up is when VIN
为 4.0V 的典型值时。
引脚具有一个内部的上拉电流
VINpre-biased
ENdefault
is typically 4.0V. The EN pin has an internal pull-up current source that can be used to adjust the input voltage
源，可用于调节输入电压欠压锁定(UVLO)，调节是通过两个外部的电阻器实现的。此外，EN引脚可浮动，使得通过内部上拉电
under voltage lockout (UVLO) with two external resistors. In addition, the EN pin can be floating for the device to
流实现器件的操作。当不执行切换功能且无负载的条件下，器件总的工作电流大约为
。当设备被禁用时，供电电流通常小
operate with the internal pull up current. The total operating current for the600µA
device
is approximately 600µA when
not
switching
and
under
no
load.
When
the
device
is
disabled,
the
supply
current
is
typically less than 2µA.
于
。
2µA
The integrated MOSFETs allow for high efficiency power supply designs with continuous output currents up to 6
集成的MOSFET
可实现高效率的供电设计，使得连续输出电流高达
按尺寸进行了处理，用以针对更低
6安培。这些
MOSFET
amperes.
The MOSFETs
have been sized to optimize efficiency
for lower duty
cycle
applications.
占空比的应用进行效率优化。
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典型特征（续）
该器件通过集成启动充电电路，减少了外部元件的数量。集成的高边MOSFET的偏置电压是通过BOOT和PH引脚间的电容
器所提供的。这个启动电容器电压被一个“BOOT到PH UVLO” (BOOT-PH UVLO)电路所监控，它允许PH引脚被拉低来为启动
电容器充电。该器件能工作在100%占空比下，只要启动电容器的电压高于预设的BOOT-PH UVLO 2.1V的典型门限值即可。输
出电压可步降至0.8V的参考电压值(Vref)。
该器件具有一个带磁滞的电源良好性比较器 (PWRGD) ，通过 VSENSE 引脚监测输出电压。 PWRGD 引脚是一个开漏
MOSFET，当VSENSE引脚电压值低于91%或高于109%的参考电压Vref时将被拉低，而当VSENSE引脚电压在94%到106%的参
考电压Vref时， PWRGD引脚则输出为高电平。
SS/TR（慢启动/跟踪）引脚用于最小化浪涌电流或在功率升高时提供电源排序。该引脚上需匹配一个小值的电容或电
阻分压器，以满足慢启动或关键电源排序的要求。
该器件具有保护机制，能够免受输出过压、过载及热故障等条件下对器件造成的损害。它利用过压电路电源良好比
较器(overvoltage circuit power good comparator)，最大程度的减少了额外的输出过压瞬变。一旦过压比较器被激活，高边
MOSFET将被关闭，无法打开，直到VSENSE引脚电压值低于106%的Vref为止。该器件同时采用高边MOSFET过载保护和双向
低边MOSFET过载保护，以达到控制电感电流和避免电流暴增的目的。该器件能在结温高于热关断临界点时自动停止工作。而
当结温降至10℃，低于热关断临界点时，器件还能在慢启动电路的控制下自动重启。
详细说明
固定频率PWM控制
该器件采用了可调的固定频率，峰值电流模式控制。输出电压被驱动COMP引脚的误差信号放大器，通过VSENSE引脚上
的外部电阻与一个内部参考电压做比较。内部振荡器激活了高边电源开关的打开。误差信号放大器的输出将转化为一个参考电
流，与高边电源开关电流相比较。当电源开关电流达到了产生自COMP电压电平的参考电流值时，高边电源开关将被关闭，而
低边电源开关将被打开。
连续电流模式下的运行 (CCM)
作为一个同步降压转换器，该器件通常工作在CCM（连续传导模式）的所有负载条件下。
VIN及Power VIN引脚 (VIN及PVIN)
该器件支持同时或分别使用VIN及PVIN引脚的多种应用。VIN引脚的电压用以为器件的内部控制电路供电。PVIN引脚的电压
用以为电源转换系统提供输入电压。如果绑定使用， VIN及PVIN的输入电压范围可由4.5V至17V。如果将它们分开使用，VIN引
脚的输入电压必须介于4.5V和17V之间，而PVIN引脚的输入电压范围可降低至1.6V至17V之间。连接至EN引脚的分压器可用于适
当的调整输入电压UVLO。在PVIN引脚上对输入电压UVLO的调整提供了一致的上电行为。
参考电压
参考电压系统通过测量一个温度稳定带隙电路的输出电压，能产生一个受温度影响不超过±1%的精确参考电压。
10
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调整输出电压
Adjusting the Output Voltage
引脚到VSENSE
(VOUT)
1%It的公差或更好的分压器
The 输出电压通过一个从输出
output voltage is set with
a resistor
divider 引脚之间的电阻分压器进行设定。我们推荐使用
from the output (VOUT) to the VSENSE pin.
is recommended to
use
1%
tolerance
or
better
divider
resistors.
Referring
to
the
application
schematic
of
Figure
34, start with a 10
电阻。关于图34中所示的应用电路，从10kΩ的R6开始并且使用等式1来计算R5。为了在低负载时提高效率，可考虑使用阻值较
kȍ for R6 and use Equation 1 to calculate R5. To improve efficiency at light loads consider using larger value
大的电阻。如果阻值太高，调节器将更容易受到噪声影响，并且由于
输入电流导致的电压误差将会很明显。
resistors. If the values are too high the regulator is moreVSENSE
susceptible
to noise and voltage errors from the
VSENSE input current are noticeable.
Vo � Vref
R5 �
R6
Vref
(1)
Where Vref = 0.8V
这里Vref = 0.8V
The minimum output voltage and maximum output voltage can be limited by the minimum on time of the
high-side MOSFET and bootstrap voltage (BOOT-PH voltage) respectively. More discussions are located in
最小输出电压和最大输出电压分别受高边MOSFET及自举电压(BOOT-PH电压)的最小开通时间所限制。在“最小输出电压”
Minimum Output Voltage and Bootstrap Voltage
(BOOT) and Low Dropout Operation.
及“自举电压(BOOT)与低压差操作”两个部分中将会有更进一步的讨论。
Safe Start-up into Pre-Biased Outputs
安全启动预偏置输出
The device has been designed to prevent the low-side MOSFET from diacharging a prebiased output. During
monotonic
pre-biased startup, the low-side
MOSFET
is not allowed to sink current until the SS/TRMOSFET
pin voltage
is
该器件专门进行了设计，防止由于低边
放电而产生一个预偏置输出。当单调预偏执启动时，低边
不接收
MOSFET
higher than 1.4V.
灌电流，直到SS/TR引脚电压值高于1.4V时。
Error Amplifier
误差信号放大器
The device uses a transconductance error amplifier. The error amplifier compares the VSENSE pin voltage to the
该器件采用了跨导误差信号放大器，它把
引脚电压与
引脚电压的较低值或
VSENSE
0.8V的内部参考电压进行比较。正
lower
of the SS/TR pin voltage or the internal
0.8V
voltage SS/TR
reference.
The transconductance
of the error amplifier
is
1300
µA/V
during
normal
operation.
The
frequency
compensation
network
is
connected
between the COMP
常工作时，误差信号放大器的跨导是1300µA / V。频率补偿部分连接在COM引脚与参考地之间。
pin and ground.
斜率补偿
Slope Compensation
该器件为开关电流信号增加了斜坡补偿。这一斜率补偿用以防止次谐波振荡。在整个工作周期范围内，已有的峰值电感电
The device adds a compensating ramp to the switch current signal. This slope compensation prevents
流将保持不变。
sub-harmonic oscillations. The available peak inductor current remains constant over the full duty cycle range.
Enable and Adjusting Under-Voltage Lockout
使能及调整欠压锁定
The EN
EN
pin provides electrical
on/off control
of the device. Once the EN pin voltage exceeds
the threshold
引脚提供器件的电动开
/关控制。一旦
EN引脚上的电压值超过了门限电压，器件将开始工作。如果
EN引脚电压值被拉至
voltage, the device starts operation. If the EN pin voltage is pulled below the threshold voltage, the regulator
低于门限电压，调节器将停止开关动作并进入低Iq状态。
stops switching and enters low Iq state.
The EN
EN引脚具有一个内部上拉电流源，允许用户通过浮动
pin has an internal pullup current source, allowing
the user to float the EN pin for enabling
the device. If
EN引脚来启动器件。如果实际应用中需要对
EN引脚进行控制，使用
an
application
requires
controlling
the
EN
pin,
use
open
drain
or
open
collector
output
logic
to
interface
with the
开漏或通过该引脚打开集电极输出逻辑至接口。
pin.
The 该器件在
device implements
internal UVLO
UVLO电路。当
circuitry
on
the VIN pin. The device
is disabled
when the VIN pin voltage
引脚电压值降至低于内部
门限值时，器件将被禁用。内部
VIN引脚上加装了内部
VIN
VIN UVLO
VIN
falls below
the
internal
VIN
UVLO
threshold.
The
internal
VIN
UVLO
threshold
has
a
hysteresis
of 150mV.
门限值具有
的磁滞。如果实际应用中要求在
引脚上有较高的
门限值，或在
引脚上有次级
，
UVLO
150mV
VIN
UVLO
PVIN
UVLO
If an application requiresEN
either
a higher UVLO
on the VIN pin or aUVLO
secondary
UVLO on the PVIN, in
比如在分离轨应用中，此时
引脚可配置为如图
功能时，建议将磁滞设置为大于
17、threshold
18、19所示的情形。当使用外部
split rail applications, then the EN pin can be configured as shown in Figure 17, Figure 18 and Figure 19. When
。 external UVLO function it is recommended to set the hysteresis to be greater than 500mV.
500mV
using the
The EN
EN
pin has a small pull-upIp，当没有外部元件连接时，
current Ip which sets the
default state of the pin to enable when no external
引脚具有一个小的上拉电流
Ip用以将引脚的默认状态设置为使能。该上拉电流还用于控制
components are connected. The pull-up current is also used to control the voltage hysteresis for the UVLO
功能的电压磁滞，一旦EN引脚通过使能门限时，它将增加至Ih。UVLO门限值可使用等式2、3进行计算。
UVLO
function since it increases
by Ih once the EN pin crosses the enable threshold. The UVLO thresholds can be
calculated using Equation 2 and Equation 3.
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TPS54620
TPS54620
ZHCS004–2009
5月 ........................................................................................................................................................................................................
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2009
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SLVS949 – MAY 2009 ........................................................................................................................................................................................................ www.ti.com
TPS54620
TPS54620
VIN
VIN
ip
ip
R1
R1
R2
R2
EN
ih
ih
EN
Figure 17. Adjustable
VIN
Under
Voltage Lock Out
图17.VIN
可调
欠压锁定
VIN
Figure 17. Adjustable
Under
Voltage Lock Out
TPS54620
TPS54620
PVIN
PVIN
ip
ip
R1
R1
R2
R2
EN
ih
ih
EN
Figure 18. Adjustable PVIN Under Voltage Lock Out, VIN • 4.5V
Figure 18. Adjustable
Under
Voltage
Lock
Out, VIN • 4.5V
图18.PVIN
可调PVIN
欠压锁定，
≥ 4.5V
VIN
TPS54620
TPS54620
PVIN
PVIN
VIN
VIN
ip
ip
ih
ih
R1
R1
R2
R2
EN
EN
19. VIN VIN
PVIN Under Voltage Lock Out
Figure 19. Adjustable
and PVIN
Figure 19. Adjustable VIN and PVIN Under Voltage Lock Out
图
可调
及
欠压锁定
� VENFALLING �
� V�ENFALLING
� � � VSTOP
VSTART
VSTART
� � VENRISING
� �� VSTOP
V
R1 =
ENRISING �
�
R1 =
�
�
�I 1V� VENFALLING
� � � Ih
�
Ip �1p �� ENFALLING
� �Ih
� V VENRISING
ENRISING �
�
(2)
R1� VENFALLING
R1� VENFALLING
R2 =
R2 =
VSTOP � VENFALLING � R1(Ip � Ih )
VSTOP � VENFALLING � R1(Ip � Ih )
(3)
Where I = 3.4 µA, I = 1.15 µA, VENRISING = 1.21 V, VENFALLING = 1.17 V
= 1.21 V, VENFALLING = 1.17 V
Where
这里 Ih =h 3.4 µA, Ip =p 1.15 µA, VENRISING
(2)
(3)
Adjustable Switching Frequency and Synchronization (RT/CLK)
Adjustable
Switching(RT/CLK)
Frequency and Synchronization (RT/CLK)
可调开关频率及同步
The RT/CLK pin can be used to set the switching frequency of the device in two mode.
The
RT/CLK
pin can be used to set the switching frequency of the device in two mode.
引脚可用以对器件两种模式下的开关频率进行设定。
RT/CLK
12
12
12
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Copyright © 2009, 版权所有：德州仪器
Texas Instruments Incorporated
© 2009
Copyright © 2009, Texas Instruments Incorporated
TPS54620
TPS54620
TPS54620
ZHCS004–2009
5月
www.ti.com.cn
www.ti.com ........................................................................................................................................................................................................ SLVS949
– MAY 年
2009
www.ti.com ........................................................................................................................................................................................................ SLVS949 – MAY 2009
In RT mode, a resistor (RT resistor) is connected between the RT/CLK pin and GND. The switching frequency of
the
device
is aadjustable
from
200 kHz
to 1600 kHz
by placing
a maximum
of 240
kOhm
minimum
of 29 kŸ
In RT
mode,
resistor (RT
resistor)
is connected
between
the RT/CLK
pin and
GND.
Theand
switching
frequency
of
在RT模式下，在
引脚与
之间连接一个电阻（
电阻）。器件的开关频率从
至and
RT/CLK
GND
200
kHz
1600minimum
kHz
respectively.
CLK
mode,
an200
external
clock
is kHz
connected
directly
to the RT/CLK
pin.
The
device
is可调，分别通过
synchronized
the device
is In
adjustable
from
kHz
to
1600
byRT
placing
a maximum
of 240
kOhm
of 29 kŸ
to
the external
clock
frequency
with
PLL.
respectively.
In240
CLK
mode,
an external
clock is connected
directly to the RT/CLK pin. The RT/CLK
device 引脚，器件通过锁
is synchronized
放置一个最大为
及最小为
kOhm
29 kΩ的电阻来实现。在
CLK模式下，一个外部时钟被直接连接至
to
the
external
clock
frequency
with
PLL.
The CLK mode overrides the RT mode. The device is able to detect the proper mode automatically and switch
相环(PLL)直接同步于外部时钟频率。
from
the RT
mode
to CLK the
mode.
The CLK
mode
overrides
RT mode. The device is able to detect the proper mode automatically and switch
fromCLK
the模式优先于
RT modeRT
to模式。器件能够自动检测到正确的模式并在
CLK mode.
RT模式与CLK模式间进行切换。
Adjustable Switching Frequency (RT Mode)
Adjustable
Frequency
可调开关频率
(RTRT
Mode)
To determineSwitching
the
resistance
for a (RT
givenMode)
switching frequency, use Equation 4 or the curve in Figure 20. To
reduce
the solution
size
one would
the switching
asuse
high
as possible,
but curve
tradeoffs
of the 20.
supply
To determine
the20
RT
resistance
for set
a given
switchingfrequency
frequency,
Equation
4 or the
in Figure
To
通过公式4或图
所示的曲线，可根据给定的开关频率确定
RT电阻值。为了减小解决方案的尺寸，应将开关频率设置得尽可
efficiency
minimum
should be frequency
considered.
reduce theand
solution
sizecontrollable
one would on
set time
the switching
as high as possible, but tradeoffs of the supply
能高，但供电效率和最小可控开通时间的折中也应加以考虑。
efficiency
controllable
Rrt(kand
� ) =minimum
48000 � Fsw
�kHz �� 0.997on� 2time should be considered.
� 0.997
Rrt(k � ) = 48000 � Fsw �kHz �
(4)
(4)
�2
250
– −电阻
– kΩ
RTRT
−RT
Resistance
Resistance
− kΩ− kΩ
250
200
200
150
150
100
100
50
50
0
200
0
200
400
400
600
1400
1600
600
800 Frequency
1000
1200
Fsw
− Oscillator
− kHz 1400
800
1000
1200
1600
FswFsw
− Oscillator
Frequency
− kHz
– 振荡器频率
– kHz
Figure 20. RT Set Resistor vs Switching Frequency
Figure 20.图RT
Resistor vs Switching Frequency
20.Set
RT设置电阻与开关频率关系曲线
Synchronization (CLK mode)
Synchronization
(CLK mode)
An internal
Phase Locked
Loop (PLL) has been implemented to allow synchronization between 200kHz and
同步（
CLK模式）
1600kHz,
to easily
switch
from(PLL)
RT mode
to CLKimplemented
mode.
An internaland
Phase
Locked
Loop
has been
to allow synchronization between 200kHz and
该器件具有一个内部锁相环
，用以实现从
至mode.
(PLL)
200kHz
1600kHz的同步，以及在RT模式与CLK模式间的轻松切换。
1600kHz,
and
to
easily
switch
from
RT
mode
to
CLK
To implement the synchronization feature, connect a square wave clock signal to the RT/CLK pin with a duty
cycle
between the
20%synchronization
to 80%. The
clock
signal
amplitude
must
transition
0.8VRT/CLK
and higher
thana2.0V.
To implement
feature,
connect
a20%
square
wave
clocklower
signalthan
to the
pin with
duty
为了执行同步功能，在
至80%
的方波时钟信号。时钟信号的幅度转换时低电平必须低
RT/CLK引脚上连接一个占空比从
The
of the 20%
switching
cycle
is synchronized
to the falling
edge
of RT/CLK
pin.
cyclestart
between
to 80%.
The
clock signal amplitude
must
transition
lower
than 0.8V and higher than 2.0V.
于
且高电平必须高于
。开关周期的开始应同步于
引脚的下降沿。
0.8V
2.0Vcycle
RT/CLK
The
start
of the where
switching
synchronized
the
falling
edge of RT/CLK
pin.can be configured as shown in
In applications
both RT ismode
and CLKtomode
are needed,
the device
Figure
21. Before
external
clock
is and
present,
device
in 所示的情形。在外部时钟出现之前，器件工作在
RT
thebeswitching
frequency
is set
In applications
where
both RT
mode
CLK the
mode
are works
needed,
themode
deviceand
can
configured
as shown
in
在某些既需要
模式又需要
模式的应用中，该器件可配置为如图
RTthe
CLK
21
RT
by
RT 21.
resistor.
When
the external
is present,
the CLK
mode
overrides
thethe
RTswitching
mode. The
first time
Figure
Before
the external
clockclock
is present,
the device
works
in RT
mode and
frequency
is the
set
模式下，开关频率由
电阻进行设置。一旦外部时钟出现，
模式将优先于
模式。在第一次
引脚被拉高至超过
RT
CLK
RTswitches
RT/
SYNC
is pulled
above
RT/CLK
high
(2.0V),
the
device
the
RT
mode
to time
the CLK
by RT pin
resistor.
When
the the
external
clock
is threshold
present, the
CLK
mode
overrides
thefrom
RT SYNC
mode.
The
first
the
mode
and
the
RT/CLK
pin the
becomes
high
impedance
as
the PLL
PLL
starts
lock onto
the the
frequency
of the
external
高门限值
时，器件将由
模式切换至
模式，并且由于
开始锁定外部时钟，
引脚将变为高阻抗态。我们
CLK
(2.0V)
RTRT/CLK
CLK
RT/CLK
SYNC
pin is
pulled
above
high
threshold
(2.0V),
the
devicetoswitches
from
RT mode
to the
CLK
clock.
It is the
not
recommended
to switch
from
the CLK as
mode
back
to theto
RT
mode
because
the internal
switching
mode and
RT/CLK
pin
becomes
high
impedance
the
PLL
starts
lock
onto
the
frequency
of
the
external
不建议由
模式切换回
模式，因为内部开关频率在返回至由
电阻所设定的开关频率之前，将先降至
。
CLK
RT
RT
100kHz
frequency
to 100kHz first
themode
switching
by RT
resistor.
clock. It is drops
not recommended
to before
switch returning
from the to
CLK
backfrequency
to the RTset
mode
because
the internal switching
frequency drops to 100kHz first before returning to the switching frequency set by RT resistor.
RT/CLK
mode�select
RT/CLK
mode�select
Rrt
Rrt
TPS54620
TPS54620
RT/CLK
RT/CLK
21. 同时工作在
RT模式及
CLK模式下
Figure 21. 图
Works
with Both
RT mode
and CLK mode
Figure 21. Works with Both RT mode and CLK mode
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Incorporated
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©Instruments
2009
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TPS54620
ZHCS004–2009
5月 ........................................................................................................................................................................................................
www.ti.com.cn
SLVS949 – MAY年
2009
www.ti.com
Slow Start (SS/TR)
慢启动(SS/TR)
The device uses the lower voltage of the internal voltage reference or the SS/TR pin voltage as the reference
该器件采用了更低电压值的内部参考电压或
SS/TRA引脚电压作为参考电压，并相应的调节输出。一个位于
SS/TR引脚与参考地
voltage
and regulates the output accordingly.
capacitor on the SS/TR pin to ground implements
a slow start
time.
The
device
has
an
internal
pull-up
current
source
of
2.3µA
that
charges
the
external
slow
start capacitor.
之间的电容器实现了慢启动时间。该器件具有一个2.3µA的内部上拉电流源，用以为外部慢启动电容器充电。慢启动时间（
Tss，
The calculations for the slow start time (Tss, 10% to 90%) and slow start capacitor (Css) are shown in
至
）与慢启动电容器
之间的计算关系如等式
所示。参考电压
为
，慢启动充电电流
为
。
10% 90%
(Css)
5
0.8V
(Iss) 2.3 µA
Equation 5. The voltage reference
(Vref) is 0.8 V and
the slow start(Vref)
charge
current (Iss) is 2.3µA.
Tss(ms) =
Css(nF) � Vref(V)
Iss(� A)
(5)
When the input UVLO is triggered, the EN pin is pulled below 1.21V, or a thermal shutdown event occurs the
device
stops
switching
and
enters low 1.21V
current
operation. At the subsequent power up, when the shutdown
当输入
被触发时，
，或发生热关断，器件将停止开关动作并进入低电流工作状态。在随后的上
UVLO
EN引脚将被拉低
condition is removed, the device does not start switching until it has discharged its SS/TR pin to ground ensuring
电状态中，当不满足关断条件时，器件不会马上进行开关动作，直到通过它的SS/TR引脚向参考地放电完毕为止以确保正确的软
propper soft start behavior.
启动行为。
Power Good (PWRGD)
电源良好引脚(PWRGD)
The PWRGD pin is an open drain output. Once the VSENSE pin is between 94% and 106% of the internal
voltage
reference
the PWRGD pin VSENSE
pull-down
is de-asserted and94%
the 到pin
floats.
It isPWRGD
recommended
to use a
引脚是一个开漏输出。一旦
引脚值为内部参考电压的
之间时，
引脚下拉至低电平并
PWRGD
106%
pull-up resistor between the values of 10kŸ and 100kŸ to a voltage source that is 5.5V or less. The PWRGD is
且引脚浮动。我们推荐在等于或小于5.5V的电压源位置处使用一个阻值在10kΩ到100kΩ之间的上拉电阻器。当VIN输入电压高
in a defined state once the VIN input voltage is greater than 1V but with reduced current sinking capability. The
于
将处于一个确定的状态。一旦
1V但仅具有部分的消耗电流能力时，
PWRGD
VIN输入电压高于
4.5V，PWRGD将达到完全的消
PWRGD
achieves full current sinking
capability
once the VIN input voltage
is above 4.5V.
耗电流能力。
The PWRGD pin is pulled low when VSENSE is lower than 91% or greater than 109% of the nominal internal
reference voltage. Also, the PWRGD is pulled low, if the input UVLO or thermal shutdown are asserted, the EN
当pulled
低于正常的内部参考电压值的
或高于参考电压值的109%时，PWRGD将被拉低。同样的，如果输入UVLO
VSENSE
91%
pin is
low
or the SS/TR pin is below
1.4V.
或热关断置高位、EN引脚被拉低或SS/TR引脚低于1.4V时，PWRGD也将被拉低。
Bootstrap Voltage (BOOT) and Low Dropout Operation
自举电压
(BOOT)
The device
has an及低压差操作
integrated boot regulator, and requires a small ceramic capacitor between the BOOT and PH
pins to provide the gate drive voltage for the high-side MOSFET. The boot capacitor is charged when the BOOT
该器件具有一个集成的启动调节器，并且需要在BOOT 与 PH 引脚间加装一个小的陶瓷电容器以防止高边MOSFET的触发
pin voltage is less than VIN and BOOT-PH voltage
is below regulation. The value of this ceramic capacitor
驱动电压。当
电压为低调节时，启动电容器将被充电。这个陶瓷电容器的电容值应为
BOOTA引脚电压低于
VIN 并且with
BOOT-PH
should be 0.1µF.
ceramic capacitor
an X7R
or X5R grade dielectric with a voltage rating of 10V or higher
is recommended
because
of 绝缘等级、额定电压为
the stable characteristics
over temperature and voltage.
。我们推荐具有
0.1µF
X7R或X5R
10V或更高的陶瓷电容器，因为这样的电容器对于温度及电压影响具有比
To improve drop out, the device is designed to operate at 100% duty cycle as long as the BOOT to PH pin
较稳定的特性。
voltage is greater than the BOOT-PH UVLO threshold which is typically 2.1V. When the voltage between BOOT
and 为了改善压差，该器件设计为将工作在
PH drops below the BOOT-PH UVLO
threshold the BOOT
high-side
MOSFET isBOOT-PH
turned off
and2.1V
the的典型门限
low-side
至PH引脚电压高于
100%的占空比下，只要
UVLO
MOSFET is turned on allowing the boot capacitor to be recharged. In applications with split input voltage rails
值即可。当BOOT与PH间的电压降至低于BOOT-PH UVLO门限值时，高边MOSFET将被关闭，而低边MOSFET将打开，以允许
100% duty cycle operation can be achieved as long as (VIN – PVIN) > 4V.
启动电容器被充电。在带有分离输入电压轨的实际应用中，只要(VIN – PVIN) > 4V就能实现100%占空比的工作状态。
Sequencing (SS/TR)
排序(SS/TR)
Many of the common power supply sequencing methods can be implemented using the SS/TR, EN and PWRGD
pins.使用SS/TR，EN和PWRGD引脚，能够实现许多常见的电源排序方法。
The sequential method is illustrated in Figure 22 using two TPS54620 devices. The power good of the first
使用两个
器件实现的顺序法如图
TPS54620
22所示。第一个器件的电源良好引脚与第二个器件的
EN引脚相连接，这样一旦
device
is coupled
to the
EN pin of the second
device which enables the second power supply
once the primary
supply reaches regulation. Figure 23 shows
the results of22
Figure
22.
主电源达到调节态时，将激活第二个电源。图
的结果。
23中所显示的是图
14
14
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PWRGD�=�2�V�/�div
TPS54620
TPS54620
PWRGD
EN
EN
SS/TR
SS/TR
EN�=�2�V�/�div
Vout1�=�1�V�/�div
Vout2�=�1�v�/�div
PWRGD
Time�=�20�msec�/�div
Figure
Start Up Sequence
图22.
顺序启动排序
22.Sequencial
Figure
Sequential
Start Up
using EN and PWRGD
图23.23.
使用
引脚的顺序启动
EN及PWRGD
Figure 24 shows the method implementing ratio-metric sequencing by connecting the SS/TR pins of two devices
通过将两个器件的SS/TR引脚连接在一起，实现比例度量排序的方法如图24所示。调节器的输出沿斜坡上升以及达到调节态
together. The regulator
outputs ramp up and reach regulation at the same time. When calculating the slow start
都是在同一时间。当计算慢启动时间时，上拉电流源必须加倍，如等式
所示。图
中所显示的是图
25shows
24的结果。
time the pull up current source must be doubled in Equation 5.5Figure
25
the results
of Figure 24.
EN�=�2�V�/�div
TPS54620
EN
Vout1�=�1�V�/�div
SS/TR
Vout2�=�1�v�/�div
PWRGD
Time�=�20�msec�/�div
TPS54620
EN
SS/TR
PWRGD
Figure 24. Ratiometric Start Up Sequence
图24. 比例度量启动排序
Figure 25. Ratio-metric Startup using Coupled SS/TR
Pins
图25. 连接两个SS/TR引脚的比例启动
Ratio-metric and simultaneous power supply sequencing can be implemented by connecting the resistor network
将如图
所示的
组成的电阻网络与电源输出连接起来，以实现比例度量和同步的电源排序，这里的电源需要加以跟
R1和inR2Figure
of R1
and26R2
shown
26 to the output of the power supply that needs to be tracked or another voltage
reference source. Using Equation
6 and
Equation 7, the tracking resistors
can be calculated
to initiate the Vout2
踪或者是其它电压参考源。在等式
6和等式
7中，可计算出跟踪电阻器，以启动
Vout2，使之稍稍在
Vout1之前、之后或是同一时
slightly before, after or at the same time as Vout1. Equation 8 is the voltage difference between Vout1 and
刻。等式
Vout2. 8是Vout1与Vout2之间的电压差异。
To design
a ratio-metric start up in which theVout2
Vout2
voltage is slightly
greater than Vout1
the Vout1
voltage6和等式
when Vout2
为了设计一个比例度量启动，使得在启动中当
达到调节态时，
电压，在等式
Vout2的电压略大于
7中的
reaches regulation, use a negative number in Equation 6 and Equation 7 for deltaV. Equation 8 results in a
将会是一个负数。若当Vout2达到调节态时Vout2将略低于Vout1，在这样的应用下等式8的结果将为一个正数。正deltaV与
deltaV
positive
number for applications where the Vout2 is slightly lower than Vout1 when Vout2 regulation is achieved.
负
Figure
27 and Figure 27
28和图
show
the results for positive deltaV and negtive deltaV respectively.
deltaV的结果分别如图
28所示。
The deltaV variable is zero volt for simultaneous sequencing. To minimize the effect of the inherent SS/TR to
对于顺序排列，变量deltaV将等于0伏。慢启动电路中固有的SS/TR到VSENSE的偏置(Vssoffset, 29mV)以及由于上拉电流源
VSENSE offset (Vssoffset,
29mV) in the slow start circuit and the offset created by the pullup current source (Iss,
和跟踪电阻所产生的偏置，为了使这些偏置的影响最小化，
和Iss将作为变量出现在等式中。等式
(Iss,2.3
Vssoffset
29给出了
2.3µA)µA)
and
tracking resistors, the Vssoffset and Iss are included
as variables
in the equations. Figure 29
shows
the
result
when
deltaV
=
0V.
当deltaV = 0V时的结果。
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To ensure
proper operation of the device, the calculated R1 value from Equation 6 must be greater than the
为了确保对器件的正确操作，由等式6计算得到的R1的值必须大于等式9中所计算出的。
value calculated in Equation 9.
R1 =
Vout2 + � V
Vssoffset
�
Vref
Iss
(6)
Vref � R1
R2 =
Vout2 + �V � Vref
�V = Vout1 � Vout2
R1 � 2800 � Vout1� 180 � �V
(7)
(8)
(9)
TPS54620
EN
VOUT1
SS/TR
PWRGD
TPS54620
EN
VOUT 2
R1
SS/TR
R2
PWRGD
R4
R3
图26. 比例度量及同步启动排序
Figure 26. Ratiometric
and Simultaneous Startup Sequence
EN�=�2�V�/�div
Vout1�=�1�V�/�div
Vout2�=�1�V�/�div
Time�=�20�msec�/�div
Figure 27. Ratio-metric Startup with Vout1 Leading Vout2
图27. Vout1领先于Vout2时的比例度量启动
16
16
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TPS54620
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TPS54620
5月
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SLVS949 – MAY年2009
EN�=�2�V�/�div
Vout1�=�1�V�/�div
Vout2�=�1�V�/�div
Time�=�20�msec�/�div
Figure 28.图
Ratio-metric
Startup
with Vout2 Leading Vout1
28. Vout2领先于
Vout1时的比例度量启动
EN�=�2�V�/�div
Vout1�=�1�V�/�div
Vout2�=�1�V�/�div
Time�=�20�msec�/�div
Figure 29.图Simultaneous
Startup
29. 同步启动
Output Overvoltage Protection (OVP)
输出过压保护
The device incorporates
an output overvoltage protection (OVP) circuit to minimize output voltage overshoot. For
(OVP)
example, when the power supply output is overloaded the error amplifier compares the actual output voltage to
the 该器件集成了一个输出过压保护
internal reference voltage. If(OVP)
the电路，用以尽可能减少输出电压过冲。例如，当电源输出超载时，误差信号放大器
VSENSE pin voltage is lower than the internal reference voltage for a
会将实际的输出电压与内部参考电压进行比较。如果
引脚电压长时间低于内部参考电压，误差信号放大器的输出将取
considerable time, the output of the error amplifier
maximum output current. Once the condition is
VSENSEdemands
removed,
the
regulator
output
rises
and
the
error
amplifier
output transitions to the steady state voltage. In some
决于最大输出电流。一旦条件不满足，调节器的输出将上升而误差信号放大器的输出将过渡到稳态电压。在一些具有较小输出
applications with small output capacitance, the power supply output voltage can respond faster than the error
电容的应用中，电源输出电压与误差信号放大器相比具有更快的响应速度。这就导致了输出过冲的可能性。
特性通过比较
OVPovershoot
amplifier. This leads to the possibility of an output overshoot. The OVP feature minimizes the
by
comparing
the VSENSE
pin voltage to the OVP threshold.
If the
VSENSE
pin
voltage is greater
than
the OVP
引脚电压与
引脚电压比
门限值高，高边
将被关闭以防
VSENSE
OVP门限值，最大程度的减少了过冲。如果
VSENSE
OVP
MOSFET
threshold the high-side MOSFET is turned off
preventing current from flowing to the output and minimizing output
止电流流向输出端，并减少输出过冲。当
VSENSE电压降至低于OVP门限值时，高边MOSFET将在下一个时钟周期内被打开。
overshoot. When the VSENSE voltage drops lower than the OVP threshold, the high-side MOSFET is allowed to
turn on at the next clock cycle.
过流保护
Overcurrent
Protection
通过同时对高边
MOSFET及低边MOSFET做逐周期的电流限制，使得该器件不会发生过流状况。
The device is protected from overcurrent conditions by cycle-by-cycle current limiting on both the high-side
高边
过流保护
MOSFET
MOSFET
and
the low-side MOSFET.
High-side
MOSFET
overcurrent protection
通过使用
引脚电压来控制以周期为基本单位的一个周期内高边
COMP
MOSFET的关闭及低边MOSFET的打开，该器件以这
The device implements current mode control whichCOMP
uses 引脚电压产生的参考电流进行比较，当峰值开关电流与参考
the COMP pin voltage to control the turn off of the
种方式实现了电流模式控制。在每个周期中，开关电流都与
high-side MOSFET and the turn on of the low-side MOSFET on a cycle by cycle basis. Each cycle the switch
电流相交时，高边开关将被关闭。
current and the current reference generated by the COMP pin voltage are compared, when the peak switch
current intersects the current reference the high-side switch is turned off.
低边MOSFET过流保护
Low-side MOSFET overcurrent protection
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While the low-side MOSFET is turned on its conduction current is monitored by the internal circuitry.
During
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normal operation the low-side MOSFET sources current to the load. At the end of every clock cycle, the low-side
MOSFET sourcing current is compared to the internally set low-side sourcing current limit. If the low-side
当低边current
输出电流给负载。在每一
MOSFET
MOSFET
sourcing
is 打开时，其传导电流将被内部电路所监测。在正常的工作状态下，低边
exceeded the high-side MOSFET is not turned on and the low-side
MOSFET
stays on for the
next cycle. The high-side
MOSFET
is turned on again when the low-side current is below the low-sideMOSFET
sourcing
个时钟周期结束时，低边
的拉电流与固有设定的低边拉电流的限定值相比较。如果低边拉电流过高，高边
将
MOSFET
current limit at the start of a cycle.
ZHCS004–2009年5月
不被打开，并且低边MOSFET将保持原状态至下一时钟周期。当一个时钟周期的开始时，一旦低边电流低于低边拉电流的限制
The low-side
MOSFET
may also sink current from the load. If the low-side sinking current limit is exceeded the
值，高边
将被打开。
MOSFET
low-side MOSFET is turned off immediately for the rest of that clock cycle. In this scenario both MOSFETs are
off until
of the next cycle.
低边the start 也可能从负载吸收电流进来。如果超过了低边灌电流的限制值，低边
将立即被关闭直至该时钟周期
MOSFET
结束为止。在这种情况下两个
MOSFET都关闭，直至下一时钟周期开始。
Thermal Shutdown
MOSFET
The internal thermal shutdown circuitry forces the device to stop switching if the junction temperature exceeds
热关断
175°C typically. The device reinitiates the power up sequence when the junction temperature drops below 165°C
typically.
如果结温度超过了175℃的典型值时，内部的热关断电路将强制器件停止工作。直到结温度降至低于165℃的典型值时，器
件将重新启动上电排序。
Small Signal Model for Loop Response
Figure 30 shows an equivalent model for the device control loop which can be modeled in a circuit simulation
回路响应的小信号模型
program to check frequency response and transient responses. The error amplifier is a transconductance
器件控制回路的等效模型如图
30所示，可以在电路仿真程序中对其进行模拟以检查频率响应及瞬态响应。误差信号放大器
amplifier
with a gm of 1300µA/V.
The error amplifier can be modeled using an ideal voltage controlled current
source.
(2.38 MŸ) and capacitor Coea (20.7 pF) model the open loop gain
and(2.38
frequency
是一个
值为resistor
的跨导放大器。可使用一个理想的电压控制的电流源来模拟误差信号放大器。电阻
gmThe
1300µA/VRoea
Roea
MΩ)和
response
of
the
error
amplifier.
The
1-mV
ac
voltage
source
between
the
nodes
a
and
b
effectively
breaks
the
电容Coea (20.7 pF)用以模拟误差信号放大器的开环增益和频率响应。节点a和b之间、电压值为1mV的交流电压源有效的破坏
control loop for the frequency response measurements. Plotting a/c and c/b show the small signal responses of
了频率响应测量的控制回路。
处的波形图分别显示的是功率级及频率补偿的小信号响应。
处的波形图显示的时整个
a/c与c/b
a/bsignal
the power stage and frequency
compensation
respectively. Plotting a/b shows the small
response of the
a
current
source with the
overall loop. The dynamic loop response can be checked by replacing the RL with
回路的小信号响应。通过使用一个在时域分析中具有适当的阶跃幅度和步进率的电流源来替代
，可实现对动态回路响应的检
RL
appropriate load step amplitude and step rate in a time domain analysis.
验。
PH
VOUT
Power�Stage
16 A/V
a
b
c
0.8 V
R3 Coea
C2
R1
RESR
VSENSE
CO
COMP
C1
Roea
gm
1300 �A/V
RL
R2
Figure 30. Small
Model for Loop Response
图30.Signal
回路响应的小信号模型
Simple Small Signal Model for Peak Current Mode Control
峰值电流模式控制的简化小信号模型
Figure 31 is a simple small signal model that can be used to understand how to design the frequency
图31是一个简化的小信号模型，可用来理解如何设计频率补偿。该器件的功率级可近似等效为一个向输出电容和负载电阻
compensation.
The device power stage can be approximated to a voltage controlled current source (duty cycle
modulator)
supplying
current to the output capacitor and load resistor. 10
The
control to output transfer function is
提供电流的电压控制的电流源（占空比调制器）。对输出传输函数的控制如等式
所示，由一个直流增益、一个主极点和一个
shown in Equation 10 and consists of a dc gain, one dominant pole and one ESR zero. The quotient of the
零点等效串联电阻(ESR)组成。开关电流的变化值与COMP引脚电压（图30的节点c）的变化值之商，即为功率级跨导(gmps)，
change in switch current and the change in COMP pin voltage (node c in Figure 30) is the power stage
对于该器件而言
的值为
gmps(gm
A/V。is 16 A/V for the device. The DC gain of the power stage is the product of gmps
which
transconductance
ps) 16
and the load resistance (RL) as shown in Equation 11 with resistive loads. As the load current increases, the DC
的乘积，如等式
gain当具有电阻性负载时，功率级的直流增益等于
decreases. This variation with load may gmps
seem与负载电阻
problematic
first glance, but
fortunately the dominant pole
(RL)at
11所示。随着负载电流的增大，直流
moves
with
load
current
(see
Equation
12).
The
combined
effect
is
highlighted
by
the dashed line in Figure 32.
增益将不断减小。由负载引起的这一变化最初看来似乎是有些问题的，但好在主极点也将随着负载电流的变化而改变（见等式
As the load current decreases, the gain increases and the pole frequency lowers, keeping the 0-dB crossover
）。其综合影响用虚线在图
中做了突出标记。
12
frequency
the same for the32varying
load conditions which makes it easier to design the frequency compensation.
由于负载电流减小，增益将增加并且极点频率将降低，使得负载条件发生变化时，交叉频率将保持在0-dB不变，通过这种
方式能够简化频率补偿设计。
18
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VOUT
VOUT
VC
VC
RESR
RESR
gm ps
gm ps
RL
RL
CO
CO
Figure
Signal
图31.Small
峰值电流模式控制的简化小信号模型
Figure 31.
31. Simplified
Simplified
Small
Signal Model
Model for
for Peak
Peak Current
Current Mode
Mode Control
Control
VOUT
VOUT
Adc
Adc
VC
VC
RESR
RESR
gm ps
gm ps
RL
RL
fp
fp
CO
CO
fz
fz
图32. 峰值电流模式控制的简化频率响应
Figure
Figure 32.
32. Simplified
Simplified Frequency
Frequency Response
Response for
for Peak
Peak Current
Current Mode
Mode Control
Control
��
��1+
1+ 2�
VOUT
VOUT = Adc � �� 2�
= Adc � �
VC
VC
��1+
��1+ 2�
� 2�
Adc
=
gm
�
R
Adc = gmps � RL
ps
s
s
�
�
s
s
�
�
��
��
�
z
� z ��
��
��
�
p ��
�p
(10)
(10)
(11)
(11)
L
1
1
�
�p
p=
= C � R � 2�
O
CO � RLL � 2�
1
1
�
�z
z=
= C � R
O
ESR
CO � RESR �
� 2
2�
�
(12)
(12)
(13)
(13)
Where
Where
这里 gmea is the GM amplifier gain ( 1300µA/V)
gmea is the GM amplifier gain ( 1300µA/V)
是is
放大器增益
gm
the
power stage
(16A/V).
GM
( 1300gain
µA / V)
gm
gmeaps
ps is the power stage gain (16A/V).
R
the
是功率级增益
(16A / V)
gm
RLpsis
is
the load
load resistance
resistance
L
the output capacitance.
O is
RC
CL是负载电阻
O is the output capacitance.
is
R
是输出电容
is the
the equivalent
equivalent series
series resistance
resistance of
of the
the output
output capacitor.
capacitor.
CROESR
ESR
RESR是输出电容器的等效串联电阻
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19
19
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TPS54620
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TPS54620
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620
Small Signal Model for Frequency Compensation
频率补偿的小信号模型
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TPS54620
The
device
uses
a transconductance
amplifier
for the error所示的两个常用的频率补偿电路。在
amplifier and readily supports two类型中，通过加入一
of the commonly
Small
Signal
Model
for Frequency
Compensation
该器件采用跨导放大器作为误差信号放大器，轻松支持如图
ZHCS004–2009年5月
33
2A
SLVS949 – MAY 2009 ........................................................................................................................................................................................................ www.ti.com
used frequency
compensation
circuits shown
in Figure 33. In Type 2A, one additional high frequency pole is
Small
Signal Model
for Frequency
Compensation
个额外的高频极点来降低高频噪声。
Signal Model
fordevice
Frequency
Compensation
The
uses a high
transconductance
amplifier for the error amplifier and readily supports two of the commonly
added
to attenuate
frequency noise.
The
uses
a transconductance
forand
thereadily
error
supportshigh
two frequency
of the commonly
Small
Signal
Model
for for
Frequency
Compensation
useddevice
frequency
compensation
circuits
shown
in
Figure
33. amplifier
In Type and
2A,
one
additional
pole is
ice uses a transconductance
amplifier
the
erroramplifier
amplifier
supports
two readily
of the
commonly
The 下面的设计准则提供给那些选择使用一般方法来进行频率补偿的高级用户。所给出的逐步的设计过程在应用部分同样有可能被
design
guideline
are
provided
for inadvanced
users
who 2A,
prefer
compensate
using the general
used
frequency
compensation
circuits
shown
Figure
33.
In Type
onetoadditional
pole is
added
to attenuate
highbelow
frequency
noise.
quency compensation
circuits
in Figure
33.
In Type
additional
high
frequency
pole high
is frequency
The
device
uses
a shown
transconductance
amplifier
for2A,
theone
error
and
readilymay
supports
of the commonly
method.
The
step-by-step
design procedure
described
in
the amplifier
application
section
also betwo
used.
added
to
attenuate
high
frequency
noise.
用到。
o attenuate high
noise.
used
frequency
compensation
circuits
shown
Figure 33.
In Type
onetoadditional
high using
frequency
pole is
Thefrequency
design
guideline
below are
provided
for inadvanced
users
who 2A,
prefer
compensate
the general
The
design
guideline
below
are
provided
for
advanced
users
who
prefer
to
compensate
using
the
general
added
to
attenuate
high
frequency
noise.
method.
The
step-by-step
design
procedure
described
in
the
application
section
may
also
be
used.
VOUT
ign guideline below are provided for advanced users who prefer to compensate using the general
method.
The procedure
step-by-step
design procedure
described
in themay
application
section may also be used.
The step-by-step
design
described
in
the application
section
used.
The design
guideline below
are
provided
for advanced
usersalso
whobeprefer
to compensate using the general
VOUT
R1
method. The step-by-step design
procedure
VSENSEdescribed in the application section may also be used.
VOUT
VOUT
R1
R2
Type 2B
COMP Type 2A
R1
VSENSE
VOUT
R1
Type 2B
COMP Type 2A
Vref
VSENSE
VSENSE
R3 2B
Type C2
2A
Type
gm ea
R3
COMP
R2
Type
2A
Type 2B
R1 COMP
VSENSE
Vref
Type C2
2A
R3 2B
Type
C1
COMP
gm ea
Roea
Coea R3
Vref
R2
Vref
C1 C2
R3
gm
R3
ea
R3
R2
gm ea
C1
Vref R3 C2
Roea
Coea
R3
C1 C2
C1
gm
R3
ea
Roea
Coea
R2 Coea
C1
RoeaFigure
C1
33. Types
of
Frequency
Compensation
C1
C1
图33.Roea
频率补偿的不同类型
Coea
Figure 33. Types of FrequencyC1
Compensation
The general design guidelines for
device33.
loop
compensation
are as
follows
Types
of Frequency
Compensation
器件回路补偿的一般设计准则如下：
Figure 33. Types of Figure
Frequency
Compensation
1. Determine
the crossover
fcloop compensation are as follows
The
general design
guidelinesfrequency
for
device33.
Figure
Types of Frequency Compensation
1.2.确定交叉频率
fcdetermined
can be
byfrequency
The
general
guidelines
for devicefc
loop
are as follows
1. R3
Determine
the crossover
eral design guidelines
fordesign
device
loop compensation
are
ascompensation
follows
可由下式计算得到
2.
R3
�
�
�
�
�
2
c
VOUT
Co
1.
the
crossover
The
general
design
for devicefcloop compensation are as follows
2. Determine
R3
determined
byfrequency
R3can
= be
ermine the crossover
frequency
fcguidelines
gm
�
Vref
�
gm
2.
R3
can
be
determined
by
ea
� �crossover
� ps
c � VOUTfrequency
Co
1. Determine
fc
an be determined
by = 2� the
R3
�
�
�
�
�
2
c
VOUT
Co
gm
�
Vref
�
gm
R3
can
be
determined
by
�
2� � � c �2. VOUT
Co
ea
ps
R3 =
Where
=
gm�ea� c� �Vref
� gm
ps
�
�
2
VOUT
Co
gmea � Vref R3
� gm
ps is the GM amplifier gain ( 1300µA/V)
= ea
gm
这里Where
gmea � Vref � gmps
(14)
(14)
Where
gmps is
the power
stage gain (16A/V).
re
amplifier
gm
ea is the GM
放大器增益
gmea是GM
( 1300
µA / V) gain ( 1300µA/V)
Vref
is
the
reference
voltage
gm
is
GM
amplifier
gain(0.8V)
( 1300µA/V)
Where
gmea
is the
the
power
stage
gain
(16A/V).
psgain
gmea is the GM
( 1300µA/V)
是功率级增益
(16A
/ V)
gmpsamplifier
�
�
gm
is
the
power
stage
gain
(16A/V).
1
ps
Vref
isis the
reference
voltage
gm
the
GM amplifier
gain(0.8V)
( 1300µA/V)
gmps is the power
stage
gain
(16A/V).
ea
� �p =
�
Vref是参考电压
(0.8V)
Vref
is
the
reference
voltage
(0.8V)
CO � R1L � 2� � .
gm
is the
power stage
gain
Vref is the reference
voltage
(0.8V)
3. Place
apscompensation
zero at
the(16A/V).
dominant pole �
� �p =
�
1
Vrefbe
is determined
the reference
� the(0.8V)
C1 can
byvoltage
。
1 pole � ��p = CO � RL � 2� � .
3.3.替换一个补偿零点，在主极点处
Place
a compensation
zero
at
dominant
�
p
=
�
CO � R1L � 2� � .
� �
� Co
3.C1Place
aR
compensation
CO � RLpole
� 2�
� the dominant
C1
can
determined
by
由下式计算得到
e a compensation
zero
dominant zero
pole at
C1
= atbeLthe
� ��p. =
�
CO � RL � 2� � .
R3
C1bycana R
be
determined zero
by at the dominant pole �
3. Place
compensation
an be determined
L � Co
C1 = R � Co
C2 can
is optional.
It can be
determined
byused to cancel the zero from the ESR (Equivalent Series Resistance)
RL � Co 4. C1
C1
= beL R3
=
capacitor
Co.
RL R3
� Co
4. C2
It can be used to cancel the zero from the ESR (Equivalent Series Resistance)
R3
(15)
C1is=optional.
R
�ItCo
ESR
4.
C2
is
optional.
can
be
used
to
cancel
the
zero
from
the
ESR
(Equivalent
Series
Resistance)
capacitor
Co.
R3
C2
=
s optional. It can be used to cancel the zero from the ESR (Equivalent Series Resistance) of the output
R3� Co
capacitor
Co.
是可选择的。它能用来消除产生自输出电容器
RESR
4.
Co的
ESR（串联等效电阻）的零点。
acitor Co.
4.C2C2
It can be used to cancel the
zero
from the ESR (Equivalent Series Resistance)
C2is =optional.
R
�
Co
ESR
Co.
R3
RESR � Co capacitor
C2
=
=
R R3� Co
R3
(16)
C2 = ESR
R3
20
20
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(14)
(14)
(14)
(15)
of the output
(15)
(15)
of the output
of the output
(15)
(16)
of the output
(16)
(16)
(16)
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产品文件夹链接：TPS54620
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Copyright © 2009, Texas Instruments Incorporated
Copyright © 2009, Texas Instruments Incorporated
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s)
:TPS54620
Copyright
© 2009, Texas Instruments Incorporated
TPS54620
TPS54620
ZHCS004–2009年5月
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APPLICATION
INFORMATION
应用信息
设计指南
— 逐步的设计过程
Design Guide
– Step-By-Step Design Procedure
This这个例子详细描述了使用陶瓷输出电容如何进行高频开关调节器的设计。有几个参数必须首先了解，以便开始设计过程。
example details the design of a high frequency switching regulator design using ceramic output capacitors.
A few parameters must be known in order to start the design process. These parameters are typically determined
这些参数通常确定在系统级。在此示例中，我们先从以下这些已知的参数开始：
at the system level. For this example, we start with the following known parameters:
参数
Parameter
输出电压
Output Voltage
输出电流
Output Current
瞬态响应1A的负载阶跃
Transient Response
输入电压 1A load step
Input Voltage
输出电压纹波
数值
Value
3.3 V
3.3 V
6A
6A
ΔVout = 5 %
ǻVout
12 V的标准值, 8=V5到%
17 V之间
12 V nominal,
8 V to 17 V
33 mV p-p
启动输入电压（上升的
Output Voltage Ripple
Vin）
启动输入电压（下降的
Vin）
Start
Input Voltage (Rising
Vin)
Stop Input 开关频率
Voltage (Falling Vin)
33
mV V
p-p
6.528
6.190 VV
6.528
480
kHzV
6.190
Switching Frequency
480 kHz
Typical Application Schematic
典型应用示意图
The我们开发出如图
application schematic
of Figure 34 was developed to meet
the requirements
above. This circuit is available
34的应用示意图以满足上述要求。该电路可作为
TPS54620EVM
– 374的评估板。设计过程将在本章中给
as the TPS54620EVM-374 evaluation module. The design procedure is given in this section.
出。
Figure 34.图
Typical
Application Circuit
34. 典型应用电路
Operating Frequency
工作频率
The第一步是为调节器决定一个开关频率。需要在高开关频率与低开关频率间做一个折中。
first step is to decide on a switching frequency for the regulator. There is a trade off between higher and
lower switching frequencies. Higher switching frequencies may produce smaller a solution size using lower
valued inductors and smaller output capacitors compared to a power supply that switches at a lower frequency.
与具有较低开关频率的电源相比，通过使用更廉价的电感器和更小的输出电容器，使得具有较高开关频率的电源设计会得
However, the higher switching frequency causes extra switching losses, which hurt the converter’s efficiency and
到更小尺寸的解决方案。然而，较高的开关频率会造成额外的开关损耗，这将损害转换器的效率和热性能。本设计中，我们选
thermal performance. In this design, a moderate switching frequency of 480 kHz is selected to achieve both a
small solution size and a480kHz
high efficiency
operation.
择了一个适中的开关频率，
，能同时实现小尺寸的解决方案和高效率的工作状态。
Output Inductor Selection
输出电感的选择
To calculate the value of the output inductor, use Equation 17. KIND is a coefficient that represents the amount
利用等式17
可计算输出电感值。
KIND
of inductor
ripple
current relative
to 是一个系数，表示相对于最大输出电流的电感纹波电流总量。电感纹波电流能被输出
the maximum output current. The inductor ripple current is filtered by the
电容器滤掉。因此，选择高电感纹波电流将影响对输出电容器的选择，这是因为输出电容器必须具有一个等于或大于电感纹波
output capacitor. Therefore, choosing high inductor ripple currents impact the selection of the output capacitor
since the output capacitor must have a ripple current rating equal to or greater than the inductor
ripple current. In
电流的纹波电流等级。一般情况下，电感纹波值由设计者自行设置；然而对于绝大多数的应用来说，
KIND的值通常在0.1至0.3
general, the inductor ripple value is at the discretion of the designer; however, KIND is normally from 0.1 to 0.3
之间。
for the majority of applications.
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5月 ........................................................................................................................................................................................................
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2009
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Vinm ax � Vout
Vout
ax � Vout �
Vout
L1 � Vinm
ax
� Vout � VinmVout
L1 � Vinm
Io
�
Kind
� f sw
L1 �
� Vinm ax
Io � Kind
ax � f sw
Io � Kind
Vinm ax � f sw
(17)
(17)
(17)
For this design example, use KIND = 0.3 and the inductor value is calculated to be 3.08 uH. For this design, a
For
this
design
use
=
0.3
and
the inductor
value
is
to
uH. For
this
design,
a
对于本设计样例，取
。因而在这一设计中，我们选择了一个最接近标准值的电
= KIND
0.3，计算得到的电感值为
3.08 uH
For
this standard
design example,
example,
use
KIND
=3.3
0.3
and
value
is calculated
calculated
to be
be 3.08
3.08
this
design,
a
nearest
valueKIND
was
chosen:
uH.
Forthe
theinductor
output
filter
inductor,
it is important
thatuH.
theFor
RMS
current
and
nearest
standard
value
was
chosen:
3.3
uH.
For
the
output
filter
inductor,
it
is
important
that
the
RMS
current
and
nearest
standard
was
3.3 uH. The
For the
output
filter inductor,
itcurrent
is important
the和峰值电感电流可从
RMSEquation
current and
saturation
currentvalue
ratings
notchosen:
be exceeded.
RMS
and peak
inductor
can bethat
found
from
19
感：
。对于输出滤波器电感，重要的一点是其电流不能超过均方根
电流和饱和额定电流。
3.3
uH
(RMS)
RMS
saturation
current
ratings
saturation
current
ratings not
not be
be exceeded.
exceeded. The
The RMS
RMS and
and peak
peak inductor
inductor current
current can
can be
be found
found from
from Equation
Equation 19
19
and Equation
20.
等式
和 等式20
中计算得到。
and
Equation
20.
19
and Equation 20.
Vinmax � Vout
Vout
� Vout �
Vout
Iripple � Vinmax
Vinmax
Vout� f sw
Iripple
L1� Vout �� Vinmax
Iripple �
�
(18)
L1
Vinmax
(18)
L1
Vinmax �� ff sw
sw
(18)
2
2
�
�
V
Vinmax
Vo
�
�
1 � Vo � ��Vinmax � Vo �� �2
2
ILrms � Io2 � 11 � � Vo � �Vinmax � Vo � �
o
ILrms
�� � Vinmax
� L1� f sw ��
ILrms �
Io2 �
� Io
� 12
�
12
(19)
Vinmax �� L1
L1�� ff sw
sw ��
12 �� Vinmax
(19)
(19)
Iripple
ILpeak � Iout � Iripple
Iripple
ILpeak
�
Iout
�
(20)
ILpeak � Iout � 2
2
(20)
2
(20)
For this design, the RMS inductor current is 6.02 A and the peak inductor current is 6.84 A. The chosen inductor
For
this
design,
the
RMS
inductor
current
is
6.02
A
and
the
peak
inductor
current
is
6.84
A.
The
chosen
inductor
Fora this
design,
the RMSseries
inductor
is 6.02
A and thecurrent
peak inductor
current
6.84aA.RMS
The current
chosen rating
inductor
is
Coilcraft
MSS1048
3.3current
uH. It has
a saturation
rating of
7.38 Ais and
of
is
MSS1048
is a
a Coilcraft
Coilcraft
MSS1048 series
series 3.3
3.3 uH.
uH. It
It has
has a
a saturation
saturation current
current rating
rating of
of 7.38
7.38 A
A and
and a
a RMS
RMS current
current rating
rating of
of
7.22
A.
7.22
A.
RMS电感电流为6.02 A而峰值电感电流为6.84 A。所选用的电感器是Coilcraft MSS1048系列3.3 uH的电感。它
7.22本设计中，
A.
The 7.38
current
flowing through7.22
theAinductor
is the inductor ripple current plus the output current. During power up,
具有
的RMS额定电流值。
A的饱和额定电流值及
The
current
flowing
through
the
is
inductor
ripple
current
plus
output current.
During power
up,
The
flowingload
through
the inductor
inductor
is the
the current
inductorcan
ripple
currentabove
plus the
the
current.
power
up,
faultscurrent
or transient
conditions,
the inductor
increase
the output
calculated
peakDuring
inductor
current
faults
or
transient
load
conditions,
the
inductor
current
can
increase
above
the
calculated
peak
inductor
current
faults
or transient
load conditions,
inductor the
current
can current
increasecan
above
the calculated
level calculated
above.
In transient the
conditions,
inductor
increase
up to the peak
switchinductor
current current
limit of
当前流经电感器的是电感纹波电流与输出电流的叠加值。在启动、故障或瞬态负载条件下，电感电流能增加并超过前面计
level
calculated
above. In
conditions,
the
current
can increase
up
switch current
limit
level
calculated
In transient
transient
conditions,
the inductor
inductor
current
increase
up to
to the
the
current current
limit of
of
the device.
For above.
this reason,
the most
conservative
approach
is to can
specify
an inductor
withswitch
a saturation
the
device.
For
this
reason,
the
most
conservative
approach
is
to
specify
an
inductor
with
a
saturation
current
算所得到的峰值电感电流等级。在瞬态条件下，电感电流还可能提高到器件开关电流的限制值。出于这个原因，最保守的办法
the
device.
reason,
conservative
is the
to specify
an inductor
with a saturation current
rating
equal For
to orthis
greater
thanthe
themost
switch
current limitapproach
rather than
peak inductor
current.
rating
rating equal
equal to
to or
or greater
greater than
than the
the switch
switch current
current limit
limit rather
rather than
than the
the peak
peak inductor
inductor current.
current.
是指定一个电感，使它的饱和额定电流值要等于或大于开关电流限制值，而不是峰值电感电流。
Output Capacitor Selection
Output
Output Capacitor
Capacitor Selection
Selection
输出电容的选择
There are three primary considerations for selecting the value of the output capacitor. The output capacitor
There
are
three
primary
for selecting
the
value
of
the
output
The output
capacitor
There
are three
primary considerations
considerations
selecting
the and
value
of the
the regulator
output capacitor.
capacitor.
capacitor
determines
the modulator
pole, the outputforvoltage
ripple,
how
responds The
to a output
large change
in
determines
the
modulator
pole,
the
output
voltage
ripple,
and
how
the
regulator
responds
to
a
large
change
选择输出电容器的电容值时，有三个主要的考虑因素。输出电容决定了调节器的极值、输出电压纹波，以及对于负载电流
determines
pole, the output
ripple, and
how
responds
to athree
largecriteria
change in
in
load
current.the
Themodulator
output capacitance
needs voltage
to be selected
based
on the
the regulator
more stringent
of these
load
load current.
current. The
The output
output capacitance
capacitance needs
needs to
to be
be selected
selected based
based on
on the
the more
more stringent
stringent of
of these
these three
three criteria
criteria
的较大变化调节器将应如何响应。需要基于以下三个更为严格的标准来选择输出电容：
The desired response to a large change in the load current is the first criteria. The output capacitor needs to
The
desired
response
to
change in
load
current
is the
criteria.
The
capacitor
needs to
The
desired
response
to a
a large
large
in the
the can
loadnot.
current
the first
firstwould
criteria.
Theif output
output
capacitor
to
supply
the load
with current
whenchange
the regulator
This issituation
occur
there are
desiredneeds
hold-up
supply
the
load
with
current
when
the
regulator
can
not.
This
situation
would
occur
if
there
are
desired
hold-up
对于负载电流的较大变化应得到所期望的响应，是第一个准则。当调节器不能提供负载电流时，输出电容应能提供。当调
supply
thethe
loadregulator
with current
when
regulator
can not.
would
occur above
if thereaare
desired
hold-up
times for
where
the the
output
capacitor
mustThis
holdsituation
the output
voltage
certain
level
for a
times
for
the
where the
output
capacitor
must
the output
above
level for
节器需要具有一个期望的滞留时间时，这种情况将会发生，即在输入功率消失以后，输出电容必须在一段特定的时间内将输出
times
for amount
the regulator
regulator
the input
outputpower
capacitor
must hold
hold
outputisvoltage
voltage
above a
a certain
certain
for a
a
specified
of timewhere
after the
is removed.
The the
regulator
also temporarily
not ablelevel
to supply
specified
amount
of
time
after
the
input
power
is
removed.
The
regulator
is
also
temporarily
not
able
to
supply
specified
of timeifafter
power
removed.
regulator
is also
notas
able
to supply
sufficient amount
output current
therethe
is input
a large,
fast isincrease
in The
the current
needs
of temporarily
the load such
transitioning
电压保持在某一电平上。如果从负载处产生一个大的、快速增加的电流需求，比如从空负载到满负载的转换过程，则调节器同
sufficient
output
current ifif there
is
fast
in
current
needs
of
load
such
transitioning
sufficient
output
is a
a large,
large,
fast increase
increase
in the
the
current
needs
of the
the
loadcontrol
such as
as
from no load
to acurrent
full load.there
The regulator
usually
needs two
or more
clock
cycles
for the
looptransitioning
to see the
from
no
load
to
a
full
load.
The
regulator
usually
needs
two
or
more
clock
cycles
for
the
control
loop
see
样在短时间内无法提供足够的输出电流。调节器的控制回路通常需要两个或两个以上的时钟周期，才能检测到负载电流及输出
from
no in
load
tocurrent
a full load.
regulator
needs
moretoclock
the control
loop to
tocapacitor
see the
the
change
load
and The
output
voltage usually
and adjust
thetwo
dutyorcycle
reactcycles
to thefor
change.
The output
change
in
load
current
and
output
voltage
and
adjust
the
duty
cycle
to
react
to
the
change.
The
output
capacitor
change
load to
current
and
adjust
dutythe
cycle
to react
the change.
The
output
capacitor
电压的变化并通过调整占空比来对变化做出反应。输出电容必须设计为能够提供额外的电流给负载，直到控制回路对负载变化
must beinsized
supply
theoutput
extravoltage
currentand
to the
loadthe
until
control
loop toresponds
to the
load
change.
The
must
be sized
the
extra
current
the
until
loop
to
load
change.
The
must
sized to
to supply
supply
thelarge
extraenough
currenttoto
tosupply
the load
load
until the
the control
control
loopforresponds
responds
to the
the while
load only
change.
The
outputbe
capacitance
must be
the difference
in current
2 clock cycles
allowing
做出响应为止。输出电容必须足够大，以保证在只允许输出电压下降至一个可容忍的量值这样的条件下，它还能在
2个时钟周期
output
capacitance
must
be
large
enough
to
supply
the
difference
in
current
for
2
clock
cycles
while
only
allowing
output
capacitance
must
be large
to supply
the difference
in current
for 2 clock
cycles
while only
allowing
a tolerable
amount of
droop
in the enough
output voltage.
Equation
21 shows
the minimum
output
capacitance
necessary
a
tolerable amount
of droop
内提供差电流。等式
a
amount
droop in
in the
the output
output voltage.
voltage. Equation
Equation 21
21 shows
shows the
the minimum
minimum output
output capacitance
capacitance necessary
necessary
totolerable
accomplish
this.21of给出了为了达到这一点所需的最小输出电容值。
to
accomplish
this.
to accomplish2 this.
� �Iout
Iout
Co � 22 �� �
�� �
Iout
Co
Vout
� ff sw
Co �
(21)
�
�
sw
(21)
f sw � �Vout
Vout
(21)
Where ǻIout is the change in output current, Fsw is the regulators switching frequency and ǻVout is the
Where
ǻIout
is
the
change
in
output
current,
Fsw
is
the
regulators
switching
frequency
and
ǻVout
is
the
这里Δ
是输出电流的改变量，
是输出电压改变量的允许值。在这个例子中，我们预先
Where
ǻIout
is the
in output
current,
is theVout
regulators
switching
frequency
and ǻVout
the
Iout
Fsw是调节器的开关频率，Δ
allowable
change
in change
the output
voltage.
For thisFsw
example,
the
transient
load response
is specified
as is
a 5%
allowable
change
in
the
output
voltage.
For
this
example,
the
transient
load
response
is
specified
as
a
5%
allowable
change
in
the
output
voltage.
For
this
example,
the
transient
load
response
is
specified
as
a
5%
change
in
Vout
for
a
load
step
of
1A.
For
this
example,
ǻIout
=
1.0
A
and
ǻVout=
0.05
x
3.3
=
0.165
V.
Using
设定瞬态负载响应为
变化，当每一个负载阶跃值为
5%的
Voutstep
1A时。因此本例中Δ
Iout ǻVout=
= 1.0A，Δ
Vout=
0.05= x0.165
3.3 = V.
0.165 V。
change
in
for
1A.
ǻIout
=
A
0.05
x 3.3
change
in Vout
Vout gives
for a
a aload
load
step of
ofcapacitance
1A. For
For this
thisofexample,
example,
ǻIout
= 1.0
1.0
A and
and
0.165 capacitor
V. Using
Using
these
numbers
minimum
25 µF. This
value
does
not ǻVout=
take the 0.05
ESRxof3.3
the=output
these
numbers
gives
a
minimum
capacitance
of
25
µF.
This
value
does
not
take
the
ESR
of
the
output
capacitor
通过这些值可以得到最小电容值为
。这个值并没有把输出电容的
25 capacitance
µF
ESR计算到输出电压改变量中去。对于陶瓷电容器，
ESR
theseaccount
numbers
gives
a minimum
25 µF. This
value
does
not take
the ESR
of the
output
into
in the
output
voltage
change.
Forofceramic
capacitors,
the ESR
is usually
small
enough
to capacitor
ignore
in
into
account
in
the
output
voltage
change.
For
ceramic
capacitors,
the
ESR
is
usually
small
enough
to
ignore
in
into
account
in
the
output
voltage
change.
For
ceramic
capacitors,
the
ESR
is
usually
small
enough
to
ignore
in
通常非常小，在这一计算中可忽略不计。
this calculation.
this
calculation.
this calculation.
Equation 22 calculates the minimum output capacitance needed to meet the output voltage ripple specification.
Equation
calculates the
output capacitance
needed
to
meet
the
voltage
ripple
specification.
等式2222
计算的是满足输出电压纹波规格所需的最小输出电容。这里
是最大可允许输出电压纹波，
fsw
Vripple
Equation
22
the minimum
minimum
capacitance
needed
to是开关频率，
meet output
the output
output
voltage
ripple
Where fsw
iscalculates
the switching
frequency,output
Vripple
is the maximum
allowable
voltage
ripple,
and specification.
Iripple is the
Where
fsw
is
the
switching
frequency,
Vripple
is
the
maximum
allowable
output
voltage
ripple,
and
Iripple
是电感器的纹波电流。在这种情况下，最大输出电压纹波是
。根据这一要求，等式
。 is
Where
fsw
is thecurrent.
switching
is the maximum
allowable
output
voltage
ripple, this
and
Iripple
is the
the
Iripple
33mVvoltage
22的计算结果为
13.2uF
inductor
ripple
In frequency,
this case, Vripple
the maximum
output
ripple
is 33mV.
Under
requirement,
inductor
ripple
current.
In
this
case,
the
maximum
output
voltage
ripple
is
33mV.
Under
this
requirement,
inductor
current.
In this case, the maximum output voltage ripple is 33mV. Under this requirement,
Equation ripple
22 yields
13.2uF.
Equation
Equation 22
22 yields
yields 13.2uF.
13.2uF.
22
22
22
22
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Copyright © 2009, 版权所有：德州仪器
Texas Instruments Incorporated
© 2009
Copyright © 2009, Texas Instruments Incorporated
Copyright © 2009, Texas Instruments Incorporated
TPS54620
TPS54620
TPS54620
ZHCS004–2009
5月
www.ti.com.cn
www.ti.com ........................................................................................................................................................................................................ SLVS949
– MAY 年
2009
www.ti.com ........................................................................................................................................................................................................
........................................................................................................................................................................................................ SLVS949
SLVS949 –
MAY 2009
2009
www.ti.com
– MAY
Co �
Co � 8 �
8�
1
11
1 �
�
f sw Voripple
f sw Voripple
Iripple
Iripple
(22)
(22)
(22)
Equation
calculates the maximum ESR an output capacitor can
have to 23
meet
the output
ripple
等式 2323
计算的是满足输出纹波规格的、一个输出电容能具有的最大
中可以看出，
应该不到
ESR 。从等式
ESRvoltage
19.7
Equation
23
calculates the maximum ESR an output capacitor can
have to meet
the output
voltage
ripple
specification. Equation 23 indicates the ESR should be less than 19.7 mOhm. In this case, the ceramic caps’
specification.
Equation
23
indicates
the
ESR
should
be
less
than
19.7
mOhm.
In
this
case,
the
ceramic
caps’
。在这种情况下，陶瓷电容器的
将远远小于
。
mOhm
ESR
19.7 mOhm
ESR
ESR is
is much
much smaller
smaller than
than 19.7
19.7 mOhm.
mOhm.
Voripple
Resr
Resr �
� Voripple
Iripple
(23)
Iripple
(23)
(23)
Additional
capacitance
de-ratings
for
aging,
temperature
and
DC
bias
should
be
factored
in
which
increases
Additional
capacitance de-ratings for aging, temperature and DC bias should be factored in which increases this
this
老化、温度及直流偏置所带来的额外的电容额定值下降，也应该做为增加这一最小值的考虑因素。在这个例子中，我们使
minimum
value. For this example, a 47 µF 6.3V X5R ceramic capacitor with 3 milliohms of ESR is be used.
minimum value. For this example, a 47 µF 6.3V X5R ceramic capacitor with 3 milliohms of ESR is be used.
用了一个
、ESR为
Capacitors
generally
limits
to the 的陶瓷电容器。电容器一般用来限制它们所能处理的纹路电流值而不会失败或产生
amount of ripple current they can handle without failing or producing
47 µF
6.3V X5Rhave
3 milliohms
Capacitors
generally
have
limits
to the amount of ripple current they can handle without failing or producing
excess
capacitor
excess heat.
heat. An
An output
output capacitor
capacitor that
that can
can support
support the
the inductor
inductor ripple
ripple current
current must
must be
be specified.
specified. Some
SomeRMS
capacitor
过多热量。一个能够支持电感纹路电流的输出电容器必须对其进行指定。有些电容的数据表给定了最大纹波电流的
（均方
data
sheets
specify
the
RMS
(Root
Mean
Square)
value
of
the
maximum
ripple
current.
Equation
24
can
be
used
data
sheets
specify
the
RMS
(Root
Mean
Square)
value
of
the
maximum
ripple
current.
Equation
24
can
be
used
根）值。等式
纹路电流。针对这一应用，等式
的计算结果为
。
485mA
to calculate 24
the可用于计算需要支持的输出电容的
RMS ripple current the outputRMS
capacitor
needs to support. For24
this
application,
Equation
24 yields
to calculate the RMS ripple current the output capacitor needs to support. For this application, Equation 24 yields
485mA.
485mA.
Vout
Vout �� ��Vinmax
Vinmax �
� Vout
Vout ��
Icorms
Icorms �
�
12
(24)
12 �� Vinmax
Vinmax �� L1
L1�� ff sw
sw
(24)
(24)
Input Capacitor Selection
Input Capacitor Selection
输入电容的选择
The TPS54620 requires a high quality ceramic, type X5R or X7R, input decoupling capacitor of at least 4.7 uF of
The TPS54620
TPS54620
requires a high
quality
ceramic, type X5R or X7R, input decoupling
capacitor
of at least 4.7 uF of
需要一个类型为
X5R或
X7R、高品质的陶瓷输入退耦电容器，放置在
PVIN输入电压和
Vin输入电压引脚上，且具有
effective
effective capacitance
capacitance on
on the
the PVIN
PVIN input
input voltage
voltage pins
pins and
and 4.7
4.7 uF
uF on
on the
the Vin
Vin input
input voltage
voltage pin.
pin. In
In some
some
applications
additional
may
also
不低于
输入还可能用到额外的大容量电容。有效电容包括了所有直流偏置的影响。输
4.7 uF的有效电容值。在一些应用中
PVIN
applications
additional bulk
bulk capacitance
capacitance
may
also be
be required
required for
for the
the PVIN
PVIN input.
input. The
The effective
effective capacitance
capacitance
includes any DC bias effects. The voltage rating of the input capacitor must be greater than the maximum input
includes any DC bias effects. The voltage rating of the input capacitor must
be greater
than the maximum input
入电容的额定电压必须大于最大输入电压。该电容所具有的纹波额定电流也必须大于
的最大输入纹波电流。输入纹波
TPS54620
voltage. The capacitor must also have a ripple current rating greater than the
maximum input current ripple of the
voltage.
The
capacitor
must
also
have
a
ripple
current
rating
greater
than
the
maximum
input
current ripple of the
电流的计算如等式
所示。
TPS54620.
input
TPS54620. The
The 25
input ripple
ripple current
current can
can be
be calculated
calculated using
using Equation
Equation 25.
25.
Vout �Vinmin � Vout �
Icirms � Iout � Vout � �Vinmin � Vout �
Icirms � Iout � Vinmin �
Vinmin
(25)
Vinmin
Vinmin
(25)
(25)
The value
value of
of a
a ceramic
ceramic capacitor
capacitor varies
varies significantly
significantly over
over temperature
temperature and
and the
the amount
amount of
of DC
DC bias
bias applied
applied to
to the
the
The
capacitor.
The
陶瓷电容器的容值受温度及施加在电容上的直流偏置量的影响，会发生很大的改变。由温度引起的电容值改变，可以通过
capacitor.
The capacitance
capacitance variations
variations due
due to
to temperature
temperature can
can be
be minimized
minimized by
by selecting
selecting a
a dielectric
dielectric material
material that
that
is stable over temperature. X5R and X7R ceramic dielectrics
are陶瓷介质常被选则作为电源调节器电容，这是因为它们
usually selected for power regulator capacitors
选择受温度影响较小的稳定介质材料来最大程度的予以消除。
X5R及X7R
is stable over temperature. X5R and X7R ceramic dielectrics
are usually selected for power regulator capacitors
because they have a high capacitance to volume ratio and are fairly stable over temperature. The output
because they have a high capacitance to volume ratio and are fairly stable over temperature. The output
具有较高的电容体积比，并且在温度影响下相当稳定。输出电容的选择也必须把直流偏置考虑进去。电容值随着直流偏置跨电
capacitor
capacitor must
must also
also be
be selected
selected with
with the
the DC
DC bias
bias taken
taken into
into account.
account. The
The capacitance
capacitance value
value of
of a
a capacitor
capacitor
decreases
design,
容的增加将不断降低。对于本设计样例，所需的陶瓷电容器应至少具有
的额定电压值，以支持最高输入电压。因此在设计
25Vexample
decreases as
as the
the DC
DC bias
bias across
across a
a capacitor
capacitor increases.
increases. For
For this
this
example
design, a
a ceramic
ceramic capacitor
capacitor with
with at
at
least a 25 V voltage rating is required to support the maximum input voltage. For this example, one 10 µF and
中，我们选用了一个
和一个
、额定电压为
的电容器并将它们并联在一起，这是因为
和
的输入连接在一
least a 25 V voltage
rating
is
required
to
support
the
maximum
input
voltage.
For
this
example,
one
10
µF
and
10 µF
uF
25 V
PVIN
one 4.7 uF 25 V capacitors
in4.7
parallel
have been
selected as the VIN and PVIN inputs VIN
are tied
together so the
one 4.7 TPS54620
uF 25 V 可由一个单一电源供电。输入电容值决定了调节器的输入电压纹波。输入电压纹波可由等式
capacitors in parallel have been selected as the VIN and PVIN inputs are tied together
so the
起，这样
26计算得到。使
TPS54620
voltage
TPS54620 may
may operate
operate from
from a
a single
single supply.
supply. The
The input
input capacitance
capacitance value
value determines
determines the
the input
input ripple
ripple
voltage of
of
the
voltage
can
calculated
using
example
用设计样例中的数值，
，并且输入纹波电流
Ioutmax=6
A, ripple
Cin=14.7
, Fsw=480
kHz，能够得到输入电压纹波为
213the
mVdesign
rms为
the regulator.
regulator. The
The input
input
voltage
ripple
canµFbe
be
calculated
using Equation
Equation 26.
26. Using
Using
the
design
example values,
values,
Ioutmax=6 A, Cin=14.7 µF, Fsw=480 kHz, yields an input voltage ripple of 213 mV and a rms input ripple current
Ioutmax=6
2.95
A。A. A, Cin=14.7 µF, Fsw=480 kHz, yields an input voltage ripple of 213 mV and a rms input ripple current
of 2.95
of 2.95 A.
Ioutmax � 0.25
�Vin
Vin �
� Ioutmax � 0.25
�
Cin
(26)
Cin �� ff sw
sw
(26)
(26)
Slow Start Capacitor Selection
慢启动电容的选择
Slow Start Capacitor Selection
The 慢启动电容决定了上电过程中，输入电压达到器预先设定的标称值所经历的最小时间。这将是非常有用的，如果负载需要
slow start capacitor determines the minimum amount of time it takes for the output voltage to reach its
The slow start capacitor determines the minimum amount of time it takes for the output voltage to reach its
nominal programmed value during power up. This is useful if a load requires a controlled voltage slew rate. This
nominal programmed
value
power up. This is useful if a load requires a controlled voltage slew rate. This
一个受控的压摆率
(voltage
slewduring
rate)。如果输出电容非常大，需要大量的电流用于对电容器快速充电并使其达到输出电压级
is
is also
also used
used ifif the
the output
output capacitance
capacitance is
is very
very large
large and
and would
would require
require large
large amounts
amounts of
of current
current to
to quickly
quickly charge
charge
时，这段时间将同样起作用。为电容器充电所需的大电流有可能使
达到电流的限定值，或者从输入电源得到的过多的
the
necessary
to
TPS54620
the capacitor
capacitor to
to the
the output
output voltage
voltage level.
level. The
The large
large currents
currents
necessary
to charge
charge the
the capacitor
capacitor may
may make
make the
the
TPS54620 reach the current limit or excessive current draw from the input power supply may cause the input
电流有可能引起输入电压轨的暂降。
TPS54620 reach the current limit or excessive current draw from the input power supply may cause the input
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Copyright © 2009, Texas
Incorporated
版权所有：德州仪器
©Instruments
2009
Copyright © 2009, Texas
Instruments
Incorporated
Copyright © 2009, Texas Instruments Incorporated
Product
Folder
产品文件夹链接：
TPS54620
Product
Folder Link(s)
Link(s) :TPS54620
:TPS54620
Product
Folder
Link(s)
:TPS54620
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23
23
23
23
TPS54620
TPS54620
年5月 ........................................................................................................................................................................................................
ZHCS004–2009
www.ti.com.cn
SLVS949
www.ti.com
SLVS949 –
– MAY
MAY 2009
2009 ........................................................................................................................................................................................................
www.ti.com
voltage
rail to
to sag.
sag. Limiting
Limiting the
the output
output voltage
voltage slew
slew rate
rate solves
solves both
both of
of these
these problems.
problems. The
The soft
soft start
start capacitor
capacitor
voltage
rail
限制输出电压的摆率能够解决这两个问题。通过等式
27 可计算出软启动电容值。对于本样例电路，软启动时间并不是那
value
value can
can be
be calculated
calculated using
using Equation
Equation 27.
27. For
For the
the example
example circuit,
circuit, the
the soft
soft start
start time
time is
is not
not too
too critical
critical since
since the
the
么重要，这是因为输出电容值是
，它不需要多大的电流就能够充电至
。我们把样例电路的软启动时间主观设定为
47 µF
3.3V
3.5
output
which
to
output capacitor
capacitor value
value is
is 47
47 µF
µF
which does
does not
not require
require much
much current
current
to charge
charge to
to 3.3
3.3 V.
V. The
The example
example circuit
circuit has
has
the，这样就需要一个
soft start
start time
time set
set
to的电容与之匹配。在
an arbitrary
arbitrary value
valueTPS54620
of 3.5
3.5 ms
ms
which
requires
a为
10
nF。capacitor.
capacitor. In
In TPS54620,
TPS54620, Iss
Iss is
is 2.3
2.3
中，
，Vref
ms
10 nF
Iss为2.3uA
0.8V
the
soft
to
an
of
which
requires
a
10
nF
uA and
and Vref
Vref is
is 0.8V.
0.8V.
uA
Tss((ms
ms)) �� Iss
Iss(( �
�A
A ))
Tss
C7
C7 �
�
Vref
(
V
)
Vref ( V )
(27)
(27)
Bootstrap Capacitor
Capacitor Selection
Selection
Bootstrap
自举电容的选择
A 0.1
0.1 uF
uF ceramic capacitor
capacitor must
must be
be connected
connected between
between the
the BOOT
BOOT to
to PH
PH pin
pin for
for proper
proper operation.
operation. It
It is
is
A
一个0.1 ceramic
uF的陶瓷电容器必须连接在
BOOT至
PH引脚之间以便进行正确操作。我们推荐使用一个
X5R或绝缘性更佳的陶瓷电
recommended
to use
use a
a ceramic
ceramic capacitor
capacitor
with
X5R or
or better
better grade
grade dielectric.
dielectric. The
The capacitor
capacitor
should have
have 10V
10V or
or
recommended
to
with
X5R
should
容器。该电容应具有
higher
10V或更高的额定电压。
higher voltage
voltage rating.
rating.
Under Voltage
Voltage Lockout
Lockout Set
Set Point
Point
Under
欠压锁定设置点
The
Under
(UVLO)
can
using
external
voltage
divider
network
of
and
The 通过改变外部分压器网络
Under Voltage
Voltage Lock
Lock Out
Out
(UVLO)
can be
be adjusted
adjusted
using the
the
voltage 的
divider
network
of R3
R3
and R4.
R4.
连接在TPS54620
引脚之间，
R3和
R4可对欠压锁定
(UVLO)进行调节。
R3external
VIN与EN
R4则连接在
R3 is
is connected
connected between
between VIN
VIN and
and the
the EN
EN pin
pin of
of the
the TPS54620
TPS54620 and
and R4
R4 is
is connected
connected between
between EN
EN and
and GND
GND ..
R3
与GND
之间。
具有两个门限值，一个当输入电压上升时作为上电的门限值，另一个当输入电压下降时作为掉电的门限
EN
The
UVLO
hasUVLO
two thresholds,
thresholds,
one for
for power
power up
up when
when the
the input
input voltage
voltage is
is rising
rising and
and one
one for
for power
power down
down or
or
The
UVLO
has
two
one
brown
outs
when
the
For
example
design,
值。对于本设计样例，一旦输入电压增加至超过了
启动或使能）时，电源将启动并开始进行转换。当调节器开始
6.528V
UVLO
brown outs when the input
input voltage
voltage is
is falling.
falling.
For（the
the
example
design, the
the supply
supply should
should turn
turn on
on and
and start
start
switching
6.528V
(UVLO
start
the
starts
switching once
once the
the input
input voltage
voltage increases
increases above
above6.190
6.528V
(UVLO
start or
or enable).
enable). After
After
the regulator
regulator
starts
进行转换以后，它将继续这一动作直到输入电压降至低于
停止或失效）时为止。等式
V（UVLO
2和等式
3可用于计算上限
switching, itit should
should continue
continue to
to do
do so
so until
until the
the input
input voltage
voltage falls
falls below
below 6.190
6.190 V
V (UVLO
(UVLO stop
stop or
or dissable).
dissable).
switching,
和下限电阻值。对于规定的停止电压，最接近标准的电阻值分别是：
R3为for
35.7the
kΩ，
R4为and
8.06 lower
kΩ。 resistor
Equation 2
2 and
and Equation
Equation 3
3 can
can be
be used
used to
to calculate
calculate the
the values
values
for
the
upper
and
lower
resistor values.
values. For
For the
the
Equation
upper
stop
voltages
specified
the
nearest
standard
resistor
value
for
R3
is
35.7
kŸ
and
for
stop voltages specified the nearest standard resistor value for R3 is 35.7 kŸ and for R4
R4 is
is 8.06
8.06 kŸ.
kŸ.
输出电压反馈电阻的选择
Output Voltage
Voltage Feedback
Feedback Resistor
Resistor Selection
Selection
Output
电阻分压网络R5及R6用于设置输出电压。对于本设计样例，我们选择R6的值为10 kOhm。通过等式28，可以计算得到R5
The
divder
R5
to
the
The resistor
resistor
divder nework
nework
R5 and
and R6
R6 is
is used
used的电阻值为
to set
set the
the output
output voltage.For
voltage.For
the example
example design,
design, 10
10 kOhm
kOhm was
was
的电阻值为
。最接近标准值误差不到
。
31.25
selected for
for
R6.kOhm
Using
Equation 28,
28, R5
R5 is
is 1%
calculated as
as31.6kOhm
31.25 kOhm.
kOhm.
The nearest
nearest standard
standard 1%
1% resistor
resistor is
is 31.6
31.6
selected
R6.
Using
Equation
calculated
31.25
The
kOhm.
kOhm.
Vo �
� Vref
Vref
Vo
R5
R6
R5 �
�
R6
Vref
(28)
Vref
(28)
Minimum
最小输出电压
Minimum Output
Output Voltage
Voltage
Due
to
internal
design
voltage.
的内部设计，对于任何给定的输入电压都具有一个最小的输入电压限制。输出电压绝不可能低于
的内部
Due出于
to the
the
internal
design of
of the
the TPS54620,
TPS54620, there
there is
is a
a minimum
minimum output
output voltage
voltage limit
limit for
for any
any given
given input
input
voltage.
TPS54620
0.8V
The
output
voltage
can
never
be
lower
than
the
internal
vlotage
reference
of
0.8
V.
Above
0.8
V,
the
ouyput
The
output
voltage
can
never
be
lower
than
the
internal
vlotage
reference
of
0.8
V.
Above
0.8
V,
the
ouyput
参考电压。输出电压需高于0.8V，但还有可能受到最小可控开通时间的限制。在这种情况下，最小输出电压的计算如等式29所
voltage may
may be
be limited
limited by
by the
the minimum
minimum controllable
controllable on
on time.
time. The
The minimum
minimum output
output voltage
voltage in
in this
this case
case is
is given
given by
by
voltage
示。
Equation 29
29
Equation
�
�
Voutm
Voutm in
in �
� ontim
ontim em
em in
in �� Fsm
Fsm ax
ax �� �Ioutm
Ioutm in
in �� �RDS2m
RDS2m in
in �� �
� Ioutm
Ioutm in
in �� �RL
RL �
� RDS2m
RDS2m in
in �
Where:
Where: 其中：
Voutmin =
= minimum
minimum achieveable
output voltage
voltage
Voutmin
achieveable output
Voutmin = 可取得的最小输出电压
Ontimemin =
= minimum
minimum controllable
controllable on-time
on-time (135
(135 nsec
maximum)
Ontimemin
nsec maximum)
Ontimemin
= 最小可控开通时间（最大为
135 nsec）
Fsmax
=
maximum
switching
frequency
including
tolerance
Fsmax = maximum switching frequency including tolerance
(29)
(29)
= 最大开关频率包括容许误差
Vinmax
=
input
Vinmax Fsmax
= maximum
maximum
input voltage
voltage
最大输入电压
Ioutmax Vinmax
= minimum
minimum
load current
current
= load
Ioutmax
=
RDS1min
= minimum
minimum
high side
side MOSFET
MOSFET on
on resistance
resistance (36-32
(36-32 mŸ
mŸ typical)
typical)
RDS1min
=
high
Ioutmax
= 最小负载电流
RDS2min
=
minimum
low
side
MOSFET
on
resistance
(19
mŸ
typical)
RDS2min = minimum 电阻器上的最小高边
low side MOSFET on resistance （
(19 mŸ typical)
Ω的典型值）
RDS1min =
RL
of
RL =
= series
series resistance
resistance电阻器上的最小低边
of output
output inductor
inductor
RDS2min =
RL = 输出电感的串联阻值
Compensation Component
Component
Selection
Compensation
Selection
MOSFET 36-32 m
MOSFET（19 mΩ的典型值）
There
补偿组件的选择
There are
are several
several industry
industry techniques
techniques used
used to
to compensate
compensate DC/DC
DC/DC regulators.
regulators. The
The method
method presented
presented here
here is
is
easy to
to calculate
calculate and
and yields
yields high
high phase
phase margins.
margins. For
For most
most conditions,
conditions, the
the regulator
regulator has
has a
a phase
phase margin
margin between
between
easy
目前存在一些业界的技术用于补偿
DC或DC调节器。这里给出的方法计算简单并且能获得较高的相位裕度。在大多数情况
60 and
and
90 degrees.
degrees. The
The method
method presented
presented
here ignores
ignores the
the effects
effects of
of the
the slope
slope compensation
compensation that
that is
is internal
internal to
to
60
90
here
the
the
compensation
over
frequency
the TPS54620.
TPS54620. Since
Since
the90slope
slope
compensation is
is ignored,
ignored, the
the actual
actual cross
cross
over 内部斜坡补偿的影响。由于斜坡补偿
frequency is
is usually
usually lower
lower than
than
下，调节器具有一个
度之间的相位裕度。我们在这里提出的方法忽略了
60度到
TPS54620
the
for
the cross
cross over
over frequency
frequency used
used in
in the
the calculations.
calculations. Use
Use SwitcherPro
SwitcherPro software
software软件进行更加精确的设计。
for a
a more
more accurate
accurate design.
design.
被忽略，实际的交叉频率通常低于我们在计算中使用的交叉频率。可使用
SwitcherPro
24
24
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Copyright
Texas
© 2009
Copyright ©
© 2009,
2009, 版权所有：德州仪器
Texas Instruments
Instruments Incorporated
Incorporated
产品文件夹链接：
Product
Folder
:TPS54620
TPS54620
Product
Folder Link(s)
Link(s)
:TPS54620
www.ti.com.cn
www.ti.com ........................................................................................................................................................................................................
www.ti.com
www.ti.com ........................................................................................................................................................................................................
........................................................................................................................................................................................................
TPS54620
TPS54620
TPS54620
TPS54620
ZHCS004–2009年5月
SLVS949 – MAY 2009
SLVS949
SLVS949 –
– MAY
MAY 2009
2009
fpmod
esrthe esrfzmod
31
Cout 30 and
22.4
µf
First, the modulator pole,
fpmod, and
zero, fzmod must30
be calculated
using Equation
Equation
31.
First,
the
modulator
pole,
fpmod,
and
the
esr
zero,
fzmod
must
be
calculated
using
Equation
30
and
Equation
31.
TPS54620
First,Cout,
the modulator
pole,
fpmod,ofand
theµf.esr
zero,
fzmod 32
must
calculated
Equation
30 and Equation
31.
值。利用等式
的起始点，然后就可以得到需要补偿的元件。对于本设计样例，
为12.9
32和等式
33可估算处闭环交叉频率
fco
fpmodfor
For
use
a derated
value
22.4
use
Equation
andbeEquation
33using
to estimate
a starting
point
the
For
Cout,
use
a
derated
value
of
22.4
µf.
use
Equation
32
and
Equation
33
to
estimate
a
starting
point
for
the
www.ti.com
........................................................................................................................................................................................................
SLVS949
– MAY
2009
For
Cout,
use
a
derated
value
of
22.4
µf.
use
Equation
32
and
Equation
33
to
estimate
a
starting
point
for
the
closed
loop
crossover
frequency
fco.
Then
the
required
compensation
components
may
be
derived.
For
this
TPS54620
，
为
。等式
得到的是调节器极点与
零点的几何均值，而等式
得到的是调节器极点与二分之一开关频率
kHz
fzmod
2730
kHz
32
esr
33
closed
loop
crossover
the
components
may
be
For
closed
loop
crossover
frequency
fco.
Then
theis required
required
compensation
components
may
be derived.
derived.
For this
this
design example,
fpmod frequency
is 12.9 kHzfco.
andThen
fzmod
2730 kHz.compensation
Equation 32 is
the geometric
mean
ofSLVS949
the modulator
www.ti.com
........................................................................................................................................................................................................
– MAY 2009
design
example,
fpmod
is
12.9
kHz
and
fzmod
is
2730
kHz.
Equation
32
is
the
geometric
mean
of
the
modulator
的几何均值。根据这两个值中最低的那个，选取一个与之最接近的频率，作为我们期望得到的交叉频率
。在这种情况下，等式
fco
First,
the
modulator
pole,
fpmod,
and
the
esr
zero,
fzmod
must
be
calculated
using
Equation
30
and
Equation
31.
design
example,
is 12.9
kHz and
fzmod
is 2730 kHz.
Equation
is the geometric
of the
pole
and
the esr fpmod
zero and
Equation
33 is
the geometric
mean
of the 32
modulator
pole and mean
one half
themodulator
switching
pole
and
the
esr
zero
and
Equation
33
is
the
geometric
mean
of
the
modulator
pole
and
one
half
the
switching
For
Cout,
use
a
derated
value
of
22.4
µf.
use
Equation
32
and
Equation
33
to
estimate
a
starting
point
for
the
pole
and
the
esr
zero
and
Equation
isesr
the
geometric
mean
ofascalculated
the
pole
and one
the
switching
的结果为
。最低值为
，因此我们选择一个略高一点的频率，
，作为我
frequency.
Use
a而等式
frequency
nearand
the33
lower
ofzero,
these
two
values
themodulator
intended
crossover
frequency
fco.
In this
32
175
kHz
33得到的结果为
55.7
kHz
55.7
kHzbe
60.5
kHz
First,
the modulator
pole,
fpmod,
the
fzmod
must
using
Equation
30 half
and
Equation
31.
frequency.
Use
a frequency
frequency
near
the
lower
ofthe
these
two 55.7
values
as The
the intended
intended
crossover
frequency
fco.For
In this
this
closedEquation
loopUse
crossover
frequency
fco.lower
Thenof
required
compensation
components
may kHz.
be derived.
frequency.
a
near
the
these
two
values
as
the
crossover
frequency
fco.
In
case
32
yields
175
kHz
and
Equation
33
yields
kHz.
lower
value
is
55.7
A
slightly
higher
For
Cout,
use
a
derated
value
of
22.4
µf.
use
Equation
32
and
Equation
33
to
estimate
a
starting
point
for
the
们期望得到的交叉频率。
case
Equation
32
yields
175
kHz
and
Equation
33
yields
55.7
kHz.
The
lower
value
is
55.7
kHz.
A
slightly
higher
design
example,
is175
12.9
kHz
and
fzmod is
2730
kHz.
Equation
32lower
is thevalue
geometric
mean of
modulator
case
32fpmod
yields
kHz
and
Equation
yields
55.7
kHz. The
is 55.7
A the
slightly
higher
frequency
of crossover
60.5
kHz
isfrequency
chosen
as
the
intended
crossover
frequency.
closedEquation
loop
fco.
Then
the33
required
compensation
components
may kHz.
be derived.
For
this
frequency
of
60.5
kHz
is
chosen
as
the
crossover
frequency.
pole
and the
esr zero
and
Equation
33 intended
is the geometric
mean
of the modulator pole and one half the switching
frequency
of
60.5
kHz
is
chosen
as
the
intended
crossover
frequency.
design example, fpmod
Ioutis 12.9 kHz and fzmod is 2730 kHz. Equation 32 is the geometric mean of the modulator
frequency.
Use a frequency
near the lower of these two values as the intended crossover frequency fco. In this
f pmod
Iout
Iout
pole and
the �
zero
and
Equation 33 is the geometric mean of the modulator pole and one half the switching
ff pmod
�
2 ��
� Vout
� Cout
(30)
pmod
�esr
case Equation
32
yields
175
kHz and Equation 33 yields 55.7 kHz. The lower value is 55.7 kHz. A slightly higher
�� Vout
�� Cout
frequency. Use 22a�� �
frequency
near the lower of these two values as the intended crossover frequency fco. In (30)
this
Vout
Cout
(30)
1 chosen
frequency of 60.5�kHz
is
as the intended crossover frequency.
f zm od � 32 yields
case Equation
11 175 kHz and Equation 33 yields 55.7 kHz. The lower value is 55.7 kHz. A slightly higher
zm od
od �
� 2 � � � RESR
� Cout as the intended crossover frequency.
Iout
(31)
ff zm
frequency
of 60.5
is chosen
�� RESR
f pmod
� 22 �� ��kHz
(31)
RESR �� Cout
Cout
(31)
2 � � � Vout
� Cout
(30)
f co � f pmod
�Iout
f zmod
(32)
ff pmod
co
�� ff 1zmod
co �
� �ff pmod
pmod
zmod
(32)
(32)
(30)
f zm od � 2 � � � Vout � Cout
f sw� Cout
2
�
�
�
RESR
(31)
1
ff co
�
f
pmod
�
f
sw
zm �
co
�od �ff pmod
pmod �� f sw
2
ff co
(33)
2 � � � RESR
(31)
co � f pmod
� f zmod
2 � Cout
(33)
2
(32)
(33)
Now the
compensation
components can be calculated.First claculate the value for R2 which sets the gain of the
f
co
�
f
pmod
�
f
zmod
Now
the
compensation
components
can
be
calculated.First
claculate
the
value
for
R2
which
sets
the
gain
of
the
f
sw
现在就可以计算出补偿元件了。首先计算
的值，这个值用于设置交叉频率下的补偿网络的增益。利用等式
来确定
Now
the
components
canR2
be
calculated.First
claculate
value for
which
sets34the
gain
of (32)
the
R2的值。
compensated
the crossover
frequency.
Use Equation
34 to the
determine
theR2
value
of R2.
f cocompensation
� fnetwork
pmod � at
compensated
network
at
the
crossover
frequency.
Use
Equation
34
to
determine
the
value
of
R2.
compensated
network
at
the
crossover
frequency.
Use
Equation
34
to
determine
the
value
of
R2.
2
(33)
2� � f c � Voutf �sw
Cout
f co� �22�
� �� Cout
R2
cc �� Vout
� ��f ffpmod
Vout
Cout
R2
�
2
Gm
�
Vref
�
VI
R2 �compensation components
Now the
can be calculated.First claculate the value for R2 which sets the gain of (33)
the
gm
(34)
Gm
�� Vref
gm
Gm
Vref �� VI
VI
(34)
compensated
network
at gm
the crossover frequency. Use Equation 34 to determine the value of R2.
(34)
Now
compensation
components
can be calculated.First
claculate
the value for R2
which
sets modulator
the gain ofpole
the
Next the
calcutlate
value
of C3. Together
with R2, C3 places
a compensation
sero
at the
2�C3�network
f cthe
� Vout
� Cout
然后计算
的值。
与
一起，在调节器极点频率处设置了一个补偿
。等式
给出了
值的计算。
Next
calcutlate
the
value
of
C3.
Together
with
R2,
C3
places
a
compensation
sero
at
the
modulator
pole
compensated
at
the
crossover
frequency.
Use
Equation
34
to
determine
the
value
of
R2.
C3
R2
sero
35
C3
Next
calcutlate
the
value
of
C3.
Together
with
R2,
C3
places
a
compensation
sero
at
the
modulator
pole
R2 � Equation 35 to determine the value of C3.
frequency.
frequency.
Equation
35
Vref
� VI
�Gm
� f c�� Cout
� Vout
�to
Cout
frequency. 2Vout
Equation
35
to
determine the
the value
value of
of C3.
C3.
gmdetermine
(34)
R2
�
C3 � Vout
Vout
�
Cout
�
Cout
Gm
�
Vref
�
VI
gm
C3
�
� R2 value of C3. Together with R2, C3 places a compensation sero at the modulator pole
(35)
� Iout the
(34)
Next C3
calcutlate
Iout
(35)
Iout �� R2
R2 35 to determine the value of C3.
(35)
frequency.
Equation
Usingcalcutlate
Equation 34
Equation
the standard
for places
R2 andaC3
are 1.69 kŸ and
pF. modulator pole
Next
theand
value
of C3.35Together
withvalues
R2, C3
compensation
sero8200
at the
Using Equation
Equation
34
and Equation
Equation 35
35 the
the standard
standard values for
for R2
R2 and
and C3
C3 are
are 1.69
1.69 kŸ
kŸ and
and 8200
8200 pF.
pF.
Vout 34
� Cout
Using
and
frequency.
35 to determine
the value of values
C3.
C3 � Equation
An additional
high frequency
pole
can
be used if necessary
by adding
a capcitor in parallel with the series
根据等式
和等式
，能够得到
与
的标准值分别为
Ω和
。
34
35
R2
C3
1.69
k
8200
pF
Iout
R2frequency
An
additional
high
be
ifif necessary
by
capcitor
parallel
with
the
(35)
Vout
��Cout
An
additional
high
frequency
pole
can
be used
used
necessary
by adding
adding
a pole
capcitor
inused
parallel
with
the series
series
combination
R2
and
C3. Thepole
polecan
frequency
is given
by Equation
36. Thisa
is notin
in this
design.
C3 � of
combination
of
R2
and
C3.
The
pole
frequency
is
given
by
Equation
36.
This
pole
is
not
used
in
this
design.
combination
of
R2
and
C3.
The
pole
frequency
is
given
by
Equation
36.
This
pole
is
not
used
in
this
design.
Iout34
(35)
Using
Equation
35 the standard values for R2 and C3 are 1.69 kŸ and 820036pF.
1� R2and Equation
如果需要的话，可以在
给出了这一极点频率
R2与C3的串联组合中并行接入一个电容器，以获得另外一个高频极点。等式
11
fp �
p�
� 2 � � high
� R2
Cp
ffEquation
p
Using
34 ��and
Equation
35 the
for R2 and
C3 are 1.69
kŸ andin8200
pF. with the series
An additional
frequency
pole
can standard
be usedvalues
if necessary
by adding
a capcitor
parallel
(36)
的计算方法。在我们的设计样例中没有用到这一极点。
2 ��
� �� R2
R2
Cp
Cp
(36)
combination2 �of
R2 �and
C3. The pole frequency is given by Equation 36. This pole is not used in this design. (36)
An additional high frequency pole can be used if necessary by adding a capcitor in parallel with the series
Application
Curves
1
combination
R2 and C3. The pole frequency is given by Equation 36. This pole is not used in this design.
Application
Curves
f p � of
Application
Curves
2 � � � R2
1 � Cp
(36)
LOAD TRANSIENT
STARTUP with VIN
fp �
LOAD TRANSIENT
TRANSIENT
STARTUP with
with VIN
VIN
2 � � � R2 � Cp LOAD
STARTUP
(36)
Vin�=�10�V�/�div
Application Curves Vout�=�50�mV�/�div�(ac�coupled)
Vin�=�10�V�/�div
Vin�=�10�V�/�div
Vout�=�50�mV�/�div�(ac�coupled)
首先，调节器的极点
应用曲线
Application Curves
，以及
的零点
必须通过等式
和等式
计算得到。对于
，使用
的降额数
Vout�=�50�mV�/�div�(ac�coupled)
LOAD TRANSIENT
STARTUP with VIN
EN�=�2�V�/�div
EN�=�2�V�/�div
Vin�=�10�V�/�div
EN�=�2�V�/�div
启动时的VIN
负载瞬态
LOAD TRANSIENT
STARTUP with VIN
Vout�=�50�mV�/�div�(ac�coupled)
Iout�=�2A /�div�(1.5 A to�4.5�load�step)
Iout�=�2A /�div�(1.5 A to�4.5�load�step)
Vout�=�50�mV�/�div�(ac�coupled)
Iout�=�2A /�div�(1.5 A to�4.5�load�step)
Vin�=�10�V�/�div
EN�=�2�V�/�div
SS/TR�=�1�V�/�div
SS/TR�=�1�V�/�div
SS/TR�=�1�V�/�div
EN�=�2�V�/�div
Iout�=�2A /�div�(1.5 A to�4.5�load�step)
Vout�=�2�V�/�div
Vout�=�2�V�/�div
Vout�=�2�V�/�div
SS/TR�=�1�V�/�div
Time�=�2�msec�/�div
Time�=�2�msec�/�div
Time�=�2�msec�/�div
SS/TR�=�1�V�/�div Figure 36.
Iout�=�2A /�div�(1.5 A to�4.5�load�step)
Time�=�500 μsec�/�div
Time�=�500 μsec�/�div
Time�=�500 μsec�/�div
Figure 35.
Figure
Figure 35.
35.
Figure
Figure 36.
36.
Vout�=�2�V�/�div
Time�=�500 μsec�/�div
Time�=�2�msec�/�div
Vout�=�2�V�/�div
Figure 35.
Figure 36.
Time�=�500 μsec�/�div
Time�=�2�msec�/�div
图Figure
35 35.
Figure
图36 36.
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Copyright © 2009, Texas Instruments Incorporated
Copyright ©
© 2009,
2009, Texas
Texas Instruments
Incorporated
Copyright
Instruments Incorporated
产品文件夹链接：TPS54620
Product Folder Link(s) :TPS54620
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Folder Link(s)
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TPS54620
TPS54620
ZHCS004–2009
5月 ........................................................................................................................................................................................................
www.ti.com.cn
SLVS949 – MAY年
2009
www.ti.com
TPS54620
SLVS949 – MAY 2009 ........................................................................................................................................................................................................ www.ti.com
启动时的
启动时的PRE-BIAS
EN
TPS54620
STARTUP
with EN
STARTUP
with PRE-BIAS
SLVS949 – MAY 2009 ........................................................................................................................................................................................................
www.ti.com
Vin�=�5�V�/�div
Vin�=�10�V�/�div
STARTUP with EN
STARTUP with PRE-BIAS
Vin�=�5�V�/�div
Vin�=�10�V�/�div
STARTUP with EN
STARTUP with PRE-BIAS
EN�=�2�V�/�div
Vin�=�5�V�/�div
Vin�=�10�V�/�div
EN�=�2�V�/�div
EN�=�2�V�/�div
Vout�=�2�V�/�div
SS/TR�=�1�V�/�div
Vout�starting�from�pre-bias�voltage
Vout�=�2�V�/�div
SS/TR�=�1�V�/�div
Vout�=�2�V�/�div
Vout�starting�from�pre-bias�voltage
SS/TR�=�1�V�/�div
Time�=�2�msec�/�div
Vout�=�2�V�/�div
Time�=�20�msec�/�div
Vout�starting�from�pre-bias�voltage
Vout�=�2�V�/�div
图Figure
37 37.
Figure
图38 38.
Time�=�2�msec�/�div
Time�=�20�msec�/�div
Vout�=�2�V�/�div
Figure with
37. VIN
SHUTDOWN
Time�=�2�msec�/�div
Figure 38.
SHUTDOWN
with EN
Vin�=�10�V�/�div
Time�=�20�msec�/�div
Vin�=�10�V�/�div
Vin�=�10�V�/�div
Vin�=�10�V�/�div
关闭时的
VINwith
Figure
37. VIN
SHUTDOWN
关闭时的
FigureEN
38.
SHUTDOWN
with EN
SHUTDOWN with VIN
SHUTDOWN with EN
EN�=�2�V�/�div
Vin�=�10�V�/�div
Vin�=�10�V�/�div
EN�=�2�V�/�div
EN�=�2�V�/�div
EN�=�2�V�/�div
SS/TR�=�1�V�/�div
EN�=�2�V�/�div
SS/TR�=�1�V�/�div
EN�=�2�V�/�div
SS/TR�=�1�V�/�div
SS/TR�=�1�V�/�div
Vout�=�2�V�/�div
Vout�=�2�V�/�div
SS/TR�=�1�V�/�div
SS/TR�=�1�V�/�div
Vout�=�2�V�/�div
Time�=�2�msec�/�div
Time�=�2�msec�/�div
Vout�=�2�V�/�div
Figure 39.
Figure 40.
Vout�=�2�V�/�div
Time�=�2�msec�/�div
Time�=�2�msec�/�div
Vout�=�2�V�/�div
39. with NO LOAD
OUTPUT VOLTAGE
图Figure
39RIPPLE
Time�=�2�msec�/�div
Vout�=�10�mV�/�div�(ac�coupled)
Figure
39. with NO LOAD
OUTPUT VOLTAGE
RIPPLE
Vout�=�10�mV�/�div�(ac�coupled)
无负载时的输出电压纹波
OUTPUT
VOLTAGE RIPPLE with NO LOAD
Figure
OUTPUT VOLTAGE
图RIPPLE
40 40. with FULL LOAD
Time�=�2�msec�/�div
Vout�=�10�mV�/�div�(ac�coupled)
Figure
40. with FULL LOAD
OUTPUT VOLTAGE
RIPPLE
Vout�=�10�mV�/�div�(ac�coupled)
OUTPUT满负载时的输出电压纹波
VOLTAGE RIPPLE with FULL LOAD
Vout�=�10�mV�/�div�(ac�coupled)
Vout�=�10�mV�/�div�(ac�coupled)
PH�=�5�V�/�div
PH�=�5�V�/�div
PH�=�5�V�/�div
PH�=�5�V�/�div
PH�=�5�V�/�div
PH�=�5�V�/�div
Time�=�1 μsec�/�div
Time�=�1 μsec�/�div
Figure 41.
Figure 42.
Time�=�1 μsec�/�div
Time�=�1 μsec�/�div
Figure 41.
Figure 42.
Time�=�1 μsec�/�div
Time�=�1 μsec�/�div
图Figure
41 41.
Figure
图42 42.
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Copyright © 2009, 版权所有：德州仪器
Texas Instruments Incorporated
© 2009
产品文件夹链接：
Product
Folder Link(s)
:TPS54620
TPS54620
Product Folder Link(s) :TPS54620
Copyright © 2009, Texas Instruments Incorporated
Copyright © 2009, Texas Instruments Incorporated
TPS54620
TPS54620
ZHCS004–2009
5月
www.ti.com.cn
www.ti.com ........................................................................................................................................................................................................ SLVS949
– MAY 年
2009
TPS54620
TPS54620
无负载时的输入电压纹波
www.ti.com ........................................................................................................................................................................................................
SLVS949
– MAY 2009
INPUT
VOLTAGE RIPPLE with NO LOAD
INPUT 满负载时的输入电压纹波
VOLTAGE RIPPLE with FULL
LOAD
www.ti.com ........................................................................................................................................................................................................
SLVS949 – MAY 2009
Vin�=�200�mV�/�div�(ac�coupled)
Vin�=�200�mV�/�div�(ac�coupled)
INPUT VOLTAGE RIPPLE with NO LOAD
INPUT VOLTAGE RIPPLE with NO LOAD
INPUT VOLTAGE RIPPLE with FULL LOAD
INPUT VOLTAGE
RIPPLE with FULL LOAD
Vin�=�200�mV�/�div�(ac�coupled)
Vin�=�200�mV�/�div�(ac�coupled)
Vin�=�200�mV�/�div�(ac�coupled)
Vin�=�200�mV�/�div�(ac�coupled)
PH�=�5�V�/�div
PH�=�5�V�/�div
PH�=�5�V�/�div
PH�=�5�V�/�div
PH�=�5�V�/�div
PH�=�5�V�/�div
Time�=�1 μsec�/�div
Time�=�1 μsec�/�div
Figure 43.
Figure 44.
图43
图44
Time�=�1 μsec�/�div
Time�=�1 μsec�/�div
LINE
REGULATION
Time�=�1
μsec�/�div
Figure 44.
Figure 44.
电压调节率
LINE
REGULATION
LINE REGULATION
40
60
30
150
180
150
60
30
20
-10
150
120
30
Phase
120
90
0
90
60
-30
Gain
20
10
-20
60
30
-60
Gain
0
-30
-120
-10
-20
-50
-30
-60
-150
-20
-30
-60
-60
-90
-180
1000000
1000
100
10
-40
-50
100000
30
0
-90
0
-10
-40
10000
10
0
-30
-30
-40
-90
-120
Frequency�-�Hz
0.04
0.03
0.05
0.01
-0.02
0
Io�=�3A
Io�=�0A
0
-0.03
-0.01
Io�=�3A
Io�=�0A
Io�=�6A
-0.01
-0.04
-0.02
-0.02
-0.05
-0.03
9
Io�=�6A
8
9
10
11
8
9
10
11
-0.05
10
1
10
Vin�=�12�V
Vin�=�12�V
0.03
0
0.02
0.02
-0.01
0.01
0.01
-0.02
0
0
-0.03
-0.01
-0.01
-0.04
-0.02
10
0.1
1
1
2
3
4
5
Output�Current�- A
6
7
8
0
1
2
3
0
1
2
3
-0.05
4
5
Output�Current�- A
4
5
Output�Current�- A
6
7
8
6
7
8
13
14
15
16
17
Figure 46.
12
13
Input�Voltage�-�V
12
13
14
15
16
17
14
15
16
17
10
1
10
10
0.1
1
Vout
VoutVsense
1
0.01
0.1
0.1
0.001
0.01
1
0.01
0.1
Ideal�Vsense
Vsense
Ideal�Vsense
Vsense
0.1
0.001
0.01
0.01
0.0001
0.001
0.01
0.0001
0.001
0.01
0.0001
0.00001
0.001
0.00001
Figure 47.
-0.04
-0.05
12
TRACKING
PERFORMANCE
Input�Voltage�-�V
Figure
图46 46.
Figure 46.
Vout
TRACKING PERFORMANCE
TRACKING
PERFORMANCE
跟踪性能
Ideal�Vsense
0.001
0.00001
0.00010.001
0
11
-0.04
-0.05
0.04
0.01
0.03
-0.03
-0.04
10
Input�Voltage�-�V
Vin�=�12�V
0.05
0.02
0.04
-0.02
-0.05
-0.03
Io�=�3A
Io�=�0A
Io�=�6A
-180
LOAD
REGULATION
Frequency�-�Hz
图Figure
45 45.
Figure 45.
LOAD REGULATION
LOAD
REGULATION
负载调节率
0.05
0.03
0
0.02
0.02
-0.01
0.01
8
1000000
1000000
Figure 45.
0.04
0.01
0.03
-0.03
-0.04
-150
-180
100000
100000
10000
10000
10001000
100 100
10 10
-60
0.05
0.02
0.04
-120
-150
Frequency�-�Hz
-50
-60
Percent�Regulation�-�%
Percent�Regulation�-�%
Percent�Regulation�-�%
Phase
Output�Voltage�-�V
Output�Voltage�-�V
Output�Voltage�-�V
Gain�-�dB
Gain�-�dB Gain�-�dB
Gain
40
30
0
0.03
0.05
180
90
60
50
20
50
40
10
0.04
120
Percent
Percent
Regulation
Regulation
Percent
- % Regulation
-%
-%
50
0.05
180
Phase�-�Deg
Phase�-�DegPhase�-�Deg
60
0.001
Figure 47.
Figure 47.
0.1
1
0.001
0.00001
10 0.0001
0.0001
Track�In�Voltage�-�V
0.01
Figure
48. 1
0.1
0.01 Track�In�Voltage�-�V
0.1
Vsense�Voltage�-�V
Vsense�Voltage�-�V
Vsense�Voltage�-�V
CLOSED LOOP RESPONSE
Figure 43.
Figure 43.
闭环响应
CLOSED
LOOP RESPONSE
Phase
CLOSED LOOP RESPONSE
Time�=�1 μsec�/�div
1
0.00001
10 0.00001
10
Track�In�Voltage�-�V
Figure 48.
Figure 48.
图47
图48
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Incorporated
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2009
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产品文件夹链接：
Product
Folder Link(s) :TPS54620
TPS54620
Copyright © 2009, Texas Instruments Incorporated
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s) :TPS54620
TPS54620
TPS54620
TPS54620
SLVS949 – MAY 2009 ........................................................................................................................................................................................................ www.ti.com
年5月
ZHCS004–2009
www.ti.com.cn
SLVS949 – MAY 2009
........................................................................................................................................................................................................
www.ti.com
Tjmax�=�150�°C,
no�air�flow
Tjmax�=�150�°C,
no�air�flow
150
150
125
125
125
125
100
100
100
100
75
75
VIN =�12�V,
V
=�3.3�V,
VOUT
IN =�12�V,
Fsw�=�480�kHz,
V
OUT =�3.3�V,
room�temp,�no�air�flow
Fsw�=�480�kHz,
room�temp,�no�air�flow
2
3
4
5
Load�Current�- A
2
3
4
5
Load�Current�Figure 49.A
50
50
25
25
MAXIMUM AMBIENT TEMPERATURE
vs TEMPERATURE
MAXIMUM
AMBIENT
最大环境温度
vs芯片功耗
IC POWER vs
DISSIPATION
IC POWER DISSIPATION
150
TA -�Maximum
TA -�Maximum
Ambient�Temperature�-�°C
Ambient�Temperature�-�°C
TA -�Maximum
TA -�Maximum
Ambient�Temperature�-�°C
Ambient�Temperature�-�°C
MAXIMUM AMBIENT TEMPERATURE
vs TEMPERATURE
MAXIMUM
AMBIENT
最大环境温度
负载电流
LOADvs
CURRENT
vs
LOAD CURRENT
150
0
1
0
1
6
75
75
50
50
25
25
6
0
0.5
0
0.5
1
1.5
2 2.5
3
3.5
PD -�IC�Power�Dissipation�-�W
1
1.5
2 2.5
3
3.5
PD -�IC�Power�Dissipation�-�W
150
100
95
A
125
95
90
no�air�flow
125
90
85
Efficiency�-�%
Efficiency�-�%
TJ -�Junction�Temperature�-�°C
TJ -�Junction�Temperature�-�°C
100
TA =�room�temperature,
no�air�flow
T =�room�temperature,
150
100
100
75
75
85
80
VOUT
VOUT
=�5�V=�3.3�V
75
70
VOUT =�3.3�V
VOUT =�1.8�V
70
65
65
60
50
60
55
25
VOUT =�5�V
80
75
50
25
4
Figure 50.
图50
Figure 50.
EFFICIENCY
vs
EFFICIENCY
效率
vs负载电流
LOAD
CURRENT
vs
LOAD CURRENT
图49
Figure 49.
JUNCTION TEMPERATURE
vs
JUNCTION
TEMPERATURE
结温度
vs芯片功耗
IC POWER
DISSIPATION
vs
IC POWER DISSIPATION
4
VOUTVOUT
=�1.8�V=�1.2�V
55
50
0
0
0.5
1
1.5
2
2.5
3
3.5
Pic�-�IC�Power�Dissipation�-�W
0.5
1
1.5
2
2.5
3
3.5
Pic�-�IC�Power�Dissipation�-�W
Figure 51.
4
0
VIN�=�12�V
Fsw�=�500�kHz
VIN�=�12�V
Fsw�=�500�kHz
1
2
50
4
图51
0
1
VOUT =�1.2�V
VOUT =�0.8�V
VOUT =�0.8�V
3
4
Load�Current�- A
3
2
4
Load�Current�Figure 52.A
5
6
5
6
图52
Figure 51.
Figure 52.
Thermal Performance
Thermal Performance
热性能
Figure 53. Thermal Signature of TPS54620EVM-374 Operating at
VIN=12V,VOUT=3.3V/6A,
TA = Room Temperature
Figure 53.
Thermal Signature of TPS54620EVM-374
Operating at
图53. TPS54620EVM-374
工作在TVIN=12V
、
、
VOUT=3.3V/6A
VIN=12V,VOUT=3.3V/6A,
=
Room
Temperature
A
TA =室温 条件下的热特征
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Product
Folder Link(s)
:TPS54620
© 2009
Copyright © 2009, 版权所有：德州仪器
Texas Instruments Incorporated
TPS54620
TPS54620
ZHCS004–2009年5月
www.ti.com.cn
www.ti.com
www.ti.com ........................................................................................................................................................................................................
........................................................................................................................................................................................................ SLVS949
SLVS949 –
– MAY
MAY 2009
2009
Fast Transient Considerations
快速暂态
(Fast Transient)的考虑因素
In applications where fast transinet responses are very important, the application circuit in Figure 34 can be
在快速暂态响应十分重要的应用中，需要将如图34所示的应用电路修改为如图54所示的自定义参考设计电路(PMP4854-2,
modified
as shown in Figure 54 which is a customized reference design (PMP4854-2, REV.B).
REV.B)。
The frequency responses of Figure 54 is shown in Figure 55. The crossover frequency is pushed much higher to
图54的频率响应如图
所示。交叉频率被推高很多，达到
118kHz，而相位裕度约为57Deg。
118kHz
and the phase55
margin
is about 57Deg.
图54. 具有快速暂态的
输出电源设计
3.3V
(PMP4854-2)
Figure 54. 3.3V Output
Power Supply
Design
(PMP4854-2)
with Fast Transients
Figure 55. Closed
Loop Response
for PMP4854-2
图55. PMP4854-2
的闭环响应
PCB Layout
Guidelines
印刷电路板
设计指南
(PCB)
Layout
is a critical portion of good power supply design.
See Figure56
56所示。最上层包括了
for a PCB layoutVIN
example.
TheVPHASE
top layer
布板对于好的电源设计而言是一个至关重要的部分。
、 VOUT以及
等
PCB布板的样例如图
contains the main power traces for VIN, VOUT, and VPHASE. Also on the top layer are connections for the
主要的电源走线。同样在最上层上还布有TPS54620剩余管脚的连接线，并填充大面积的地线。上层的地线应通过过孔与中间层
remaining pins of the TPS54620 and a large top side area filled with ground. The top layer ground area sould be
™
地
的地线相连接，过孔位于输入旁路电容与输出滤波电容处，以及直接位于
的器件下方，用以提供一个从
connected to the internal ground layer(s) using vias at the inputTPS54620
bypass capacitor,
the output filter PowerPAD
cpacitor and
directly under the GND
TPS54620
device to provide a thermal
path
from
the
PowerPAD™
land
to
ground.
The
GND
至地线的散热结构。
引脚应直接与芯片下方的散热增强封装
相连。当满额定负载下工作时，上层以及中间层的地
(power pad)
pin should be tied directly to the power pad under the IC and the power pad. For operation at full rated load, the
线区域必须能够提供足够的散热面积。如果有几个信号路径在快速的改变电流或电压，将会导致与杂散电感或寄生电容的相互作
top side ground area together with the internal ground plane, must provide adequate heat dissipating area. There
用，产生噪声或降低电源的性能。为了有助于消除这些问题，使用一个低
、具有that
绝缘等级的陶瓷旁路电容，来使
X5R或
X7Rinteract
are several signals paths that conduct fast changing currents or ESR
voltages
can
with stray inductance
or
parasitic
capacitance
to
generate
noise
or
degrade
the
power
supplies
performance.
To
eliminate these
引脚也必须通过一个低
PVIN引脚避开地线。应注意尽量减少由于旁路电容、PVIN引脚及地线之间的连接所形成回路的面积。VINhelp
problems, the PVIN pin should be bypassed to ground with a low ESR ceramic bypass capacitor with X5R or
ESR
X5R或Care
X7R绝缘等级的陶瓷旁路电容来与地线隔开。
X7R、具有
dielectric.
should be taken to minimize the loop area formed by the bypass capacitor connections, the
PVIN pins, and the ground connections. The VIN pin must also be bypassed to ground using a low ESR ceramic
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应确保这个电容与模拟地的走线相连接，而不是与PVIn旁路电容的电源地走线相连接。由于PH连接是开关点，因而输出电
感应放置在靠近PH引脚的位置，并且PCB的导线面积要尽可能小，以避免过度的电容耦合。输出滤波电容的地线应使用与PVIN
输入旁路电容相同的电源地走线。在保持足够宽度的同时应尽量减少这类导线的长度。如图所示，小信号部分应连接至模拟地
路径。RT/CLK引脚对噪声比较敏感，因此RT电阻应放置在尽可能靠近IC且具有最小长度走线的位置处。其它的外部元件可大致
放置在如图所示的位置。使用其它的PCB布线方式，可能也会得到可接受的性能，但这一布线方式已经证明能产生比较好的效
果并作为一个设计准则。
30
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TPS54620
ZHCS004–2009年5月
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上层
接地区域
频率设置电阻
输出滤波
电容
输入旁路
电容
GND
GND
启动
电容
PWRGD
RT/CLK
PH
PVIN
PH
PVIN
EN
VIN
SS/TR
V_SNS
PVIN
输出
电感
BOOT
EXPOSED
POWERPAD
AREA
VOUT
PH
COMP
VIN
慢启动
电容器
VIN
输入旁路
电容
UVLO设置
电阻器
补偿网络
反馈电阻器
与接地层相连的过孔
元件下方的内层蚀刻
图56 PCB设计
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TPS54620
ZHCS004–2009
5月 ........................................................................................................................................................................................................
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SLVS949 – MAY年
2009
www.ti.com
Figure 57. Ultra-Small
PCB layout
Using的超小
TPS54620
(PMP4854-2)
图57. 基于TPS54620
(PMP4854-2)
PCB设计
Estimated Circuit Area
The estimated printed circuit board area for the components used in the design of Figure 34 is 0.58. in2 (374
mm2). This area does not include test points or connectors.
电路面积的估值
The board area can be further reduced if size is a big concern in an application. Figure 57 shows the printed
circuit
board
layout for PMP4854-2 as shown 0.58
in Figure
54 whose
board area is as small as 17.27 mm x 11.30
在图
平方英寸（
34中用到的元件在印刷电路中的估计面积为
374平方毫米）。该面积不包括测试点或者连接器。
mm.
如果实际应用对尺寸有比较高的要求，该部分电路板面积还可以进一步缩小。图57给出了如图54所示的PMP4854-2的印刷
电路板设计，而它的实际板面积大小仅为17.27 mm x 11.30mm。
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PACKAGE OPTION ADDENDUM
PACKAGE OPTION ADDENDUM
www.ti.com
www.ti.com.cn
2-Jun-2009
2 – 6 – 2009
PACKAGING INFORMATION
封装信息
(1)
Orderable
Device
订购器件
(1)
Status
状态 (1)
Package
封装类型
Type
Package
封装图纸
Drawing
生态环保(2)
Pins
引脚 Package
封装数量 Eco Plan
分级 (2)
Qty
TPS54620RGYR
ACTIVE
QFN
RGY
14
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TPS54620RGYT
ACTIVE
QFN
RGY
14
250
CU NIPDAU
Level-2-260C-1 YEAR
Green (RoHS &
no Sb/Br)
Lead/Ball
Finish
铅/球含量
(3)
MSL
Peak Temp (3)
湿度灵敏度峰值
The marketing status values are defined as follows:
(1)
ACTIVE:
Product device recommended for new designs.
销售状态定义如下：
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
ACTIVE:
NRND: Not推荐使用该产品器件做新的设计。
recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
已经宣布该设备将停产，在停产之前还可以购买。
TI
LIFEBUY:
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE:
TI has discontinued the production of the device.
不推荐用于新的设计。器件依然在产以支持原有的客户，但是在新的设计中
TI不推荐使用该器件。
NRND:
器件已经被研制出但没有量产，目前有可能获得样片，但也有可能无法获取。
PREVIEW:
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent
for the latest availability information and additional product content details.
TI已经停止生产该器件。
OBSOLETE:
TBD: The Pb-Free/Green conversion plan has not been defined.
(RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
生态环保分级：
、Pb-Free
）或Green
（RoHS &无锑
Pb-Free
(RoHS)
RoHS0.1%
Exempt
/溴），
forEco
all 6Plansubstances,
including the
requirement
that
lead not（
exceed
by weight
in homogeneous
materials.
Where designed to be soldered
at
high
temperatures,
TI
Pb-Free
products
are
suitable
for
use
in
specified
lead-free
processes.
敬请登陆http://www.ti.com/productcontent 以核对最新的信息及其他产品内容详情。
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
：无铅
package,
or /绿色改建计划尚未确定。
2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
TBD
compatible) as defined above.
”或者
“Pb-Free
要求，所有六种物质中规定铅含量不
：Sb/Br):
TI 中术语“
Lead-Free
Pb-Free
(RoHS)
Green (RoHS
& no
TI defines
"Green"
to mean
Pb-Free”是指半导体产品符合当前
(RoHS compatible), and free RoHS
of Bromine
(Br) and Antimony (Sb) based flame
retardants
(Br
or
Sb
do
not
exceed
0.1%
by
weight
in
homogeneous
material)
得超过同质材料质量的0.1%。在需要高温焊接的地方，TI 无铅产品适用于特定的无铅工序。
Pb-Free
(2)
（RoHS Exempt）：该组件至少有一项符合RoHs豁免，要么1）模具和封装之间使用无铅覆晶焊锡凸块焊料，要么2）
Pb-Free
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
模具和引线之间使用无铅胶粘剂。否则，根据前面的定义，该组件将被认为是无铅的（符合
RoHS标准）。
Green（RoHS&无锑/溴）：TI的定义，“绿色”意味着无铅（符合RoHS标准）并且无需要用到阻燃剂溴和锑（按重量计算的
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
均质材料中
或Sbits
不超过
provided. TI Br
bases
knowledge
and belief on information provided by third parties, and makes no representation or warranty as to the
0.1%）。
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
工业标准分类的湿度灵敏度指数，及焊接峰值温度。
MSL，峰值温度。
--分别表示按照
JEDEC
incoming
materials and
chemicals. TI and
TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
reasonable
(3)
重要信息和免责声明：本页中提供的信息代表了TI在提供日期时掌握的知识和理解。TI 提供的知识和理解都是基于第三方提供
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in thisTIdocument
sold by TI
的信息，对这些信息的可靠性不做任何承诺和保证。我们目前正在努力，更好的整合这些来自第三方的信息。
已采取并将继续
to Customer on an annual basis.
采取合理的措施来提供有价值的和精确的信息，但是对引入的材料及化学成分可能还没有进行破坏性测试或者化学分析。TI 及
TI 供应商考虑到某些信息的所有权因素，因此CAS 编号及其他限制性信息可能没有公开。
任何情况下，如果在每年的基础上由TI卖给客户的总价款超出了在本文档中的所列的信息，TI将不付有相关责任。
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PACKAGE
MATERIALS
INFORMATION
PACKAGE
OPTION
ADDENDUM
30 – 5 – 2009
PACKAGE MATERIALS INFORMATION
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30-May-2009
带和卷信息
TAPE AND REEL INFORMATION
www.ti.com
30-May-2009
卷尺寸
TAPE AND
REEL INFORMATION
带尺寸
卷
直径
洞
A0
B0
K0
W
P1
尺寸设计上要适合零件的宽度
尺寸设计上要适合零件的长度
尺寸设计上要适合零件的厚度
载体带的总宽度
临近连个洞的中心间隔
卷宽度(W1)
带上PIN 1取向的四象限位置分布
定位孔
用户进料方向
*All dimensions are nominal
袋状象限
Device
Package Package Pins
SPQ
*All dimensions are nominal
Type Drawing
*所有尺度都是标称值。
Device
Package Package Pins
SPQ
Type
Drawing
封装
封装
TPS54620RGYR
QFN
RGY
14 卷直径
1000
器件
引脚
SPQ
类型
图纸
(mm)
TPS54620RGYT
QFN
RGY
14
250
TPS54620RGYR
QFN
RGY
14
1000
TPS54620RGYR
QFN
RGY
14
1000
180.0
TPS54620RGYT
QFN
250
TPS54620RGYT
QFN
RGY
14RGY 25014
180.0
Reel
Reel
Diameter Width
(mm)
(mm)
Reel W1Reel
Diameter
Width
卷宽度
180.0
12.4
A0
(mm) W1(mm)
(mm)
W1(mm)
180.0
12.4
180.0
12.4
12.4
3.85
180.0
12.4
12.4
3.85
A0 (mm)
A0 (mm)
3.85
B0
(mm)
3.85
3.85
3.85
3.85
3.85
B0 (mm)
P1
W
Pin1
(mm) (mm) Quadrant
B0 (mm)
K0 (mm)
P1
W
Pin1
(mm)
8.0
12.0 Quadrant
Q1
K03.85
P1 1.35 W (mm)
Pin1象限
(mm)
3.85 (mm) 1.35 (mm) 8.0
12.0
Q1
3.85
1.35
8.0
12.0
Q1
1.35
8.0
12.0
Q1
3.85
1.35
8.0
12.0
Q1
1.35
8.0
12.0
Q1
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Pack Materials-Page 1
Pack Materials-Page 1
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PACKAGE OPTION ADDENDUM
PACKAGE MATERIALS INFORMATION
30 – 5 – 2009
www.ti.com.cn
www.ti.com
带和卷盒子尺寸
30-May-2009
*所有尺度都是标称值。
*All dimensions are nominal
Device
Package Type Package Drawing
器件
封装类型
封装图纸
引脚
TPS54620RGYR
QFN
RGY
TPS54620RGYR
QFN
RGY
14
TPS54620RGYT
QFN
RGY
TPS54620RGYT
QFN
RGY
14
Pins
SPQ
标准包装量
14
1000
1000
14
250
250
Length (mm)
长度(mm)
190.5
190.5
190.5
190.5
Width (mm)
宽度(mm)
212.7
212.7
212.7
212.7
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Pack Pack
Materials-Page
2
Materials-Page
2
Height (mm)
高度(mm)
31.8
31.8
31.8
31.8
工程数据
RGY(S-PAFP-N14)
塑料四方平板包装
引脚1 索引区域
顶部和底部
0.20标称
的引脚框架
水平座
座高度
外部散热盘
底端视图
注意： A. 所有的线尺度都以毫米作为基本单位。尺寸和公差均符合美国机械工程师协会(ASME) Y14.5M – 1994标准。
B. 此图如果发生变化，恕不另行通知。
C. QFN（四方平板无引线）封装配置参数。
D. 为了热性能及工程性能，封装的散热盘必须焊接到PCB板上。
E. 引脚1标识符位于封装的上层及底层，且在标示出的区域内。引脚1标识符可能是塑模的、标记的或是金属的。
F. 封装符合电子器件工程联合委员会(JEDEC) MO-241 variation BA标准。
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THERMAL PAD MECHANICAL DATA
RGY (S-PVQFN-N14)
www.ti.com.cn
散热信息
该封装包括一个外部散热盘，其设计目的是用来直接与外部散热器相连。该散热盘必须直接焊接到印制电路板（ PCB）上
面。 焊接后，PCB可以被用作散热器。另外，通过使用热过孔，散热盘可以被直接连接到器件的电气原理图所示的适合的铜板
上， 或者被连接到PCB内部设计的一个特殊散热结构上去。这种设计使集成电路（IC）的热传导性得到了优化。
关于四方平板无引线（ QFN ）封装及其优点的信息，请参阅应用报告、四方平板无引线逻辑封装、及德州仪器文献
No.SCBA017。该文档可以在www.ti.com网站上找到。
该封装中外部散热盘的尺寸如下图所示。
外部散热盘
底部视图
注：所有的线尺度都以毫米作为基本单位。
外部散热盘尺寸
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4206353 - 3/D 03/09
LAND PATTERN
样例模板设计
模版厚度0.125mm（注：E）
样板设计
热焊盘中心64%的焊料部分
被印制区域覆盖
非阻焊层
焊盘
设计的样例可能由于条件约
束而有所改变
（注：D,F）
样例
阻焊层开孔
（注：F）
样例
焊盘几何形状
(注：C)
注意： A. 所有的线尺度都以毫米作为基本单位。
B. 该图所示的设计如有更改，恕不另行通知。
C. 发布的IPC-7351建议作为替代设计。
D. 该封装是为能焊接到板上的热焊盘而设计的。如需详细的关于热信息、过孔要求以及推荐的PCB板设计方案，请参见应用手册、四方平
板封装、德州仪器的文献——编号 SCBA271，SLUA271及产品数据表。这些资料都可以从www.ti.com.cn网站上得到。
E. 激光切割的梯形外壁和圆角的孔径能让膏剂更好的脱离。客户可访问他们的电路板装配网站，以获得所推荐的模板设计方法。对模板的
设计考虑因素请参见IPC 7525。
F. 客户可访问他们的电路板制作网站，以获取信号焊盘间助焊层的网络容限。
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other Texas Instruments products and application solutions:
相关产品链接:
•
DSP - 数字信号处理器 http://www.ti.com.cn/dsp
•
电源管理 http://www.ti.com.cn/power
•
放大器和线性器件 http://www.ti.com.cn/amplifiers
•
接口 http://www.ti.com.cn/interface
•
模拟开关和多路复用器 http://www.ti.com.cn/analogswitches
•
逻辑 http://www.ti.com.cn/logic
•
RF/IF 和 ZigBee® 解决方案 www.ti.com.cn/radiofre
•
RFID 系统 http://www.ti.com.cn/rfidsys
•
数据转换器 http://www.ti.com.cn/dataconverters
•
时钟和计时器 http://www.ti.com.cn/clockandtimers
•
标准线性器件 http://www.ti.com.cn/standardlinearde
•
温度传感器和监控器 http://www.ti.com.cn/temperaturesensors
•
微控制器 (MCU) http://www.ti.com.cn/microcontrollers
相关应用链接:
•
安防应用 http://www.ti.com.cn/security
•
工业应用 http://www.ti.com.cn/industrial
•
计算机及周边 http://www.ti.com.cn/computer
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ZHCS004
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可访问以下 URL 地址以获取有关其它 TI 产品和应用解决方案的信息：
产品
放大器
http://www.ti.com.cn/amplifiers
数据转换器
http://www.ti.com.cn/dataconverters
DSP
http://www.ti.com.cn/dsp
接口
http://www.ti.com.cn/interface
逻辑
http://www.ti.com.cn/logic
电源管理
http://www.ti.com.cn/power
微控制器
http://www.ti.com.cn/microcontrollers
应用
音频
http://www.ti.com.cn/audio
汽车
http://www.ti.com.cn/automotive
宽带
http://www.ti.com.cn/broadband
数字控制
http://www.ti.com.cn/control
光纤网络
http://www.ti.com.cn/opticalnetwork
安全
http://www.ti.com.cn/security
电话
http://www.ti.com.cn/telecom
视频与成像
http://www.ti.com.cn/video
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http://www.ti.com.cn/wireless
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