Download Simulating FPGA Power Integrity Using S-Parameter Models

White Paper: Kintex-7 and Virtex-7 FPGAs
WP411 (v1.0) January 30, 2012
Simulating FPGA Power Integrity
Using S-Parameter Models
By: Hany Fahmy and Colin Warwick of Agilent Technologies, Inc.
and Jack Carrel, Ray Anderson, Harry Fu, and Romi Mayder of Xilinx, Inc.
The purpose of a Power Distribution Network (PDN) is to
provide power to electrical devices in a system. Each device
in a system not only has its own power requirements for its
internal operation, but also a requirement for the input
voltage fluctuation of that power rail. For Xilinx Kintex™-7
and Virtex®-7 FPGAs, the analog power rails have an input
voltage fluctuation requirement of not more than 10 mV
peak-to-peak from the 10 kHz to the 80 MHz frequency
range. The self- generated voltage fluctuation on the power
rails is a function of frequency and can be described by
Ohm's Law: Voltage (frequency) = Current (frequency) *
Self-Impedance (frequency).
Thus, if the user determines the self-impedance (frequency)
and knows the current (frequency) of the PDN, then the
voltage (frequency) can be determined. The self-impedance
(frequency) can easily be determined by simulating the
frequency domain self-impedance profile of the PDN and
is, thus, the subject of this white paper.
© Copyright 2012 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Zynq, and other designated brands included herein are trademarks of Xilinx in the United
States and other countries.
WP411 (v1.0) January 30, 2012
www.xilinx.com
1
Overview
Overview
Before simulating the frequency domain self-impedance profiles of a PDN, it is
important to establish expectations for the simulation results. To do this, an
understanding of the fundamental concepts must be attained:
• Series-Resonance Circuit and Impedance Minimums
• Parallel-Resonance Circuit and Impedance Maximums
• Frequency Components of Electrical Signals
• S-Parameter Model vs. Lumped RLC Model for Decoupling Capacitors
Series-Resonance Circuit and Impedance Minimums
A series-resonant circuit is defined by a capacitor (C) and inductor (L) that are
connected in series. When the XC (capacitive reactance) and XL (inductive reactance)
are equal in magnitude and opposite in phase, the current is at maximum. This
condition gives rise to an impedance minimum. The frequency at which this equality
occurs is called the series-resonant frequency and is described by Equation 1:
f
1 = ----------------2π LC
Equation 1
A common series-resonant circuit is formed by the capacitance (C) and the parasitic
inductance (L) of a given capacitor mounted on a printed circuit board. Figure 1 shows
the schematic circuit representation while Figure 2 shows the frequency domain
impedance profile.
X-Ref Target - Figure 1
Series-Resonant Circuit
R
R3
R = R_PCB_Capacitance
P3
Num = 3
C
C2
C=C_PCB_Capacitance
L
L2
L=L_PCB_Cap_Inductance
P4
Num = 4
WP411_01_012412
Figure 1:
Series-Resonant Components of a PCB-Mounted Capacitor
X-Ref Target - Figure 2
Series Resonant Circuit
1.6
1.4
Series_Resonance
1.2
1.0
0.8
Impedance
Minimum
0.6
0.4
0.2
0.0
0.0
0.1
0.2
0.3
0.4
0.5
Freq, GHz
Figure 2:
2
0.6
0.7
0.8
0.9
1.0
WP411_02_111011
Frequency-Domain Impedance Profile of PCB-Mounted Capacitor
www.xilinx.com
WP411 (v1.0) January 30, 2012
Overview
Parallel-Resonance Circuit and Impedance Maximums
A parallel anti-resonant circuit is defined by a capacitor (C) and inductor (L) that are
connected in parallel. When the XC (capacitive reactance) and XL (inductive reactance)
are equal in magnitude and opposite in phase, the reactive branch currents are also
equal in magnitude and opposite in phase. This gives rise to a minimum total current
and thus, a maximum total impedance is created. The frequency at which this
condition occurs is called the parallel anti-resonant frequency and is described by
Equation 2:
f
1 = ----------------2π LC
Equation 2
A common parallel anti-resonant circuit is one formed by the die capacitance and
package inductance. Figure 3 shows a schematic circuit representation while Figure 4
shows the frequency domain impedance profile.
X-Ref Target - Figure 3
Parallel Anti-Resonant Circuit
P1
Num = 1
R
R1
R = R_Die_Capacitance
R
R2
R = R_Package_Inductance
C
C1
C = C_Die_Capacitance
L
L1
L = L_Package_Inductance
P2
Num = 2
WP411_03_112411
Figure 3:
Parallel Anti-Resonant Components of Die and Package Properties
X-Ref Target - Figure 4
Parallel Anti-resonant Circuit
0.8
Parallel_Anti_Resonance
0.7
Impedance
Maximum
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0.0
0.1
0.2
0.3
0.4
0.5
Freq, GHz
Figure 4:
WP411 (v1.0) January 30, 2012
0.6
0.7
0.8
0.9
1.0
WP411_04_111011
Frequency-Domain Impedance Profile of Die and Package Properties
www.xilinx.com
3
Overview
Frequency Components of Electrical Signals
The frequency domain current profile of VCCO(f) is shown in Figure 5 and Figure 6 as
simulated at the BGA power balls of the Xilinx Virtex-7 XC7VX485T FPGA in the
FFG1761 pin package.
In the example, the simulation is running a memory interface at 1.866 Gb/s with a
PRBS15 data pattern. The power spectral density of VCCO(t) is wide-banded,
extending from 10 MHz up to the 10 GHz. As the data traffic pattern and activity
change, the simulations demonstrate that the dominant frequency components of the
power spectral density also change. Therefore, the simulations show that PDN noise is
a wide-band phenomenon; PDN simulations must, therefore, be run over a wide-band
frequency range.
DDR3 Die Input 1,866 Mb/s
Frequency Spectrum DDR3 Die Input
2.0
mag(FS_Kintex_7_SSTL15), mV
DDR3_Die_Input_Eye_Diagram, Volts
X-Ref Target - Figure 5
1.5
1.0
0.5
0.0
-0.5
30
25
20
15
10
5
0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
IE7
IE8
Time, nsec
25
20
15
10
5
0
-5
-10
20
30
40
50
60
70
80
90
100
mag(FS_Kirtex_7_SSTL15_Current), mA
Kintex_7_SSTL15_Current, mA
30
01
IE10
Freq, Hz
SSTL15 HPIO VCCO Current
0
IE9
Frequency Spectrum SSTL15 Current
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
IE7
Time, nsec
IE8
IE9
IE10
Freq, Hz
WP411_05_011112
Figure 5:
4
Memory Interface Simulation Activity Patterns
www.xilinx.com
WP411 (v1.0) January 30, 2012
Overview
X-Ref Target - Figure 6
–
+
Power
V_DC
SRC1
VDC = 1.5V
+
+
40Ω
Impedance
3 Inch Trace
PU
PRBS
T
PC
O
GC
PRBS15
IBIS_O
IBIS1
K7325TFF900
SSTL15 HP IO
Eye_Probe
Eye_Probe1
PU
VIN
DDR3 Die Input
Output
PD
VtPRBS
VPRBS1
DDR3
Package
Parasitics
L
SLIN
L1
TL1
Subst = ”SSub1” L = 1.38 nH
R = 0.25656
W = 5.0 mil
L = 3000.0 mil
I/O
C
DigO
C1
C = 0.33 pF
PC T
GC L
IBIS_IO + V_DC
IBIS4
SRC2
– VDC = 1.5V
PD
DDR3
1.86 Gb/s
DQ Pin
WP411_06_011112
Figure 6:
Simulation Test Setup
Because the power spectral density is of a wide band, the frequency domain
self-impedance profile must be simulated over a wide range. Below 1 kHz, the voltage
regulator module (VRM) dominates the frequency domain self-impedance profile.
Above 10 GHz, the on-die capacitance dominates the impedance profile. Thus, Xilinx
recommends running the simulations from 1 kHz to 10 GHz.
S-Parameter Model vs. Lumped RLC Model for Decoupling Capacitors
As a comparison between using lumped RLC circuits and S-parameters to run PDN
simulations, the decoupling capacitors portion of the PDN circuit is examined first.
In this simulation, an attempt is made to curve-fit an S-parameter model for common
X5R capacitors in the following EIA case sizes: 0201, 0402, 0603, 0805, 1206, and 1610.
After matching the capacitive reactance and the series-resonant frequency given in
Equation 1,the percentage error of the inductive reactance at 100 MHz is measured.
These simulations are done at room temperature (25°C) with no applied DC bias.
Figure 7 through Figure 9 show the circuit schematic representations. Figure 10 and
Figure 11 show the simulation results.
WP411 (v1.0) January 30, 2012
www.xilinx.com
5
Overview
X-Ref Target - Figure 7
+ Term
–
Term1
Num = 1
Z = 50Ω
+ Term
–
+ Term
Term4
Num = 4
– Z = 50Ω
+ Term
Term3
Num = 3
–
Z = 50Ω
+ Term
–
Term16
Num =16
Z = 50Ω
Term2
Num = 2
Z = 50Ω
S2P
SNP1
L
L2
L= 320 pH
R= 10 mΩ
+ Term
–
Term15
Num = 15
Z = 50Ω
+ Term
+ Term
Term14
Num = 14
–
Z = 50Ω
Term13
Num = 13
–
Z = 50Ω
S2P
SNP4
L
L3
L = 500 pH
R = 8 mΩ
Data Sheet
Ceramic
0201 1uF
4V X5R
C
C2
C = 0.69 uF
Data Sheet
Ceramic
0402 4.7uF
4V X5R
C
C3
C = 3.7 uF
WP411_07_013012
Figure 7:
Decoupling Capacitors Simulation, Schematic Representation 1
X-Ref Target - Figure 8
+ Term
–
Term12
Num = 12
Z = 50Ω
+ Term
–
Term11
Num = 11
Z = 50Ω
+ Term
+ Term
Term10
Num = 10
–
Z = 50Ω
Term9
Num = 9
–
Z = 50Ω
+ Term
+ Term
Term17
Num = 17
–
Z = 50Ω
Term18
Num = 18
–
Z = 50Ω
+ Term
+ Term
Term19
Num = 19
–
Z = 50Ω
Term20
Num = 20
–
Z = 50Ω
S2P
SNP3
L
L4
L = 800 pH
R = 4 mΩ
S2P
SNP5
L
L6
L = 800 pH
R = 3.5 mΩ
Data Sheet
Ceramic
0603 22uF
4V X5R
C
C4
C = 14 uF
Data Sheet
Ceramic
0805 22uF
4V X5R
C
C6
C = 14 uF
WP411_08_013012
Figure 8:
Decoupling Capacitors Simulation, Schematic Representation 2
X-Ref Target - Figure 9
Figure 9:
6
+ Term
+ Term
Term21
Num = 21
–
Z = 50Ω
Term22
Num = 22
–
Z = 50Ω
+ Term
+ Term
Term23
Num = 23
–
Z = 50Ω
Term24
Num = 24
–
Z = 50Ω
+ Term
+ Term
Term32
Num = 25
–
Z = 50Ω
Term31
Num = 26
–
Z = 50Ω
+ Term
+ Term
Term30
Num = 27
–
Z = 50Ω
Term29
Num = 28
–
Z = 50Ω
S2P
SNP6
Data Sheet
Ceramic
1206 100uF
4V X5R
L
C
L5
C5
L = 1,360 pH C = 50 uF
R = 2.75 mΩ
S2P
SNP8
Data Sheet
Ceramic
1210 100uF
4V X5R
L
C
L7
C7
L = 1,200 pH C = 60 uF
R = 1.9 mΩ
WP411_09_013012
Decoupling Capacitors Simulation, Schematic Representation 3
www.xilinx.com
WP411 (v1.0) January 30, 2012
Overview
1
1E-1
1E-2
1E5
1E6
1E7
1E8
1E9
6E9
Freq, Hz
Impedance Phase 0201
95
80
65
50
35
20
0
-10
-25
-40
-55
-70
-85
-100
1E5
1E6
1E7
1E8
1E9
Freq, Hz
Impedance Magnitude 0603
1E1
1
1E-1
1E-2
1E-3
1E5
1E6
1E7
1E8
1E9
6E9
Freq, Hz
Impedance Phase 0603
95
80
65
50
35
20
0
-10
-25
-40
-55
-70
-85
-100
1E5
1E6
1E7
1E8
1E9
Freq, Hz
phase(Ceramic_1206_1uF_RLC), deg mag(Ceramic_1206_1uF_RLC)
phase(Ceramic_1206_1uF_S), deg
mag(Ceramic_1206_1uF_S)
Impedance Magnitude 0201
1E1
phase(Ceramic_0603_1uF_RLC), deg mag(Ceramic_0603_1uF_RLC)
phase(Ceramic_0603_1uF_S), deg
mag(Ceramic_0603_1uF_S)
phase(Ceramic_0201_1uF_RLC), deg mag(Ceramic_0201_1uF_RLC)
phase(Ceramic_0201_1uF_S), deg
mag(Ceramic_0201_1uF_S)
X-Ref Target - Figure 10
Impedance Magnitude 1206
1E1
1
1E-1
1E-2
1E-3
1E5
1E6
1E7
1E8
1E9
6E9
Freq, Hz
Impedance Phase 1206
95
80
65
50
35
20
0
-10
-25
-40
-55
-70
-85
-100
1E5
1E6
1E7
1E8
1E9
Freq, Hz
WP411_10_011612
Figure 10:
Simulation Results (EIA Case Sizes 0201 / 0603 / 1206)
1E-1
1E-2
1E-3
1E5
1E6
1E7
1E8
1E9
6E9
Freq, Hz
Impedance Phase 0402
95
80
65
50
35
20
0
-10
-25
-40
-55
-70
-85
-100
1E5
1E6
1E7
1E8
Freq, Hz
1E9
Impedance Magnitude 0805
1E1
1
1E-1
1E-2
1E-3
1E5
1E6
1E7
1E8
1E9
6E9
Freq, Hz
Impedance Phase 0805
95
80
65
50
35
20
0
-10
-25
-40
-55
-70
-85
-100
1E5
1E6
1E7
Freq, Hz
1E8
1E9
phase(Ceramic_1210_100uF_RLC), deg mag(Ceramic_1210_100uF_RLC)
phase(Ceramic_1210_100uF_S), deg
mag(Ceramic_1210_100uF_S)
1
mag(Ceramic_0805_22uF_RLC)
mag(Ceramic_0805_22uF_S)
Impedance Magnitude 0402
1E1
phase(Ceramic_0805_22uF_RLC), deg
phase(Ceramic_0805_22uF_S), deg
phase(Ceramic_0402_4_7uF_RLC), deg mag(Ceramic_0402_4_7uF_RLC)
phase(Ceramic_0402_4_7uF_S), deg mag(Ceramic_0402_4_7uF_RLC)
X-Ref Target - Figure 11
Impedance Magnitude 1210
1E1
1
1E-1
1E-2
1E-3
1E5
1E6
1E7
1E8
1E9
6E9
Freq, Hz
Impedance Phase 1210
95
80
65
50
35
20
0
-10
-25
-40
-55
-70
-85
-100
1E5
1E6
1E7
1E8
1E9
Freq, Hz
WP411_11_011612
Figure 11:
WP411 (v1.0) January 30, 2012
Simulation Results (EIA Case Sizes 0402 / 0805 / 1210)
www.xilinx.com
7
Overview
A summary of the data is shown below in Table 1:
Table 1:
Summary of Result Data, Decoupling Capacitors Simulation
Size
Capacitance (µF)
Impedance Magnitude @ 100 MHz
S-Parameter
RLC
Model
% Error
Series-Resonant
Frequency
66.7
0.209
0.751
259.3
600 KHz
100
100.0
0.255
0.845
231.4
700 KHz
14
22
57.1
0.18
0.501
178.3
1.5 MHz
603
14
22
57.1
0.178
0.501
181.5
1.5 MHz
402
3.7
4.7
27.0
0.15
0.313
108.7
3.5 MHz
201
0.69
1
44.9
0.129
0.198
53.5
10 MHz
EIA
Code
S-Parameter
Data
Sheet
% Error
1210
60
100
1206
50
805
It is known that the typical capacitor manufacturer specifies the capacitance of a
capacitor with zero DC bias and 0.5 Vrms AC voltage, while the s-parameter models
are typically measured with a 0 dbm AC signal.
In S-Parameter Models for Decoupling Capacitors section, the various methods for
generating the S-parameter model of a capacitor are examined.
S-Parameter Models for Decoupling Capacitors
At first glance, the measurement of the capacitor's PDN impedance profile (the
impedance with respect to frequency) seems to be a simple task, but several subtle
details are required to ensure the measured data is accurate.
The frequency domain measurement is usually accomplished by utilizing a Vector
Network Analyzer (VNA). The obvious method is to probe the PDN making an S11
measurement, and then convert the measured s-parameters to impedance by means of
the Equation 3 relationship:
1 + S11
Z dut = 50 -----------------1 – S11
Equation 3
An impedance measurement using this method, however, has inherent inaccuracies
due to the fact that the instrument typically has a 50Ω input impedance and the PDN
has a very low impedance (typically in the milliohm range). The accuracy of the
measured VNA data inherently has errors because the typical uncertainty of S11
(when rho, the reflection coefficient, is near 1) can be in the 1%–2% range.
This equates to an impedance uncertainty in the 0.3Ω-to-0.4Ω range. If PDN
impedances in the milliohm range are being measured, it quickly becomes obvious
that the desired impedance measurement is lost in the measurement uncertainty.
A second factor to consider is that the inductive parasitics of the probing arrangement
can easily exceed the value of the DUT inductance. There is no easy way to back out
the probe parasitics from the measured data.
Fortunately, an S21 measurement is a good alternative to an S11 measurement to
determine the PDN impedance. In this method, it is found that Zdut = 25(S21). With
this measurement technique, the solder of the decoupling capacitor is included in the
measurement. By utilizing the S21 measurement, the impedance uncertainty is
reduced into the 10s-of-milliohms range. In addition, the probe parasitics are in series
with 50Ω as opposed to being in series with the DUT impedance, which reduces their
effects to near negligible levels. For a more complete discussion of this topic, see
Accuracy Improvements of PDN Impedance Measurements in the Low to Middle Frequency
8
www.xilinx.com
WP411 (v1.0) January 30, 2012
Overview
Range presented at DesignCon 2010 by Istvan Novak of SUN Microsystems and
Yasuhiro Mori and Mike Resso of Agilent Technologies
(http://www.home.agilent.com/upload/cmc_upload/All/DC10_ID2696_Novak-M
ori-Resso.pdf).
RLC Models for Decoupling Capacitor
Decoupling capacitors are often characterized by vendors by means of three
parameters: R (resistance), L (inductance), and C (capacitance). The C parameter is the
decap's intrinsic capacitance; the L is its intrinsic inductance; and the R is the ESR of
the decoupling capacitor. When this simple RLC model for a decoupling capacitor is
utilized in a simulation along with a good PDN model, the mounting inductance and
spreading inductance associated with the package or PCB combines with the decap's
intrinsic inductance to effectively model the loop inductance. This loop inductance
plus the package inductance resonates with the die capacitance to form a parallel
anti-resonant circuit with a unique impedance profile.
Series RLC models of decoupling capacitors are easy to understand, and they simulate
quickly as both frequency domain and transient simulations with a minimum of
issues. As noted previously, the RLC values for the model can come from a vendor's
data sheet; alternatively, they can be derived from measured s-parameter data by
fitting the values of a simple series RLC circuit to the response of the s-parameters. In
some cases, particularly at low frequencies, the simple series RLC circuit works
adequately. However, when it is required to determine the impedance profile of a
PDN accurately over a wide bandwidth of DC to several gigahertz, things usually do
not work out so simply.
Two main issues make simple series RLC models inadequate for accurate PDN
simulations. Due to the stacked layers of the decoupling capacitor construction, there
is distributed inductance and resistance in the Z axis of the plate stack. This causes the
L parameter of the series RLC representation to be frequency dependent. In most
simulators, there is no frequency-dependent L element. First, a reasonably accurate
series RLC model can be constructed at either low frequencies or high frequencies, but
cannot model both simultaneously. Second, while a complex multi-element model can
be constructed to more accurately model the frequency-dependent L effect, such
models are very difficult to design and manage.
Therefore, rather than use a simple series RLC circuit that is known to be inaccurate
over a wide bandwidth, or attempt to synthesize a more complex multi-element
model, the simulation work done at Xilinx suggests that it is much easier and more
accurate to utilize a measured wideband s-parameter decoupling capacitor model
when simulating PDNs.
Note: Ceramic decoupling capacitor models are strongly voltage dependent. Therefore, it is
important to obtain the s-parameter model from the capacitor manufacturer that has been
measured at the operating voltage of interest—for both DC and AC voltages.
WP411 (v1.0) January 30, 2012
www.xilinx.com
9
Running the PDN Simulations with the Agilent ADS 2011.10
Running the PDN Simulations with the Agilent ADS 2011.10
To simulate the frequency domain self-impedance profile of a Power Distribution
Network, Xilinx recommends using the Agilent ADS 2011 software bundle. This
software bundle provides the high-speed-digital (HSD) designer with a wide range of
tools. Every aspect of the power integrity problem requires a specific technique for
solving it. For example, PDN analysis requires the following:
1. True frequency-domain simulation of the PDN parallel anti-resonances and series
resonances with solid S-parameter handling and assurance of “Passivity and
Causality”
2. Patented convolution (Kramers-Kronig) to bring frequency-domain models
(measurement-based models and EM-based models) into the time domain (eye
diagrams, BER contours, and jitter decomposition)
3. Using an extraction technique, such as Method-of-Moment, which has excellent
accuracy from DC to GHz range
PDN Simulation Example
In this simulation example, the simulation performed is the PDN of the MGTAVCC
and MGTAVTT analog power rails for the Xilinx 7 series XC7VX485T FPGA in the
FFG1761 pin package.
Two cases are simulated here. Case 1 uses the PCB capacitors listed in Table 2, which
are similar to the recommended PCB caps for the Xilinx Virtex-6 devices.
Table 2:
Case 1 Capacitors
QTY per Group
MGTAVCC
MGTAVTT
MGTVCCAUX
Capacitance
(µF)
4
4
2
0.022
4
4
0
0.47
2
2
1
1
2
2
1
4.7
Case 2 uses the PCB capacitors described in Table 3.
Table 3:
Case 2 Capacitors
QTY per Group
MGTAVCC
MGTAVTT
MGTVCCAUX
Capacitance
(µF)
0
0
0
0.022
0
0
0
0.47
0
0
0
1
0
0
0
4.7
Figure 12 is the schematic for both cases (1) and (2) listed above for the MGTAVCC and
MGTAVTT power rails. For case 2 (with no PCB capacitors), there is still one bulk
capacitor mounted on the PCB specified by the manufacturer of the voltage regulator
module.
10
www.xilinx.com
WP411 (v1.0) January 30, 2012
Running the PDN Simulations with the Agilent ADS 2011.10
X-Ref Target - Figure 12
Package
Capacitors
S2P
SNP50
File=“GRM033C80G104KE19series(for_Fuji2_AVTT_AVCC).s2p”
S2P
SNP51
File=“GRM033C80G104KE19series(for_Fuji2_AVTT_AVCC).s2p”
S2P
SNP52
File=“GRM033C80G104KE19series(for_Fuji2_AVTT_AVCC).s2p”
Die Capacitors
+
–
Term
Term13
Num=13
Z=50 Ohm
+
–
Term
Term14
Num=14
Z=50 Ohm
C
C30
C=22.16 nF
R
R8
R=10 mOhm
S2P
SNP53
File=“GRM033C80G104KE19series(for_Fuji2_AVTT_AVCC).s2p”
S6P
SNP48
File=“fga2034_485t_ff1761_031411_Avcc_G10.s6p”
L
L28
L=25 nH
R=1 mOhm
S2P
SNP105
File=“GRM155R61C223KA01_022uF_0402 S2P”
VRM
S2P
SNP104
File=“GRM155R61C223KA01_022uF_0402.S2P”
S20P
SNP47
File=“VC7203_MGTAVCC_092611_175001_S.s20p”
+
–
V_DC
SRC7
Vdc=1.2 V
S2P
SNP49
File=“T520V337M2R5ATE025.s2p”
S2P
SNP112
File=“GRM188R60J475KE19_47uF_0603.S2P”
S2P
SNP113
File=“GRM188R60J475KE19_47uF_0603.S2P”
S2P
SNP105
File=“GRM155R61C223KA01_022uF_0402.S2P”
S2P
SNP111
File=“GRM152R60J474ME15_047_0402.S2P”
S2P
SNP105
File=“GRM155R61C223KA01_022uF_0402.S2P”
S2P
SNP110
File=“GRM188R61C105KA93_1uF_0603.S2P”
S2P
SNP108
File=“GRM152R60J474ME15_047_0402.S2P”
S2P
SNP107
File=“GRM152R60J474ME15_047_0402.S2P”
S2P
SNP106
File=“GRM152R60J474ME15_047_0402.S2P”
S2P
SNP109
File=“GRM188R61C105KA93_1uF_0603.S2P”
WP411_12_012212
Figure 12:
WP411 (v1.0) January 30, 2012
Power Rails Simulation Schematic Representation
www.xilinx.com
11
Running the PDN Simulations with the Agilent ADS 2011.10
Figure 13 show the simulations results.
MGTAVCC - Magnitude
1300
1200
1100
1000
900
800
Typical Competitor
700
600
500
400
300
200
100
0
1E3
1E4
1E5
1E6
1E7
1E8
1E9
1E10
mag(Competitor_Tx_Rx_Supply_With_PCB_Caps)
mag(MGTAVTT_Die_Without_PCB_Caps)
mag(MGTAVTT_Die_With_PCB_Caps)
mag(Competitor_PLL_Supply_With_PCB_Caps)
mag(MGTAVCC_Die_Without_PCB_Caps)
mag(MGTAVCC_Die_With_PCB_Caps)
X-Ref Target - Figure 13
MGTAVCC - Magnitude
1300
1200
Typical Competitor
1100
1000
900
800
700
600
500
400
300
200
100
0
1E3
1E4
freq, Hz
1E5
1E6
1E7
1E8
1E9
1E10
freq, Hz
WP411_13_012212
Figure 13:
Power Rails Simulation Results
Figure 14 shows the complete simulation time using a typical laptop computer
running the Windows-7 64-bit operating system is only 11.68 seconds!
X-Ref Target - Figure 14
WP411_14_012212
Figure 14:
Complete Simulation Time, Windows-7 64-bit OS
Because the simulation results for both cases result in almost identical frequency
domain self-impedance profiles for the MGTAVCC and MGTAVTT power rails, and
because the MGTVCCAUX power rail has an internal low drop out regulator
integrated on the die, similar performance between the two cases should be expected.
As a simple reference, the impedance profiles were simulated on a competitive device
with 0 PCB capacitors beyond the 1 bulk PCB capacitor typically required by the
voltage regulator manufacturer. Profiles representing the VCCH_GXBL0,
VCCT_GXBL0, and VCCR_GXBL0 power rails were run.
12
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WP411 (v1.0) January 30, 2012
Running the PDN Simulations with the Agilent ADS 2011.10
As can easily be seen in the PDN profiles of a typical competitive device, the analog
rails would have a peak impedance of well over 2Ω if the PCB caps were removed!
Transmitter Hardware Measurements
Figure 15 through Figure 18 contain a series of eye diagrams at 10.3125 Gb/s using the
QPLL and 6.25 Gb/s using the CPLL with PRBS15 data pattern measured on the
Agilent Infiniium DCA-J Wide-Bandwidth Oscilloscope. This Agilent 86100C with the
86108A precision waveform analyzer has been selected to make these hardware
measurements because of the following key attributes:
1. High bandwidth, low noise, and ultra-low residual jitter
2. Simple one connection “triggerless” operation
3. PLL characterization including loop BW/jitter transfer
4. Integrated hardware clock recover with adjustable loop BW/Peaking—exceeds
industry standards
Figure 15 shows the eye diagram and associated jitter decomposition when using the
CPLL running at 6.25 Gb/s for case 1.
X-Ref Target - Figure 15
WP411_15_011612
Figure 15:
Case 1 Eye Diagram, 6.25 Gb/s
Figure 16 shows the eye diagram and associated jitter decomposition when using the
CPLL running at 6.25 Gb/s for case 2 (no PCB caps).
WP411 (v1.0) January 30, 2012
www.xilinx.com
13
Running the PDN Simulations with the Agilent ADS 2011.10
X-Ref Target - Figure 16
WP411_16_011612
Figure 16:
Case 2 Eye Diagram, 6.25 Gb/s
Figure 17 shows the eye diagram and associated jitter decomposition when using the
QPLL running at 10.3125 Gb/s for case 1.
X-Ref Target - Figure 17
WP411_17_011612
Figure 17:
Case 1 Eye Diagram, 10.3125 Gb/s
Figure 18 shows the eye diagram and associated jitter decomposition when using the
QPLL running at 10.3125 Gb/s for case 2 (no PCB caps).
14
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WP411 (v1.0) January 30, 2012
Running the PDN Simulations with the Agilent ADS 2011.10
X-Ref Target - Figure 18
WP411_18_011612
Figure 18:
Case 2 Eye Diagram, 10.3125 Gb/s
As seen in the scope screenshots in Figure 15 through Figure 18, the total jitter is both
cases 1 and 2 is within the measurement tolerance of the setup. Thus, hardware
measurements have confirmed the simulation results showing that 0 PCB caps are
required for proper operation of the transmitter.
Receiver Measurements
Table 4 is a summary of the receiver hardware measurements based on a loopback test
using eyescan. The data recorded in Table 4 is the voltage amplitude noise with all
transceivers in the package running asynchronously. As shown by the data, the
voltage amplitude noise is the same or less after all the PCB caps have been removed
when using either the CPLL or the QPLL.
Table 4:
Comparison of Voltage Amplitude Noise with/without Decoupling Caps
PLL
CPLL
QPLL
Bit Rate
6.25 Gb/s
10.3125 Gb/s
MGTAVCC
All Caps
No Caps
All Caps
No Caps
MGTAVTT
All Caps
No Caps
All Caps
No Caps
MGTVCCAUX
All Caps
No Caps
All Caps
No Caps
% Full Scale
3.6%
3.3%
5.0%
4.5%
Figure 19 is a summary of the receiver's jitter tolerance analysis with all transceivers in
the package running asynchronously for both cases 1 and 2.
As shown by the data, the jitter tolerance is the same or less after all the PCB caps have
been removed. The jitter tolerance analysis was done at 10-12 BER threshold and a data
rate of 10.3125 Gb/s.
WP411 (v1.0) January 30, 2012
www.xilinx.com
15
Summary
X-Ref Target - Figure 19
100.00
SI, UI
10.00
All Caps BER12
No Caps BER12
1.00
0.100
0.01
0.10
1.00
10.00
100.00
Frequency, MHz
WP411_xx_012212
Figure 19: Comparison of Jitter Tolerance with/without Decoupling Caps
Summary
PDN simulations, confirmed by hardware measurements, have shown that no PCB
caps beyond that recommended by the voltage regulator manufacturer are required
for the MGTAVTT, MGTAVCC, and MGTVCCAUX power rails for proper operation
of the transceivers in Xilinx's Kintex-7 and Virtex-7 devices.
While the PCB capacitors are not needed for proper operation of the transceivers,
however, proper filtering can be required on the PCB to achieve the input voltage
ripple noise specification of 10 mV peak-to-peak (10 kHz to 80 MHz) when measured
at the BGA ball of the package.
Currently, Xilinx has several Agilent ADS Power Integrity Design Kits available for
7 series FPGAs that support all device power supplies (digital and analog). Contact
your local Xilinx field application engineer to obtain these Agilent ADS Design Kits.
To obtain a 30-day free license of Agilent ADS2011, please visit the following link:
https://software.business.agilent.com/TrialLicense/TrialLicenseRequest.aspx?Prod
Num=W2200F-1U1-TRL
16
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WP411 (v1.0) January 30, 2012
Revision History
Revision History
The following table shows the revision history for this document:
Date
Version
01/30/12
1.0
Description of Revisions
Initial Xilinx release.
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WP411 (v1.0) January 30, 2012
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17