High Speed Layout Design Guidelines This application note
... Configure the unused I/O pin as an output pin and then drive the output low. This configuration acts as a virtual ground. Connect this low driving output pin to GNDINT and/or the boards ground plane. Configure the unused I/O pins as output, and drive high to prevent VCC sag. Turn on the slow slew ra ...
... Configure the unused I/O pin as an output pin and then drive the output low. This configuration acts as a virtual ground. Connect this low driving output pin to GNDINT and/or the boards ground plane. Configure the unused I/O pins as output, and drive high to prevent VCC sag. Turn on the slow slew ra ...
Interfacing AES3 and S/PDIF
... AES3 to AES3id or S/PDIF IF (BIG if) you know that either the transmitter or the receiver is transformer coupled and the interconnect distance is short then a simple resistor divider will match the impedances and change the level as shown in Fig. 1. This is the AES3id recommended network for creati ...
... AES3 to AES3id or S/PDIF IF (BIG if) you know that either the transmitter or the receiver is transformer coupled and the interconnect distance is short then a simple resistor divider will match the impedances and change the level as shown in Fig. 1. This is the AES3id recommended network for creati ...
CM1235 - Small Footprint ESD Clamp Array for
... makes the overall ESD protection device more transparent to the high bandwidth data signals passing through the channel. The innovative architecture turns the disadvantages of the parasitic inductive elements into useful components that help to limit the ESD current strike to the protected device an ...
... makes the overall ESD protection device more transparent to the high bandwidth data signals passing through the channel. The innovative architecture turns the disadvantages of the parasitic inductive elements into useful components that help to limit the ESD current strike to the protected device an ...
