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ECE 546
Lecture - 18
Timing & Signaling
Spring 2014
Jose E. Schutt-Aine
Electrical & Computer Engineering
University of Illinois
[email protected]
ECE 546 – Jose Schutt-Aine
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Semiconductor Technology Trends
ECE 546 – Jose Schutt-Aine
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The Interconnect Bottleneck
Technology
Generation
MOSFET Intrinsic
Switching Delay
Response
Time
1.0 mm
~ 10 ps
~ 1 ps
0.01 mm
~ 1 ps
~ 100 ps
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The Interconnect Bottleneck
Al
3.0 mW -cm
Cu
1.7 mW -cm
SiO2
k = 4.0
Low k
k = 2.0
Al & Cu .8m Thick
Al & Cu Line 43m Long
SPEED/PERFORMANCE ISSUE
45
40
Gate Delay
35
Sum of Delays, Cu & Low K
30
Delay (ps)
Gate wi Al & SiO2
Sum of Delays, Al & SiO2
Interconnect Delay, Al & SiO2
25
Interconnect Delay, Cu & Low K
20
15
10
Gate
5
0
650
595
540
485
430
375
320
265
210
155
100
Generation (nm)
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Chip-Level Interconnect Delay
Pulse Characteristics:
Line Characteristics
rise time: 100 ps
fall time: 100 ps
pulse width: 4ns
length : 3 mm
near end termination: 50 W
far end termination 65 W
Near End Response
Far End Response
1
0.7
0.6
Volts
0.45
Logic
threshold
0.175
Board
VLSI
Submicron
Deep Submicron
0.5
Volts
Board
VLSI
Submicron
Deep Submicron
0.725
0.4
0.3
Logic
threshold
0.2
0.1
0
-0.1
-0.1
0
0.4
0.8
1.2
1.6
2
0
T ime (ns)
0.4
0.8
1.2
1.6
2
T ime (ns)
ECE 546 – Jose Schutt-Aine
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Interconnect
• Total interconnect length (m/cm2) – active wiring
only, excluding global levels will increases:
Year
Total
Length
2003
2004
2005
2006
2007
2008
2009
579
688
907 1002 1117 1401 1559
• Interconnect power dissipation is more than 50% of
the total dynamic power consumption in 130nm and
will become dominant in future technology nodes
• Interconnect centric design flows have been adopted
to reduce the length of the critical signal path
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Metallic Conductors

Area
th
Leng
Re s ist an ce : R
Le ng th
R=
 Are a
Submicron level:
W=0.25 microns
R=422 W/mm
Package level:
W=3 mils
R=0.0045 W/mm
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Integration & Signal Speed
Before
Today
I(t)
current
current
I(t)
time
time
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Signal Integrity
Ideal
Common
Noisy
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Signal Degradation
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Modeling Interconnections
Mid-range
Frequency
Low Frequency
High Frequency
LT
CT/2
CT/2
Zo
or
Short
LT/2
LT/2
Transmission
Line
CT
Lumped
Reactive CKT
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WAVE PROPAGATION
l
l
z
Wavelength : l
propagation velocity
l=
frequency
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Why Transmission Lines ?
In Free Space
At 10 KHz : l = 30 km
At 10 GHz : l = 3 cm
Transmission line behavior is prevalent when the
structural dimensions of the circuits are
comparable to the wavelength.
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Transmission Line Model
Let d be the largest dimension of a circuit
circuit
z
l
If d << l, a lumped model for the circuit can be used
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Transmission Line Model
circuit
z
l
If d ≈ l, or d > l then use transmission line model
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Frequency Components
of Digital Signal
C0
+
C1
+
C2
+
C3
+
C4
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RC Network
A is the steady-state gain of the
1
network;
A
1   f / f2 
2
vo ( f )
A=
vi ( f )
1
f2 
2 RC
The gain falls to 0.707 of its low-frequency value at the
frequency f . f is the upper 3-dB frequency or the 3-dB
bandwidth of the RC network.
2
2
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RC Network
R
+
+
V
vi
C
-
vo
-
vo  V 1  e  t / RC 
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RC Network
R
+
+
V
vi
C
vo
-
-
Rise time : tr = t90% - t10%
t r  2.2RC 
2.2 0.35

2f2
f2
Rule of thumb: A 1-ns pulse requires a circuit with
a 3-dB bandwidth of the order of 2 GHz.
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Frequency Dependence of Lumped
Circuit Models
At higher frequencies, a lumped circuit model is no
longer accurate for interconnects and one must use
a distributed model. Transition frequency depends
on the dimensions and relative magnitude of the
interconnect parameters.
0.3 ´ 109
f 
10d er
0.35
tr 
f
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Lumped Circuit or Transmission Line?
A) Determine frequency or bandwidth of the signal
-Microwave: f = operating frequency
0.35
-Digital: f =
rise time
B) Determine propagation velocity in medium, v,
next calculate wavelength l  v
f
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Lumped Circuit or Transmission Line?
C) Compare wavelength with dimensions (feature size)
d.
Case 1: If l >> d use lumped circuit equivalent
Total inductance = L x length
Total capacitance = C x length
Case 2: If l  10d or l < 10d, use transmission-line
model
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Frequency Dependence of Lumped
Circuit Models
Dimension Frequency Rise time
Printed circuit line
10 in
>55 MHz <7 ns
(epoxy, glass)
Package lead frame 1 in
>400 MHz <0.9 ns
(ceramic)
VLSI
interconnection*
100 mm
>8 GHz
<50 ps
(silicon)
* Using RC criterion for distributed effect
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Connector Design
• Minimize physical length of connector pins.
• Maximize the ratio of power and ground pins
to the signal pins. If possible these ratios
should be < 1.
• Place each signal pin as close as possible to a
current return pin.
• Place power pins adjacent to ground pins.
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8-Bit Connector Pin-Out Options
G
S
S
S
S
S
S
S
S
P
inferior
G
S
S
P
S
G
S
S
P
S
S
G
P
S
G
S
P
S
G
S
improved
G
S
P
S
G
S
P
S
S
G
P
S
More improved
G
P
S
G
P
S
G
P
S
G
P
S
G
P
S
G
G
P
S
G
P
S
G
P
Optimal
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Capacitive Crosstalk and Delay
Description
Capacitance
Units
Vertical parallel-plate capacitance
0.05
fF/mm2
Vertical parallel-plate capacitance (minimum width)
0.03
fF/mm
Vertical fringing capacitance (each side)
0.01
fF/mm
Horizontal coupling capacitance (each side)
0.03
fF/mm
A chip has a 2-mm-long data bus of 0.6-mm wires on
1.2mm centers. Use the table values. Assume that the
perpendicular wires on adjacent layers are all grounded.
Each driver can be modeled as a voltage source in series
with a 1-kW resistor. All lines switch simultaneously to
random states. What is the worst-case maximum and
minimum delay of a line.
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Capacitive Crosstalk and Delay
A chip has a 2-mm-long data bus of 0.6-mm wires on
1.2mm centers. Use the table values. Assume that the
perpendicular wires on adjacent layers are all grounded.
Each driver can be modeled as a voltage source in series
with a 1-kW resistor. All lines switch simultaneously to
random states. What is the worst-case maximum and
minimum delay of a line.
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Capacitive Crosstalk and Delay
The resistance of the wires are much smaller than
the 1kW of the drivers and thus can be ignored
Worst case condition which will cause maximum
delay is when the effective capacitance is maximum.
If the 2 side aggressor lines transition in the opposite
direction of the main driver on the victim line, this
will create the most amount of capacitance (Miller
effect)
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Typical TL Parameters and Coupling Coefficients
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Example
Full-swing (3.3V) CMOS signal with a fast 500 ps rise time next to a low-swing
(300 mV) signal for a 10 cm run of microstrip line. The lines are each 8 mils
wide spaced 6 mils above a ground plane and spaced 8 mils from one
another (see previous Table).Is the noise induced in the low-swing line a
concern?
– From table, we get kfx=-0.047, krx=0.058
Far end crosstalk
C=C+Cm=88+6.4=94.4 pF/m
L = 355 nH/m
1
1
v

1.73108 m/s
LC
94.4 pF / m355nH / m
ECE 546 – Jose Schutt-Aine
tx 
10cm
 0.578 ns
8
1.73  10
30
Example
In worst case, near- and far-end crosstalk will be added add
absolute values
Vxtalk  k fx  t x 
Vaggressor
t
 0.047  0.578ns 
 Vaggressor  krx  k r
3.3
 3.3  0.058 1  0.37 V
500 ps
0.37 V is bigger than 300 mV/2=150 mV  This will cause problem
to the system
Victim line also produces crosstalk on the agressor. However, only
second order effect is considered.
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Transmission Systems
Full-swing CMOS transmission system
Low-swing current-mode transmission system
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Transmission Systems
CMOS
LSC
Signaling
Voltage mode: 0=GND,
1=Vdd
Current mode: 0=-3.3 mA
1=+3.3 mA
Reference
Power supply: Vr~Vdd/2
Self-centered: Ir=0 mA
Termination
Series terminated in output
impedance of driver
Parallel-terminated at receiver
with RT within 10% of Zo
Signal energy
1.3 nJ
22 pJ
Power dissipation
130 mW
11mW
Noise immunity
1.2:1 actual:required signal
swing (with LSC receiver)
18 ns
3.6:1
Delay
6 ns
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Transmission Systems
CMOS
VOH
VOL
VIH
VIL
VMH
VML
CMOS
LSC
(V)
(mV)
0.3
0.0
2.2
1.1
1.1
1.1
(mV)
165
-165
10
-10
155
155
Receiver sensitivity
Receiver offset
Power supply noise
Total noise (swing-independent)
CMOS
(%)
Self-induced power supply noise (Kin)
Crosstalk from other signals (Kxt)
Reflections of the same signal
from previous clock cycles (Kr)
Transmitter offset (Kto)
Total proportional noise fraction (KN)
300
250
300
850
LSC
(mV)
10
10
3
23
LSC
(%)
10
0
250
10
large(>5) 5
10
>35
ECE 546 – Jose Schutt-Aine
10
25
34
CMOS vs LSC
• With the worst-case combinations of noise
sources the CMOS signaling system will fail
• The LSC system has 3.6 times the signal
swing required.
• The transmission delay of the LSC system is
the one-way delay of the transmission line.
• The CMOS driver must wait for the line to
ring up to the full voltage.
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CMOS vs LSC
• Basic CMOS system is most commonly used
and yet is far from optimal
• Large energy signal is used where it is not
needed
• Transmitted signal not isolated from supply
noise
• Receiver uses reference that changes
significantly with process variations
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Signaling Modes for Transmission Lines
- Signal return impedances ZRT and ZRR
- Coupling to local power supply ZGT and ZGR
- Introduce noise VN
- Sections can be separated if TL is terminated into match impedance
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Transmitter Signaling Parameters
• Output impedance, Ro
• Coupling between signal and power
supply ZGT
• Polarity of signal
• Amplitude of signal
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Current-Mode Transmission
 x
V (t , x)  IT  t   Z o
 v
Provides isolation of both the signal and current
return from the local power supplies
- Large ZGT
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Voltage-Mode Transmission
 x
V (t , x)  VT  t  
 v
Makes a difference in:
- Signal return crosstalk
- Single power supply noise
ECE 546 – Jose Schutt-Aine
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Current- & Voltage-Mode Transmission
Current-Mode Transmission
Output impedance >> Zo
Voltage-Mode Transmission
Output impedance << Zo
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Transmitter Signal-Return Crosstalk
• A signal return path is typically shared among a
group of N signals (typically 2 to 8) to reduce cost.
• Sharing occurs at both ends of line.
• ZRT approximates the return path impedance at the
transmitter end.
• The return current from all N transmission lines
passes through impedance ZRT.
• The current IT1 = VT1/Zo sees the shared return
impedance in parallelwith the series combinationof
the line and output impedances from other signals.
• The total return impedance is ZX.
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Transmitter Signal Return Crosstalk
ZRT
VT1
VT2
RO
RO
VTN
RO
+
VL
-
Z RT  RO  Z O 
 R  ZO 
Z X  Z RT  O


 N  1   N  1 Z RT  RO  Z O
Current through each of the N-1 line impedance is:


 ZX 
Z RT
I X  IT 1 

  IT 1 
R

Z
N

1
Z

R

Z


O 
RT
O
O 
 O

Induced voltage across line impedance is:


Z RT
VX  I X Z O  VT 1 

N

1
Z

R

Z


RT
O
O


Considering worst case where N-1 signals switch simultaneously
ZO
ZO
ZO
K XRT 
 N  1 Z RT
 N  1 Z RT
( N  1)VX


VT 1
 N  1 Z RT  RO  ZO RO  ZO
With voltage-mode signaling, Ro=0, the transmitter signal
return crosstalk is a maximum. For current-mode signaling,
Ro is infinite and this form of crosstalk is eliminated.
ECE 546 – Jose Schutt-Aine
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Receiver Signal Return Crosstalk
K XRR 
 N  1 Z RR
( N  1) Z RR

( N  1) Z RR  2 Z O
2ZO
- All N terminators return their current through ZRR (shared
impedance)
- No crosstalk advantage to current-mode signaling
- TL is like a matched source
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Power Supply Noise


ZO Z R
VRN  VN 

2
Z
Z

2
Z

Z
Z


O
R
N 
 O R
- if ZR << Zo
VRN 
VN Z R
2 ZR  ZN 
To reject power supply noise, ZN=ZGT+ZGR must be made
as large as possible. This is accomplished by using a
current-mode transmitter.
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Nonideal Return Paths
• A nonideal return path will appear as an inductive
discontinuity
• A nonideal return path will slow the edge rate by
filtering out high-frequency components
• If the current divergence path is long enough, a
nonideal return path will cause signal integrity
problems at the receiver
• Nonideal return paths will increase current loop area
and exacerbate EMI
• Nonideal return paths may significantly increase the
coupling coefficient between signals
ECE 546 – Jose Schutt-Aine
46
Signal Return Crosstalk
• Return crosstalk can be reduced with rise-time
control
• As rise times get faster, every signal requires its own
return  might as well use differential signaling
• With voltage-mode signaling, the transmitter signal
return crosstalk is a maximum
• High output impedance offers advantage and reduces
transmitter return crosstalk
• For current-mode signaling, this form of crosstalk is
completely eliminated
ECE 546 – Jose Schutt-Aine
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Application: Return Signal Optimization
Voltage-mode signaling with Zo=50 W and rise time tr=2 ns and
ZRT dominated by 5 nH inductance.
Approximate ZRT=L/tr= 2.5 W
Want kXRT = 0.1
Solving for N shows that we will need 1 return for every 3 signal
traces to meet the spec.
If the rise time is decreased to 1 ns, we will need 1 return for every
2 signal line to keep the same spec
If the rise time is lower than 1 ns, we will need 1 return for every
signal  might as well use differential signaling
ECE 546 – Jose Schutt-Aine
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Ringback and Rise Time Control
•
•
•
•
Violation into threshold region
Detrimental even if threshold is not crossed
Can exacerbate ISI
Can be aggravated by nonlinear (time varying)
terminations
• Can increase skew between signals
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Signaling Over Lumped RLC Interconnect
Q: high

1  R 


LC  2 L 
2
Q: medium
 RT 
VR (t )  1  exp  
 cos( t )
2
L


Q: low
Q
1 L
R C
ECE 546 – Jose Schutt-Aine
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Example
ZO=RT=50W
RO=1 kW
CN=5 pF
LR=5 nH
VN=500 mV
Determine the amount of supply noise VN that appears
across RT as a function of frequency. How much signal
swing is required to keep the power-supply noise less than
10% of the signal swing across the spectrum from DC to
1GHz
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Example
VRN 
VN  ZO j LR 
2ZO j LR   2Z O  j LR  jC 
1
VN 4 2 ZO LRCf 2
 2
8 ZO LRCf 2  2ZO  2 fLR
2.5  1018 f 2

98.5  1018 f 2  100  j 31.4  109 f
We want 0.1 Vs > VRN  VS > 10VRN
ECE 546 – Jose Schutt-Aine
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Required Voltage Swing
0.08
|VS| (Volts)
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
0
1
2
3
4
5
6
7
8
9
10
X 108
ECE 546 – Jose Schutt-Aine
f (Hz)
53
Voltage Reference Uncertainty
Vref + uncertainty
Vih
Threshold region
Threshold
Vil
Vref - uncertainty
Time
Major Contributors
•
•
•
•
•
Power supply effects (SSN, ground bounce, rail collapse)
Noise from IC
Receiver transistor mismatches
Return path discontinuities
Coupling to reference voltage circuitry
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Efficient Bus Design Methodology
Spreadsheets & metrics
Signal categories
Topology options
Sensitivity analysis
Reference design
Routing guidelines
Buffer guidelines
Fix
Simulation of design
Pass
Design check
Fail
Tapeout
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55
Bus System Variables
•
•
•
•
•
•
•
•
I/O capacitance
Trace length, velocity, and impedance
Interlayer impedance variations
Buffer strengths and edge rates
Termination values
Receiver setup and hold times
Interconnect skew specifications
Package, daughtercard, and parameters
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56
Differential vs Single-Ended
Line impedance: Zo = 50 W
Source Resistance: Ro= 50 W
Lead Inductance: L = 5 nH
Pin count: P = 32
Data rate: TBR = 8GB/s
S+N=P
S*B=TBR
 N  1 Z
K 
XRT
B: Bit rate per signal pin
TBR: Total bit rate
S: Number of signal pins
N: Number of return pins
RT
RO  Z O
ZRT is due to the lead inductance
ZRT  ZRT/N since there are N ground pins
Need to determine S and N
ECE 546 – Jose Schutt-Aine
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Coupled Transmission Lines
w
er
h
V1
I1
Cm
I2
s
Cs
Lm
V2
Cs
ECE 546 – Jose Schutt-Aine
58
Even Mode
Ve
I e

  L11  L12 
z
t
I e
I e

  C11  C12 
z
t
Add voltage
and current
equations
1
Ve : Even mode voltage Ve = (V1 + V2 )
2
1
Ie : Even mode current Ie = (I1 + I2 )
2
Ze =
L11 + L12
=
C11 + C12
Ls + Lm
Cs
ve =
1
=
(L11 + L12 )(C11 + C12 )
Impedance
1
(Ls + Lm )Cs
ECE 546 – Jose Schutt-Aine
velocity
59
Odd Mode
Vd
I d

  L11  L12 
z
t
I
I
 d   C11  C12  d
z
t
Subtract voltage
and current
equations
Vd : Odd mode voltage
Id : Odd mode current
Zd =
vd =
L11  L12
Ls  Lm
=
C11  C12
Cs  2Cm
1
=
( L11  L12 )(C11  C12 )
1
Vd  V1  V2 
2
1
Id   I1  I 2 
2
Impedance
1
( Ls  Lm )(Cs  2Cm )
ECE 546 – Jose Schutt-Aine
velocity
60
Mode Excitation
+1
+1
EVEN
-1
+1
ODD
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61
PHYSICAL SIGNIFICANCE OF EVEN- AND
ODD-MODE IMPEDANCES
* Ze and Zd are the wave resistance seen by the even
and odd mode travelling signals respectively.
* The impedance of each line is no longer described
by a single characteristic impedance; instead, we have
V1 = Z11 I1 + Z12 I 2
V2 = Z21 I1 + Z22 I2
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62
Definitions
Even-Mode Impedance: Ze
Impedance seen by wave propagating through the coupledline system when excitation is symmetric (1, 1).
Odd-Mode Impedance: Zd
Impedance seen by wave propagating through the coupledline system when excitation is anti-symmetric (1, -1).
Common-Mode Impedance: Zc = 0.5Ze
Impedance seen by a pair of line and a common return by a
common signal.
Differential Impedance: Zdiff = 2Zd
Impedance seen across a pair of lines by differential mode
signal.
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63
Mutual Impedances
Z11, Z22 : Self Impedances
Z12, Z21 : Mutual Impedances
For symmetrical lines,
Z11 = Z22 and Z12 = Z21
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64
Even and Odd Modes
vd =
1
( Ls  Lm )(Cs  2Cm )
ve =
1
( Ls  Lm )Cs
Ls  Lm
Zd =
Cs  2Cm
Ze =
Ls  Lm
Cs
In general, odd-mode impedance is smaller than evenmode impedance.
In general, odd-mode velocity is larger than even-mode
velocity.
ECE 546 – Jose Schutt-Aine
65
Coupled Lines
Line Space
Modal Space
V1  Z11I1  Z12 I 2
Ve  Ze I e
V2  Z 21I1  Z 22 I 2
Vd  Z d I d
V1   Z11
V    Z
 2   21
Z12   I1 
Z 22   I 2 
Ve   Z e
V    0
 d 
ECE 546 – Jose Schutt-Aine
0   Ie 
Z d   I d 
66
Example - Microstrip
Cricket
userdict
/mypsb
currentpoint
/newXScale
/newYScale
/psb
/pse
{}Software
/mypsb
/mypse
store
/psb
/mdnewHeight
/picOriginY
pop
/newHeight
newWidth
/pse
load
known{/CricketAdjust
/newWidth
{}
def
store
store
/mypse
111
18
exch
div
div
exch
def
/pse
picOriginY
def
def
/picOriginX
picOriginX
load
true def}{/CricketAdjust
def
sub sub
def
exch
pop
def
def
false def}ifelse
er = 4.3
Zs = 56.4 W
Single Line
Dielectric height = 6 mils
Width = 8 mils
Coupled Lines
Height = 6 mils
Cricket
Width
= 8 mils
userdict
/mypsb
currentpoint
/newXScale
/newYScale
/psb
/pse
{}Software
/mypsb
/mypse
store
/psb
/mdnewHeight
/picOriginY
pop
/newHeight
newWidth
/pse
load
known{/CricketAdjust
/newWidth
{}
def
store
store
/mypse
111
18
exch
div
div
exch
def
/pse
picOriginY
def
def
/picOriginX
picOriginX
load
true def}{/CricketAdjust
def
sub sub
def
exch
pop
def
def
false
def}ifelse
Spacing = 12 mils
er = 4.3
Ze = 68.1 W Zd = 40.8 W
Z11 = 54.4 W Z12 = 13.6 W
ECE 546 – Jose Schutt-Aine
67
Even Mode
Zg
Vf
IT
I1
Zg
+
Vb VT I
step
2
generator
coaxial line
I tdr
line 1
line 2
reference plane tied to ground
 ae (t ,0) ad (t ,0)   ae (t ,0) ad (t ,0) 






Z
Z
Z
Z
e
d
e
d

 

Vtdr  ae (t ,0)  ad (t ,0)
Vtdr Z e
=
I tdr
2
1  e
Ze = 2(
) Zg
1  e
ECE 546 – Jose Schutt-Aine
a d (t ,0)  0
ve =
2l
e
68
Odd Mode
Vtdr  ae (t ,0)  ad (t ,0) -  ae (t ,0) - ad (t ,0)   V f  Vb
I tdr
 ae (t ,0) ad (t ,0) 
= 


Z
Z
e
d


ae (t,0) = 0,
1  1  d
Zd  
2  1  d
I tdr
 ae (t ,0) ad (t ,0) 
=- 


Z
Z
e
d


Vtdr
= 2Zd
Itdr

 Zg ,

vd =
ECE 546 – Jose Schutt-Aine
2l
d
69
Measured Even-Mode Velocity
Even-Mode velocity
0.17
h=3 mi ls
h=5 mi ls
0.168
h=7 mi ls
h=10 m ils
0.166
v e(m /ns)
h=14 m ils
0.164
h=21 m ils
0.162
0.16
0.158
4
6
8
10
12
14
16
18
Sp acing (m ils )
ECE 546 – Jose Schutt-Aine
70
Measured Odd-Mode Velocity
h=3 mi ls
h=5 mi ls
Odd-Mode Velocity
0.21
h=7 mi ls
h=10 m ils
0.205
h=14 m ils
0.2
h=21 m ils
v (m/ ns)
d
0.195
0.19
0.185
0.18
0.175
4
6
8
10
12
14
16
18
Spacing (mi ls)
ECE 546 – Jose Schutt-Aine
71
Even and Odd-Mode Impedances
Typical Even & Odd Mode Impedances
110
Zeven
Zodd
Zeven, Zodd (Ohms)
100
90
80
70
60
50
40
10
20
30
40
50
Distance (mils)
ECE 546 – Jose Schutt-Aine
72
Measured Odd-Mode Impedance
h=3 mi ls
Odd-Mode Impedance
h=5 mi ls
50
h=7 mi ls
45
h=10 m ils
h=14 m ils
Z ( W)
d
40
h=21 m ils
35
30
25
20
4
6
8
10
12
14
16
18
Spacing (mi ls)
ECE 546 – Jose Schutt-Aine
73
Measured Even-Mode Impedance
Even-Mode Impedance
12 0
h=3 mi ls
h=5 mi ls
h=7 mi ls
10 0
h=10 m ils
Z ( W)
e
80
h=14 m ils
h=21 m ils
60
40
20
4
6
8
10
12
14
16
18
Spacing (mi ls)
ECE 546 – Jose Schutt-Aine
74
Virtual Reference Plane
Electric field is perpendicular
to virtual plane
For odd modes,
there exists a
virtual reference
plane between the
conductors
Electric Field
Magnetic field is
tangent to virtual plane
Magnetic Field
Virtual reference plane
ECE 546 – Jose Schutt-Aine
75
Low-Voltage Differential Signaling
(LVDS)
Definition: Method to communicate data using a very
low voltage swing (about 350mV) differentially over
two PCB traces or a balanced cable
Criteria for high-performance communication
- Bandwidth
- Low Power
- Low Noise
Solution exists for very short and very long distances;
however for board-to-board or box-to-box, this is a challenge
ECE 546 – Jose Schutt-Aine
76
Why LVDS?
1. Differential transmission is less
susceptible to common mode noise
2. Consequently they can use lower
voltage swings
3. In PC board (microstrip) odd-mode
propagation is faster
ECE 546 – Jose Schutt-Aine
77
LVDS Attributes for EMI
1. Low output voltage swing
2. Slow edge rates
3. Odd-mode operation (magnetic fields cancel)
4. Soft output corner transitions
ECE 546 – Jose Schutt-Aine
78
LVDS Driver and Receiver
- Majority of current flows across 100-ohm resistor
- Switching changes the direction of current
- Logic state determined by current direction
ECE 546 – Jose Schutt-Aine
79
LVDS Standard
• Maximum Switching Speed
– Depends on line driver
– Depends on selected media (type and length)
• LVDS Saves Power
– Power dissipated in load is small
– LVDS devices are in CMOS=>low static power
– Lowers system power through current-mode
• Design Practices
– Matching is critical
– Preserve balance
ECE 546 – Jose Schutt-Aine
80
Differential Signaling Technologies
Differential Driver Output Voltage
Receiver Input Threshold
Data Rate
Supply Current Quad Driver (no load, static)
Supply Current Quad Receiver (no load, static)
Propagation Delay of Driver
Propagation Delay of Receiver
Pulse Skew (Driver or Receiver)
RS-422
2 to 5V
200 mV
<30Mbps
60 mA (max)
23mA (max)
11ns (max)
30ns (max)
N/A
ECE 546 – Jose Schutt-Aine
PECL
600-1000 mV
200-300mV
>400Mbps
32-65mA (max)
40mA (max)
4.5ns (max)
7.0ns (max)
500ps (max)
LVDS
250-450 mV
100 mV
>400Mbps
8.0mA
15mA (max)
1.7ns (max)
2.7ns (max)
400ps (max)
81