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ECE 331 – Digital System Design Power Dissipation and Additional Design Constraints (Lecture #14) The slides included herein were taken from the materials accompanying Fundamentals of Logic Design, 6th Edition, by Roth and Kinney, and were used with permission from Cengage Learning. Material to be covered … Supplemental Chapter 8: Sections 1 – 5 Fall 2010 ECE 331 - Digital System Design 2 Power Dissipation Fall 2010 ECE 331 - Digital System Design 3 Power Dissipation • Each integrated circuit (IC) dissipates power • PT = PS + PD Fall 2010 – PT = total power dissipated by IC – PS = static or quiescent power dissipation – PD = dynamic power dissipation ECE 331 - Digital System Design 4 Static Power Dissipation • PS = VCC * ICC – VCC = supply voltage – ICC = quiescent supply current – PS = static power consumption • ICC and VCC are specified in the datasheet for the integrated circuit (IC). • For CMOS devices, PS is very small. Fall 2010 ECE 331 - Digital System Design 5 74LS00 Datasheet Fall 2010 ECE 331 - Digital System Design 6 Static Power Dissipation • Example: 74LS00 (Quad 2-input NAND) – Supply voltage • – – Fall 2010 4.75 V <= VCC <= 5.25 V Supply current • High output: ICCmax = 1.6 mA • Low output: ICCmax = 4.4 mA Maximum static power dissipation • High output: • Low output: PS = 8.4 mW PS = 23.1 mW ECE 331 - Digital System Design 7 Static Power Dissipation – Duty Cycle • – Fall 2010 Clock signal typically has 50% duty cycle PS = PS_high * thigh + PS_low * tlow • PS_high = 8.4 mW • PS_low = 23.1 mW • Assume 50% duty cycle (high / low half the time) • PS = 8.4 mW * 0.5 + 23.1 mW * 0.5 = 15.8 mW • Assume 60% duty cycle (high 60% of the time) • PS = 8.4 mW * 0.6 + 23.1 mW * 0.4 = 14.28 mW ECE 331 - Digital System Design 8 Dynamic Power Dissipation For TTL devices, PD is negligible compared to PS. For CMOS devices, PD dominates PT. Assume PS = 0 PD >> PS PD in CMOS circuits arises from the movement of charge into and out of the device capacitance. Fall 2010 ECE 331 - Digital System Design 9 Dynamic Power Dissipation In CMOS devices, charge is stored in the CPD = power dissipation capacitance (internal) CL = capacitance of the load and wires (external) These capacitors are in parallel CT = CPD + CL The stored charge (on these capacitors) is Fall 2010 QT = CT * VDD = (CPD + CL) * VDD ECE 331 - Digital System Design 10 Dynamic Power Dissipation The charge moves into and out of the capacitors on every transition of the output. Low → High High → Low Current = movement of charge IAVG = (CPD + CL) * VDD * fT Where fT = output frequency PD = IAVG * VDD = (CPD + CL) * V2DD * fT Fall 2010 ECE 331 - Digital System Design 11 74HC00 Datasheet Fall 2010 ECE 331 - Digital System Design 12 Dynamic Power Dissipation Example: 74HC00 (Quad 2-input NAND) VDD = 5V CPD = 20 pF, CL = 50 pF PD = (20 + 50 pF) * (5V)2 * fT Fall 2010 fT (Hz) PD 1K 1.8 mW 1M 1.8 mW 100M 180 mW ECE 331 - Digital System Design 13 74HC00 Datasheet Fall 2010 ECE 331 - Digital System Design 14 Total Power Dissipation For the 74HC00, PS is determined as follows VCC = 5V ICC = 20 mA PS = VCC * ICC = 5V * 20 mA = 100 mA The PT is then determined from Fall 2010 PT = PS + PD where PD is a function of fT ECE 331 - Digital System Design 15 Total Power Dissipation • PT = PS + PD • Compare PT for Quad 2-input NAND (74xx00) • 0 Hz 1 MHz 100 MHz TTL 15.8 mW 15.8 mW 15.8 mW CMOS 100 mW 1.805 mW 180 mW Compare TTL and CMOS Fall 2010 TTL CMOS PS VCC * ICC VDD * IDD PD ~0W (CPD + CL) * V2DD * fT ECE 331 - Digital System Design 16 Hazards Fall 2010 ECE 331 - Digital System Design 17 Hazards When the input to a combinational logic circuit changes, unwanted switching transients may appear on the output. These transients occur when different paths from input to output have different propagation delays. Fall 2010 ECE 331 - Digital System Design 18 Hazards Fall 2010 ECE 331 - Digital System Design 19 Hazards When analyzing combinational logic circuits for hazards we will consider the case where only one input changes at a time. Under this condition, a static 1-hazard occurs when the input change causes one product term (in a SOP expression) to transition from 1 to 0 and another product term to transition from 0 to 1. Both product terms can be transiently 0, resulting in the static 1-hazard. Fall 2010 ECE 331 - Digital System Design 20 Hazards Under the same condition, a static 0-hazard occurs when the input change causes one sum term (in a POS expression) to transition from 0 to 1 and another sum term to transition from 1 to 0. Both sum terms can be transiently 1, resulting in the static 0-hazard. Fall 2010 ECE 331 - Digital System Design 21 Detecting Static 1-Hazards We can detect hazards in a two-level AND-OR circuit using the following procedure: 1. Write down the sum-of-products expression for the circuit. 2. Plot each term on the map and loop it. 3. If any two adjacent 1′s are not covered by the same loop, a 1-hazard exists for the transition between the two 1′s. For an n-variable map, this transition occurs when one variable changes and the other n – 1 variables are held constant. Fall 2010 ECE 331 - Digital System Design 22 Detecting Static 1-Hazards Fall 2010 ECE 331 - Digital System Design 23 Removing Static 1-Hazards redundant, but necessary to remove hazard Fall 2010 ECE 331 - Digital System Design 24 Detecting Static 0-Hazards We can detect hazards in a two-level OR-AND circuit using the following procedure: 1. Write down the product-of-sums expression for the circuit. 2. Plot each sum term on the map and loop the zeros. 3. If any two adjacent 0′s are not covered by the same loop, a 0-hazard exists for the transition between the two 0′s. For an n-variable map, this transition occurs when one variable changes and the other n – 1 variables are held constant. Fall 2010 ECE 331 - Digital System Design 25 Detecting Static 0-Hazards Fall 2010 ECE 331 - Digital System Design 26 Removing Static 0-Hazards How many redundant gates are necessary to remove the 0-hazards? Fall 2010 ECE 331 - Digital System Design 27 Hazards Exercise: Design a hazard-free combinational logic circuit to implement the following logic function F(A,B,C) = A'.C' + A.D + B.C.D' Fall 2010 ECE 331 - Digital System Design 28 Hazards Exercise: Design a hazard-free combinational logic circuit to implement the following logic function F(A,B,C) = (A'+C').(A+D).(B+C+D') Fall 2010 ECE 331 - Digital System Design 29 Hazards Two-level AND-OR circuits (SOP) cannot have static 1-Hazards. Why? Two-level OR-AND circuits (POS) cannot have static 0-Hazards. Fall 2010 Why? ECE 331 - Digital System Design 30 Questions? Fall 2010 ECE 331 - Digital System Design 31