Download A 10nW 12-bit Accurate Analog Storage Cell with 10aA Leakage

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 11, NOVEMBER 2004
1985
A 10-nW 12-bit Accurate Analog Storage Cell
With 10-aA Leakage
Micah O’Halloran and Rahul Sarpeshkar, Member, IEEE
Abstract—Medium-term analog storage offers a compact,
accurate, and low-power method of implementing temporary
local memory that can be useful in adaptive circuit applications.
The performance of these cells is characterized by the sampling
accuracy and voltage droop that can be achieved with a given
level of die area and power. Hand calculations suggest past implementations have not achieved minimum voltage droop due to
uncompensated MOS leakage mechanisms. In this paper, the dominant sources of MOS leakage are experimentally characterized
in a standard 1.5- m CMOS process using an on-chip current
integration technique, focusing specifically on the 1 fA to 1 aA
current range. These measurements reveal an accumulation-mode
source-drain coupling mechanism that can easily dominate diode
leakage under certain bias conditions and may have limited
previous designs. A simple rule-of-thumb is offered for avoiding
this leakage effect, leading to a novel ultra-low leakage switch
topology. A differential storage cell incorporating this new switch
achieves an average leakage of 10 aA at room temperature, an
8 reduction over past designs. The cell loses one bit of voltage
accuracy, 700 V on a 12-bit scale and 11.3 mV on an 8-bit scale,
in 3.3 and 54 min, respectively. This represents a 15 increase in
hold time at these voltage accuracies over the lowest leakage cell to
date, in only 92% of the area. Since the leakage is independent of
amplifier bias, the cell can operate on as little as 10 nW of power.
Initial measurements also indicate the switch’s leakage decreases
with the square of process feature size.
Index Terms—Accumulation, analog memory, analog storage,
attoamp, junction leakage, leakage, low-leakage switch, sampleand-hold, subthreshold, ultra-low current, weak inversion.
I. INTRODUCTION
M
ANY modern analog CMOS circuits employ temporary
analog storage to counteract circuit offsets and store
signal variables [1], and implement adaptation and learning
[2], [3]. Offset correction and signal storage are the most
common applications of temporary analog storage due to their
widespread use in switched capacitor circuits, and both can be
easily implemented using only a capacitor and a MOS switch.
This form of storage is a very compact, low-power, and precise
storage technique, but is useful only for short time scales since
the OFF state leakage of the MOS switch quickly degrades the
stored charge [2].
Medium-term capacitive storage cells extend the storage time
of short-term cells by reducing MOS switch leakage, and are
Manuscript received November 18, 2003; revised May 7, 2004. This work
was supported by the Center for Bits and Atoms NSF Research Grant under NSF
CCR-0122419, the Office of Naval Research under Award N00014-02-1-0434,
the Catalyst Foundation, the Packard Foundation, and the Swartz Foundation.
The authors are with the Department of Electrical Engineering and Computer
Science, Massachusetts Institute of Technology, Cambridge, MA 02139 USA
(e-mail: [email protected]; [email protected]).
Digital Object Identifier 10.1109/JSSC.2004.835817
often used in adaptive circuit design. Many leakage-reduction
techniques have been proposed in the literature [4]–[8]. However, none of these references has presented experimental work
focused specifically on characterizing the switch leakage as a
function of terminal voltages. As a result, it is not clear if the
leakages achieved in these implementations are optimal, and if
not, how they may be further reduced.
Long-term cells extend the storage times of short-term
cells by completely counteracting MOS leakage rather than
simply reducing it. Some cells counteract leakage by periodically quantizing the capacitor voltage using some form of
analog-to-digital conversion [2], [3], [6], [9], [10]. This scheme
has the disadvantages of added circuit complexity and power
due to both the analog-to-digital converter and the bussing
required for multiplexing the converter between cells. A second
long-term storage approach is to eliminate the MOS switch
altogether by employing floating-gate technology [2], [3], [11],
[12]. The disadvantages of this scheme are that it requires high
voltages for writing to the cells, exhibits slow write times,
and requires additional supporting circuitry and bussing to
accomplish the writing [2].
This paper focuses on extending the hold time of mediumterm storage cells. It is argued in Section II that past mediumterm techniques have most likely not minimized MOS drain
leakage. Then the primary sources of drain leakage in MOS
transistors are experimentally verified in a 1.5- m process, and
an important accumulation-mode conduction mechanism that
has not been accounted for in previous designs is characterized.
Section III introduces a new ultra-low leakage switch structure
based on leakage results from Section II and uses it in the design of two new analog storage cells. Measurements from the
fabricated cells are presented in Section IV. Finally, Section V
concludes the paper.
II. LOW-LEAKAGE MOS SWITCH DESIGN
A. Motivation
As was mentioned above, medium-term analog storage cells
achieve extended hold times by reducing the MOS-switch
leakage current that degrades the cell’s capacitively held
charge. In the literature, the lowest-leakage storage cell implementations have employed several different techniques to
reduce switch leakage. These techniques are briefly reviewed
below, and then a unified framework for comparing the performance of past implementations, which were fabricated in
various technologies, is introduced. This comparison motivates
the remainder of the section.
0018-9200/04$20.00 © 2004 IEEE
1986
Fig. 1. Two low-leakage MOS switches.
Two low-leakage switch topologies that have been used in
previous analog storage cells are shown in Fig. 1. Part (a) shows
and
a transmission gate switch and two leakage currents,
, that can flow to
even when the switch is off.
flows from
to ground through the NMOS drain-to-bulk
flows from
to
through the PMOS
diode and
drain-to-bulk diode. Since only the difference between these two
, reaches
, it is possible to ratio the
leakage currents,
junction areas to counterbalance these leakages to first order.
Note that a given junction area ratio minimizes the net leakage
, however typical high-perfor only one particular value of
formance storage cell topologies ensure this voltage remains
fixed, independent of the stored analog voltage, allowing the
. This strucarea ratio to be optimized for one value of
ture was implemented in 2 m CMOS in [6] and exhibited
a net leakage current of 1 fA (all currents are inferred from
measured memory cell voltage leakage rates and storage capacitor sizes). In [5], the same structure implemented in 1.2 m
CMOS yielded 4.5 fA of leakage current, while a fully differential storage cell, which only responds to differential leakage,
used a pair of these low-leakage transmission gates to achieve a
net differential leakage of 0.08 fA.
A second low-leakage switch topology is shown in Fig. 1(b).
The switch is formed by a single transistor, in this case an
NMOS, fabricated inside a well to allow the transistor bulk
voltage to differ from the substrate voltage. A disadvantage of
this switch is that it lacks the rail-to-rail input-output range of
a transmission gate. However, as was mentioned above, typical
to remain constant making
storage cell topologies force
this limitation irrelevant as long as
is chosen within the
conallowable range of the switch. Additionally, with
stant, the bulk can be driven with an identical voltage
to minimize the drain-to-bulk diode leakage. In [7], NMOS
versions of this low-leakage switch structure were used in a
fully differential storage cell implemented in 3- m CMOS.
The cell also attempted to minimize subthreshold leakage by
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 11, NOVEMBER 2004
driving the transistor gates below the bulk to turn them off, and
achieved a typical net differential leakage of 1.6 fA.
It is instructive to compare these measured leakages with
back-of-the-envelope estimates of what could theoretically be
achieved in each technology. Suppose the switch is implemented
using a single minimum-sized MOS transistor and all MOS-related switch leakage, such as subthreshold conduction, is eliminated. Then the only remaining leakage would be due to the
drain-to-bulk junction diode. The fully reverse-biased leakage
per unit area of this junction in a modern process is roughly 0.02
fA m at room temperature, with this value having decreased
by a factor of two to three in the past ten years as technology
has improved [13]. Using appropriately scaled versions of this
nominal leakage parameter for older processes, the estimated
in MOSIS scalable design
leakage of a minimum-sized (
rules) reverse-biased drain-to-bulk diode in each technology of
interest is calculated in Table I.
Before these estimates of nominal leakage current can be
compared to the measured results from above, the leakage-reduction techniques employed in each implementation must be
taken into account. The following assumptions will be made
about the effectiveness of the techniques employed. It will be assumed that both counterbalancing NMOS and PMOS leakages
and implementing the storage cell differentially achieve 80%
matching accuracy, and therefore applying either technique will
reduce the leakage to 20% of its starting value. Drain-to-bulk
voltage minimization is typically accomplished using an amplifier in feedback [7], and therefore brings the two terminals no
closer than the input-offset voltage of the amplifier employed,
which will be assumed to be 5 mV. This level of bias across the
diode can be shown to yield an 80% reduction in diode current
when compared to full reverse-bias [see (2)].
Applying the relevant reduction factors from above to the
nominal reverse-biased diode leakages from Table I, a conservative upper bound on the leakage current expected in each implementation is calculated in Table II. Also listed in the table are the
currents that were measured in each implementation, which in
all cases are at least 2.5 times larger than the generous estimates
of the leakage upper bounds. These results suggest that additional leakage mechanisms, probably due to the MOS structure,
exist and have not been compensated for in these implementations.
In the remainder of this section, the dominant sources of
leakage in MOS devices are characterized in a standard 1.5- m
CMOS n-well double-poly process. The goal of these measurements is to establish a list of guidelines that should be followed
to achieve minimum switch leakage and thus maximum storage
times with a given capacitance. The measurements also reveal
an important MOS leakage mechanism that has not been considered in previous designs.
B. Leakage Test Structure and Test Procedure
Direct measurement of sub-pA level currents is tedious to
perform in the laboratory, even with a sufficiently accurate
electrometer. At these current levels, the resistance of many
common laboratory insulators is nonnegligible, requiring
careful design of the entire test setup to ensure insulator
leakage does not affect the measurement. Additionally, external
O’HALLORAN AND SARPESHKAR: A 10-nW 12-bit ACCURATE ANALOG STORAGE CELL WITH 10-aA LEAKAGE
1987
TABLE I
ESTIMATED REVERSE-BIAS LEAKAGE CURRENT OF MINIMUM-SIZED DRAIN-TO-BULK
JUNCTIONS FOR SEVERAL TECHNOLOGIES. THE PRE-CONSTANTS IN THE LEAKAGE
PER UNIT AREA COLUMN ARE INCLUDED TO ROUGHLY ACCOUNT
FOR TECHNOLOGY AGE [13]
TABLE II
ESTIMATED UPPER BOUND ON LEAKAGE AND ACHIEVED LEAKAGE FOR THREE MEMORY CELLS
Fig. 2.
MOS leakage test structure.
electrical interference must be completely eliminated as even
faint signals can easily corrupt the measurement. Within an
integrated circuit, however, fA-level currents can be accurately conveyed across the die [13], and the entire die can be
shielded from interference by placing it in a grounded metal
box. Because of these facts, measuring MOS leakage currents
using on-chip circuitry can yield a level of accuracy that may
be difficult to achieve with an off-chip electrometer. As was
alluded to earlier, capacitive current integration offers a simple
on-chip mechanism for indirectly measuring low current levels.
It avoids off-chip error sources by first time-integrating the
small current within the low-noise on-chip environment to yield
voltage movements of a sufficient magnitude that they can be
reliably measured in the noisy off-chip environment.
The current-integrator leakage tester shown in Fig. 2 conand a PMOS-input fully
sists of an integrating capacitor
cascoded wide-output swing operational transconductance amplifer (OTA). In this figure the device under test (DUT) is an
NMOS transistor, but the same structure was also used to characterize PMOS leakage. The current-integrator topology, when
built using a high-gain amplifier, possesses several key features
that are important to the operation of the leakage tester. First,
(plus the
the negative input terminal of the OTA servos to
OTA’s input-offset voltage) as long as the amplifier output is not
railed, which allows for indirect control of , the DUT drain
that flows into the DUT drain
voltage. Second, any current
will be immediately integrated on
, causing a change in
but virtually no change in . Third, the rate of change of
is related to
and
by
(1)
independent of capacitances from
and
to ground.
Finally, a constant-current load at the integrator output due to
causes only a constant
an off-chip instrument monitoring
voltage offset error, which has no effect on the measured
.
Using the leakage tester presented above, the DUT drain current can be evaluated as a function of the four MOS terminal
voltages by iteratively applying the following procedure. At the
start of each test run, initialize the leakage tester so that the four
terminals of the DUT are at the required test voltage levels, and
the output of the integrator sits halfway between the circuit rails,
. This initialization is accomplished by temporarily
at
1988
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 11, NOVEMBER 2004
using the DUT as a switch to reset the voltage across
. After
with an
initialization, measure the time rate-of-change of
off-chip electrometer. Using this slope measurement and the
, the current
can be indirectly evaluated using
value of
(1).
In order to obtain accurate results with the leakage tester,
must be accurately known. Therefore, a capacitor calibration
structure was implemented on each of the test die using two
and
, with nominally identical package-repackage pins,
’s associated die-level bond pad was
lated capacitances. Pin
, whose
connected to the top plate of a calibration capacitor,
layout is identical to that of
. The bottom plate of
was grounded. Pin
’s associated die-level bond pad was not
connected to any other die-level structure. By measuring the
and
, an estimate of
difference in capacitance between
(and thus
) can be obtained that should be independent
of package and die-level parasitic capacitances to first order.
Using this calibration structure and an LCR meter, the fabricated
were all measured to lie in the range
pF
values of
pF. The median value of
pF was used to infer
the leakage data presented in the remainder of this section.
C. NMOS Leakage Analysis and Characterization
Transistor drain leakage is typically modeled as the combination of two separate phenomena: diode leakage and subthreshold conduction. Drain-to-bulk diode leakage for nonzero
drain-to-bulk voltages was discussed earlier and was illustrated
in Fig. 1. In an NMOS, this current can be modeled to first order
by the ideal diode equation
(2)
is the diode current and
the applied voltage,
where
is the diode saturation current and is a constant proportional to
a linear combination of the junction area and perimeter, and
is the thermal voltage (roughly 26 mV at
K).
The second source of leakage is due to subthreshold conduction. The following equation describes the drain-to-source cur, of a subthreshold (
) NMOS transistor
rent,
(3)
where
is a process-dependent current-scaling constant,
is the transistor’s threshold voltage,
is its width over length
ratio, and is a parameter that is a function of the applied
source-to-bulk voltage and has a magnitude less than one [14].1
The threshold voltage
is defined by the body-effect relation
(4)
, which is
and is a function of the nominal threshold voltage
fixed for a given technology, the applied source-to-bulk voltage
, and and , which are process-dependent parameters.
Since the drain leakage is the sum of these two leakage mechanisms, subthreshold conduction can be made negligible by reuntil
. The
at which this happens
ducing
1The parameter is equivalent to the reciprocal of the parameter n given in
this reference.
Fig. 3. Five different minimum-sized NMOS I versus V curves with V =
= 150 mV. All I ’s are referenced with respect to the
direction shown in Fig. 2.
V = 0 V and V
has several interesting dependencies. First, it is a weak function
– if the diode leakage is reduced
must decrease to
of
ensure that subthreshold conduction remains small enough to
be ignored. Second, it depends linearly on the transistor’s nomis a function of the difference
inal threshold voltage since
and
. Therefore, as the threshold voltages of
between
modern processes decrease to enable low-voltage design, the
at which subthreshold conduction can be ignored is steadily
decreasing. The net result of this trend is that in most modern
processes the subthreshold current and diode leakage equalize
V. Due to this effect, most modern NMOS transisat a
V) but have nonzero
tors that are digitally OFF (
will conduct with a level of
several orders of magnitude larger than
.
The tradeoff between diode leakage and subthreshold conduction outlined above appears to be experimentally verified in
Fig. 3. The figure shows the measured
versus
characteristics of five different minimum-sized NMOS transistors with
V and
mV. The current
(always referenced with respect to the direction shown in Fig. 2)
varies exponentially with the gate-to-source voltage for
mV indicating subthreshold conduction dominates in this
mV
region, and remains roughly constant for
where diode leakage apparently dominates. Thus, one method
of minimizing NMOS subthreshold conduction in this process
mV. Note that in this particular example,
is to bias
the gate would have to be driven to a voltage outside the range
of the existing rail voltages to avoid subthreshold conduction.
An alternate method of avoiding subthreshold leakage was
employed in the transmission gate switch shown in Fig. 1(a),
and is also discussed in [13]. Since it is the difference between
and
that controls
, subthreshold current can be reduced by increasing
, or equivalently
. For large enough
, this technique allows subthreshold conduction to be made
V. Shifting
has the added
negligible for a level of
V without the need
benefit of allowing for levels of
O’HALLORAN AND SARPESHKAR: A 10-nW 12-bit ACCURATE ANALOG STORAGE CELL WITH 10-aA LEAKAGE
Fig. 4. Minimum-sized NMOS accumulation-mode I versus V curves for
50 mV V
150 mV, with V = 0 V and V = 150 mV.
0
to drive the NMOS gate below the lower rail. Both of these effects alleviate the rail problem, however the disadvantage of inin the case of a switch is that it also reverse-biases
creasing
.
the drain-to-bulk diode, increasing
The options presented above for avoiding subthreshold conduction in NMOS transistors in this process are unattractive.
However, if it were possible to fabricate the NMOS inside
a well, the switch topology presented in Fig. 1(b) could be
biased near
to simultaneously minimize
used with
subthreshold leakage, avoid the rail problem, and minimize
drain-to-bulk leakage. The obvious alternative in an n-well
process is to implement the switch using a PMOS transistor.
Before examining the leakage of a PMOS version of this
switch, we present observations of an accumulation-mode
leakage mechanism that can easily dominate diode leakage in
both PMOS and NMOS transistors.
D. Accumulation-Mode Source-Drain Coupling
Equation (3) is valid only when the NMOS structure is biased
in weak inversion, which was true in the above experimental
mV. However, for
mV
data for
the transistor is biased in a different region of MOS operation
known as accumulation-mode. In this regime, the subthreshold
mechanisms that couple the source and drain in the MOS
channel are negligible. As a result, it is typically concluded
the source no longer significantly interacts with the drain in
accumulation mode. The measurements presented in Fig. 4 not
only show that this assumption is false, but that the source-drain
interaction is still quite strong. In this experiment, the accumuversus
characteristic of a minimum-sized
lation-mode
with
NMOS transistor was measured at multiple values of
V and
mV. The plot shows that as
approaches
, the curves asymptote to a
-independent
aA – much lower than the apparent lower
drain current of
bound seen in Fig. 3.
reFig. 5 characterizes the accumulation-mode versus
sponse of the same minimum-sized NMOS transistor at a fixed
1989
Fig. 5. Minimum-sized NMOS accumulation-mode I versus V
300 mV, with V = 0 V and V = 1 V.
150 mV V
0
curves for
Fig. 6. Empirical model of accumulation-mode NMOS leakage sources.
V, for multiple values of
. The plots show that
mV
mV the drain current
still defor
pends exponentially on
, changing an order of magnitude for
, but is independent of the source-to-bulk
a 60 mV change in
mV. Also, the residual leakage values
voltage for
, most likely due to the drain-to-bulk
weakly increase with
diode’s reverse current increasing with reverse bias. Modeling
this response as an ideal diode plus a drain-dependent offset current gives data fits with correlation coefficients above 0.99, suggesting that a significant component of the accumulation-mode
leakage current is due to a coupling of the source-to-bulk diode
current to the drain terminal. Finally, since the source and drain
are symmetric terminals in the MOS transistor, the observed interaction will also be symmetric.
An empirical model of this accumulation-mode conduction
mechanism in the NMOS is shown in Fig. 6. The distributed
drain-to-bulk and source-to-bulk diodes are modeled as two
and
pairs of lumped diodes. The first diode in each pair,
, are lumped models of the portions of the distributed
diodes that only interact with the bulk. The second diode in
and
, represent the portions of these
each pair,
distributed diodes that only interact with the opposite MOS
terminal. It is postulated that the mechanism linking these two
1990
diodes is carrier diffusion under the accumulation layer. This
theory is bolstered by the fact that in Fig. 4 the drain current in
becomes more negative. The
the upper curves decreases as
empirical model explains this behavior as a reduction in the
and
due to the increasing
cross-sectional areas of
.
depth of the accumulation layer with decreasing
A second interpretation of this empirical model is to view the
and
as a single symmetric lateral
coupled diodes
bipolar transistor acting between the source, bulk, and drain terminals. A detailed device-physics-based characterization of this
leakage mechanism could be developed based on either of these
equivalent views. However, since the primary goal of this section is only to understand how to minimize MOS leakage, a
simple rule-of-thumb for avoiding this leakage mechanism is
offered and the effect is not characterized further.2
From the symmetry of the empirical leakage model, it is
expected that the accumulation-mode source/drain interaction
. Under these
can be minimized by ensuring that
and
will be
conditions, the currents flowing in
equal in magnitude and opposite in direction, summing to zero
like in traditional subthreshold conduction or symmetric lateral
bipolar conduction. This was previously observed in Fig. 4 for
mV, and resulted in a residual leakage
due to only
. Additionally, if either (or both)
or
mV, the model predicts the net leakage from that
node will depend on the node voltage only weakly through
the diode’s reverse-bias current dependence on reverse-bias
voltage, as seen in Fig. 5.
The implications of the accumulation-mode leakage effect on
is
the switch topology of Fig. 1(b) are clear. In this switch,
intentionally biased as close to 0 V as possible to minimize the
drain-to-bulk diode leakage. Thus, to ensure that the accumulation-mode conduction mechanism characterized above does not
dominate diode leakage when the switch is turned off, we reV.
quire that
E. PMOS Low-Leakage Switch
The final measurements in this section characterize the
leakage of a PMOS version of the switch topology shown
versus
curves of five
in Fig. 1(b). The measured
minimum-sized PMOS transistors are shown in Fig. 7 for
mV
mV, with
V, a bulk-to-substrate
V, and
V.
voltage of
These bias voltages eliminate subthreshold conduction,
minimize drain-to-bulk diode leakage, and minimize accumulation-mode conduction. The leakage is characterized as a
because this voltage will eventually depend on
function of
a random amplifier offset, much like it did in the leakage tester
of Fig. 2. Thus, the sweeps shown in Fig. 7 represent the range
of leakages that most likely will be encountered in a storage
cell using a minimum-sized PMOS transistor as a switch.
2Further characterization of the effect is also not trivial. The drain terminal
leakage is easy to measure using the current-integrator structure because the
transistor can also be used as a switch when resetting the integrator between
test runs. However, this ability to easily reset the integrator is lost if the source
terminal is simultaneously connected to a second integrator, or if the bulk terminal leakage is being characterized.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 11, NOVEMBER 2004
Fig. 7. Five minimum-sized PMOS I versus V
= 1:65 V, and V
= 3:3 V.
V
curves with V
= 0 V,
An interesting result seen in Fig. 7 is the nonzero current
V. This highlights an additional leakage
when
mechanism unique to transistors fabricated inside wells. In
these transistors, the well-to-substrate junction can interact
with the drain through minority carrier diffusion, just as the
source-to-bulk junction does in accumulation-mode. Equivalently, this leakage can be viewed as the result of a vertical
bipolar transistor acting between the drain, well, and substrate terminals. Since the well-to-substrate junction is heavily
reverse-biased and the drain-to-well junction is not, a net differential leakage current flows from the drain to the substrate,
accounting for the observed offset. This theory is supported
by measurements showing this offset leakage approaches zero
approaches 0 V. The first storage cell in the next
as
section accepts this offset as unavoidable, while the second cell
attempts to eliminate it.
III. ANALOG STORAGE CELL IMPLEMENTATION
A. Single-Sided Storage Cell Overview
A top-level view of the single-sided switched-capacitor
storage cell topology is shown in Fig. 8. This cell is based on
a standard high-accuracy sample-and-hold circuit presented in
[15]. The analysis of cell operation that follows ignores switch
charge injection and device noise, but these error sources will
be considered in a moment. Additionally, for the moment
and assume that
V.
ignore
The sampling phase of circuit operation occurs while the digital signals and
(a delayed version of that occurs later
is low. Under these conditions
in time) are both high and
switches
and
are closed and switch
is open. This ties
to the
the amplifier in unity-negative feedback and connects
. The net voltage apleft side of the sampling capacitor
during this phase is
,
plied across
where
is defined to be the offset between the negative and
positive terminals of the amplifier in this unity-negative feedback configuration. At the instant in time when switches from
O’HALLORAN AND SARPESHKAR: A 10-nW 12-bit ACCURATE ANALOG STORAGE CELL WITH 10-aA LEAKAGE
1991
Fig. 8. High-level view of switched-capacitor storage cell.
high to low, switch
opens and the sampling phase ends. Asinto the virtual ground
suming zero charge injection from
will be
node of the amplifier, the voltage held across
(5)
Notice that if there is a nonzero parasitic capacitance
at
and
althe node, the capacitor divider formed by
lows movements in
to alter
even after
opens.
is also forced to
However, because of the capacitive divider,
. When switch
eventually closes
move in proportion to
and the hold phase begins the resulting negative feedback loop
to return to a voltage nearly identical to its samwill force
pling phase value. This can happen only if the left terminal of
returns to the voltage that was present at
at the instant when
opened. This independence from movements at
once
is opened is important when switch topologies are
chosen.
opens and the input voltage has been samAfter switch
pled, the delayed control signals
and
cause to open
to close. This connects the left terminal of
to the
and
, configuring the circuit in the same
output of the amplifier,
topology as the current integrator of Fig. 2 and highlighting that
it is switch that must be low-leakage. For the moment, ignore
the transient behavior of the circuit after closes and focus on
the final dc voltages that will exist after the system settles in this
new configuration. Intuitively, negative feedback will force the
virtual ground node to a hold-phase voltage of
(6)
where
is due to the amplifier’s finite open-loop dc gain
The hold-phase output voltage is
.
(7)
Using (7),
can be expressed in terms of the change in
from the sample to the hold phase
(8)
which simplifies to give
(9)
Fig. 9. PMOS-input fully cascoded wide-output swing OTA. All devices are
sized 9 m/4.5 m.
causes
to differ from the deSince the error term
, the amplifier’s dc gain
must
sired held voltage
tolerable at the extremes of
.
be large enough to keep
To this end, the amplifier was implemented as a subthreshold
fully cascoded wide-output swing OTA, shown in Fig. 9, and
. All dedesigned with an open-loop dc gain
vices in the amplifier were sized with
m
m.
V and
V, (9) predicts that the
With
absolute value of the sampling error due to finite gain will be
for V
.
B. Charge Injection, Leakage, and Switch Implementations
When MOS switches are turned off they inject channel charge
and parasitic capacitive charge into the circuit nodes attached
to their drain and source. Since the stored information of the
above cell is represented by the sampled charge at the virtual
ground node of the amplifier, any charge injection into the viropens will alter the stored analog
tual ground node when
value. To minimize this charge injection, the standard dummy
transistor compensation technique is employed in constructing
[16].
The low-leakage, low-charge-injection switch structure used
for
is shown in Fig. 10(a). Note that a single-delay version
of the control signal is used in the switch control, for reasons that will be clear when the transient response is discussed.
connects to
while terminal
Referring to Fig. 8, terminal
connects to
. Transistor
forms the core of the switch
and is the PMOS equivalent of the low-leakage NMOS switch
implements charge-injection cancelof Fig. 1(b). Transistor
lation by nominally extracting the same charge from the virtual
injects into the node, and is delayed approground node as
,
priately. The bulks of both of these devices are biased at
as this is the best available estimate of the voltage that will be
during the hold phase of the cell. This minimizes
present at
the deterministic component of the source/drain-to-bulk diode
and
, but does not counteract the random
voltages of
or the input-dependent offset
amplifier input-offset voltage
. Choosing
significantly below
also ensures that
is biased deep in accumulation-mode when it is off, minidisconnects
mizing its subthreshold conduction. Transistor
from
during the hold phase so that
the source of
can connect this node to
, minimizing accumulation-mode
1992
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 11, NOVEMBER 2004
M
Fig. 10. (a) Low-leakage low-charge-injection switch for single-sided cell use. All transistors are minimum-sized (2.25 m/1.5-m) except
, which consists
of two minimum-sized transistors in parallel. (b) Low-leakage switch for differential cell use. Compared to the switch in (a),
has been removed and
now
consists of only a single minimum-sized transistor.
M
source-drain conduction in
. Transistor
’s bulk is biased
at
to ensure that this transistor’s drain-to-bulk diode cannot
during the hold phase.
be forward biased by a high level at
can be biased at either
or
, whichever
The bulk of
is more convenient during layout.
It should be emphasized that past switch designs have also bideep in accumulation-mode when it is off to minimize
ased
’s drain-tosubthreshold conduction, and have minimized
bulk diode voltage to minimize diode leakage. It is the novel adand
combined with the switching and biasing
dition of
scheme employed that minimizes accumulation-mode conducand allows this switch to achieve even lower leakage
tion in
compared to past designs.3
Since movements at
don’t affect the cell’s sampled inis opened, the charge-injection of switches
formation once
and
don’t affect the cell’s sampled value. However, the
leakage of these switches does introduce an additional amplifier voltage offset defined by the ratio of the leakage current to
the amplifier transconductance,
m . Fortunately, this offset
is less than 1 V for standard MOS switch leakages (
fA) and amplifier bias currents greater than 500 pA. Thus,
the only restriction placed on these two switches is that they
both must pass rail-to-rail voltage levels to maximize the inputoutput voltage range, and therefore they were implemented as
minimum-sized transmission gates.
C. Random Noise
An additional sampling error can be attributed to random circuit noise, which introduces an uncertainty in the voltage apduring the sampling phase. When transiplied across
will
tions from high-to-low, the voltage sampled across
be the sum of the value given in (5) plus the instantaneous value
of this noise voltage. In this circuit the noise was determined to
be dominated by the amplifier thermal noise. Since the amplifier
is effectively tied in unity negative feedback during all phases
of circuit operation, the total thermal noise is similar in form
3To be fair, an equivalent switch topology was mentioned in [3] during a discussion of the circuit implemented in [8]. However, the topology was not actually employed in [8], and was only mentioned in [3] as a simple method of
avoiding accidental forward-biasing of the switch’s lateral bipolar transistor.
The data presented in Section II clearly illustrates that even cutoff-region operation of the lateral-bipolar transistor can significantly affect switch leakage.
M
to that of a standard single-pole RC circuit, and is described by
[17]
m
(10)
m
is the effective number of devices conIn this equation,
in this amplifier),
tributing noise from the amplifier (
is the electron charge, m
is the subthreshold
transconductance of the amplifier, and
is the total effective
capacitance present at the output of the amplifier. The RMS
voltage noise of the circuit can be evaluated by taking the
square root of (10) and simplifying to get
(11)
where
represents the expected standard deviation
of
the noise voltage, and
. During the sampling phase
while during the hold phase
alone –
does not affect the hold-phase noise. Capacitor
serves the added role of increasing the loop’s
phase margin to 90 .
The capacitor values were chosen based on noise, chargeinjection, and frequency response constraints to be
pF and
pF. Assuming
, (11) preV,
dicts a sampling-phase standard deviation of
V. Since
and a hold-phase standard deviation of
thermal noise is Gaussian, the sampling error will lie within a
window over 99% of the time [18]. The random sampling voltage error window expected in this cell is
V. Coupled with the finite-gain and charge-injection errors, this still theoretically allows the cell to achieve 12-bit accurate sampling.
D. Transient Operation and Reset Phase
The transient response of the storage cell during its transition from the sampling phase to the hold phase requires special
consideration due to the topology chosen for switch . In the
, the voltage stored across
after
case where
opens will be negative. Ignoring
for the moment, the
voltage stored on
at the end of the sampling phase will
. The problem occurs when switch
connects the
equal
to the output of the amplifier, and thus
left terminal of
. Since
, the
to
O’HALLORAN AND SARPESHKAR: A 10-nW 12-bit ACCURATE ANALOG STORAGE CELL WITH 10-aA LEAKAGE
resulting capacitive divider causes
’s voltage to only deat the instant when
closes. As a
crease slightly below
transiently rises from
to
result, the left terminal of
, and the capacitive divider formed by
and
forces above
. The voltage at remains above
while
the amplifier’s output slews to the equilibrium dc output voltage
determined previously in (7) and (9). Referring to the diagram
in Fig. 10(a), it is clear that if
is pulled above
, the
of
and
will forward bias alsource/drain-to-bulk diodes of
lowing charge to flow out of , corrupting the stored analog
information.
to 0 V
One solution to this problem is to always reset
opens, but before
closes, which will ensure that
after
during the initial transient and amplifier
is always less than
slewing phases. This is accomplished using an NMOS transistor
, as shown in Fig. 8. The digital
connected in parallel with
high after has gone low but becontrol circuitry pulses
goes low, with the pulse lasting
. The charge
fore
during slewing
injected by ’s reverse-biased diodes into
still introduces an additional sampling offset error, but calculations show that it is negligible.
1993
Fig. 11. Modifications of original cell to implement differential leakage and
charge cancellation.
E. Differential-Leakage Cancellation
The leakage of the storage cell in Fig. 8 is expected to be significantly larger than the values measured in Fig. 7 as a result of
the dummy-device charge cancellation employed in . Referring again to Fig. 10(a), this technique required
to be con’s
structed from two parallel minimum-sized transistors and
source and drain to both be connected to the virtual ground node
of the amplifier. This makes the source/drain-to-bulk area connected to the virtual ground node a factor of four larger than that
of a minimum-sized device. Since diode saturation current is
proportional to junction area, both the offset and slope of the
leakage current of this switch will be approximately four times
larger than the values measured in Fig. 7, increasing to approximately 70 aA and 4 aA/mV, respectively. The actual increase in
these parameters is not so simple to predict because the mechanisms involved exhibit more intricate dependencies on junction
sizing and layout geometry, but it is certain that they will increase.
The estimated leakage floor of the single-sided cell can be
reduced by modifying the original cell of Fig. 8 to employ differential charge-injection and leakage-cancellation techniques.
The necessary modifications to the original cell are highlighted
directly to the posiin Fig. 11. First, rather than connecting
,
tive terminal of the amplifier, this voltage is sampled using
a minimum-sized PMOS, onto
which is identical to
. The left terminal of
could be tied to any dc
is preferred as it is a quiet reference voltage
voltage, but
and thus offers a high level of power supply rejection. Switch
, shown in Fig. 10(b), is a modified version of the origtopology with transistor
eliminated and transistor
inal
formed from a single minimum-sized PMOS rather than
two in parallel. The difference between the charge injections
and
onto
and
, respectively, define
of
the net charge injection, which should nominally be zero due
to matching. Additionally, the net hold-phase leakage will be
and
, two
set by the difference between the leakage of
Fig. 12.
Difference between input and stored voltage in single-sided cell.
minimum-sized PMOS transistors that are both biased in the
ultra-low-leakage configuration. Assuming 80% matching, the
offset component of the leakage observed in Fig. 7 should be
aA, while the random component due
reduced to less than
to the amplifier input-offset voltage should remain at
aA
-mV range.
for offsets in the
IV. MEASURED PERFORMANCE
A. Single-Sided Cell
The measured dc input-output response of a representative
V,
V,
single-sided storage cell with
and an amplifier bias current of 1.5-nA is shown in Fig. 12. The
plot shows the difference between the input and stored voltage
as a function of the input voltage, as well as a first-order fit
below 0.2 V and
to the relevant portion of the data. For
above 3.1 V the error rapidly increases, indicating these sampled
voltage levels are outside the saturation region of the amplifier’s
output leg. However, inside these limits the absolute value of
1994
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 11, NOVEMBER 2004
TABLE III
MEASURED PERFORMANCE OF FABRICATED SINGLE-SIDED STORAGE CELLS
Fig. 13.
Single-sided cell leakage.
the sampling error is less than 600 V, including
sampling
V—roughly
noise. The sampling error when
200 V based on the data fit—represents the constant offset
error due to charge injection, since at this input level the finite-gain induced error is zero. The fit also shows that at the
the sampling error lies within
V of the
extremes of
nominal offset of 200 V, indicating a maximum finite-gain induced error of
V. The measured dc sweep parameters of the four storage cells that were fabricated are listed
in Table III along with the statistical results. Since the absolute
V
V, the
sampling error of all cells is less than
cells achieve 12-bit accurate sampling.
The leakage responses of the four cells are shown in Fig. 13.
The leakage was verified to be virtually independent of the sampled voltage level, as expected, so the sampled voltage level
was arbitrarily chosen to be 1 V. The measured amplifier offsets
and inferred leakage currents of each cell are listed in Table III.
The measurements show that the average leakage of the cell is
roughly a factor of three larger than the value seen in Fig. 7,
and the change in leakage for a given change in offset voltage
is between four and five times larger than that seen in Fig. 7, in
agreement with the arguments presented in Section III-E.
Fig. 14.
Difference between input and stored voltage in differential cell.
B. Differential Cell
The measured dc input-output response of a representative
V,
V, and
differential storage cell with
an amplifier bias current of 1.5 nA is shown in Fig. 14, along
with a first-order fit. This differential cell exhibits an inputoutput range spanning 0.2 to 3.1 V, a charge-injection offset of
V.
75 V, and a maximum finite-gain error of
The measured dc sweep parameters of all four differential cells
are summarized in Table IV. Notice that the input-output range
and finite-gain error are similar for the differential and singlesided cells, as expected, but the charge injection offset is consistently smaller in the differential cells. Since the absolute samsampling
pling error is now less than 400 V, including
noise, and the input-output range remains greater than 2.9 V,
these cells achieve 12-bit accurate sampling.
The leakage responses of the four differential cells are shown
in Fig. 15, and a summary of the inferred leakage currents and
measured amplifier offsets of each cell are listed in Table IV.
Clearly the differential cell leakages still vary with amplifier
offset, but the standard deviation of this dependence has been
significantly reduced by the decreased junction area. The average leakage current of the differential cells is 9 aA per cell,
O’HALLORAN AND SARPESHKAR: A 10-nW 12-bit ACCURATE ANALOG STORAGE CELL WITH 10-aA LEAKAGE
1995
TABLE IV
MEASURED PERFORMANCE OF FABRICATED DIFFERENTIAL STORAGE CELLS
Fig. 15.
Differential cell leakage.
with only one cell exceeding this level of leakage due to its
large amplifier offset voltage. This was verified by externally remV, which reduced this cell’s
ducing the amplifier offset to
leakage to under 10 aA.
C. Discussion
To compare these results with past cells, the framework introduced in Section II is used. The nominal leakage of the singlesided cells should be less than the theoretical leakage given in
Table I multiplied by the appropriate scaling factor for drain-tofA
aA. The
bulk voltage minimization, or
measured leakage is less than 80 aA in the worst case, 45 aA
in the average case, and is clearly under the estimated bound.
These cells’ worst-case leakage is already comparable to the
leakage of the leading implementation in the literature [5].
The differential cells implement drain-to-bulk voltage minimization as well as differential leakage cancellation, and their
leakage should be bounded by
fA
aA.
The achieved leakage is less than 15 aA in the worst case, 9 aA
in the average case, again under the estimated upper bound. The
average leakage is more than 8 lower than the leading implementation in the literature [5].
A die photo of the differential cell is shown in Fig. 16. Additionally, other cell parameters of interest are included in Table V.
Fig. 16.
white.
Die photograph (2.2 mm
2 2.2 mm). The differential cell is circled in
TABLE V
ADDITIONAL CELL PARAMETERS
In particular, the differential cells on average lose one bit of
voltage accuracy, 700 V on a 12-bit scale and 11.3 mV on an
8-bit scale, in 3.3 and 54 min, respectively. The hold time of this
cell at these voltage accuracies is 15 longer than the cell in [5],
using only 92% as much area. Since junction leakage nominally
1996
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 11, NOVEMBER 2004
decreases with the square of the feature size [13], the design is
expected to achieve even lower leakage and smaller cell sizes
in more modern processes. This claim is supported by preliminary measurements taken from several minimum-sized 0.5- m
versions of the low-leakage switch, which exhibit over an order
of magnitude less leakage than the 1.5- m versions presented
here. These results agree with the expected leakage reduction
due to feature-size scaling.
Before concluding, a few final issues should be briefly addressed. The first is the storage cells’ slow 10-ms sampling
time. In order to demonstrate that the proposed leakage reduction technique can be used in low-power design, the cells were
biased at low current levels, making them slow. However, the
usual power versus speed tradeoff can be applied to these cells
without affecting their leakage performance. A second issue
worth addressing is the temperature dependence of cell leakage.
Measurements revealed that the residual leakage is thermally activated, increasing by roughly a factor of 3 per 10 C. Since
this behavior is similar to that of a standard diode, the data is not
shown for brevity. The final issue that should be mentioned is
that capacitor soakage—the voltage-dependent polarization of
a capacitor’s dielectric—fundamentally limits the performance
of any sample-and-hold circuit [19]. This effect is typically ignored in analog storage cells because, due to the applications in
which they are used, the stored voltages usually remain within a
small neighborhood of the full input-output voltage range of the
cell. However, for true rail-to-rail sample-and-hold operation,
capacitor soakage will limit the sampling accuracy and initial
leakage of the cell, and must be considered.
V. CONCLUSION
Using an on-chip current integration technique to characterize the dominant sources of MOS drain leakage, an accumulation-mode leakage mechanism that can dominate junction
diode leakage has been observed. A simple rule-of-thumb was
offered for avoiding this leakage mechanism, leading to a novel
ultra-low leakage switch topology. A differential storage cell
incorporating this new switch achieves an average leakage
of 10 aA at room temperature, an 8 reduction over past
designs. The cell loses one bit of voltage accuracy, 700 V on
a 12-bit scale and 11.3 mV on an 8-bit scale, in 3.3 and 54 min,
respectively. This represents a 15 increase in hold time at
these voltage accuracies over past designs. Since the leakage is
independent of amplifier speed, the cell can operate on as little
as 10 nW of power.
REFERENCES
[1] C. C. Enz and G. C. Temes, “Circuit techniques for reducing the effects
of op-amp imperfections: Autozeroing, correlated double sampling, and
chopper stabilization,” Proc. IEEE, vol. 84, pp. 1584–1614, Nov. 1996.
[2] Y. Horio and S. Nakamura, “Analog memories for VLSI neurocomputing,” in Artificial Neural Networks: Paradigms, Applications,
and Hardware Implementations, E. Sánchez-Sinencio and C. Lau,
Eds. New York: IEEE Press, 1992, pp. 344–363.
[3] E. Vittoz, H. Oguey, M. A. Maher, O. Nys, E. Dijkstra, and M.
Chevroulet, “Analog storage of adjustable synaptic weights,” in
VLSI Design of Neural Networks, U. Ramacher and U. Rückert,
Eds. Norwell, MA: Kluwer, 1991, pp. 47–63.
[4] K. Stafford, P. Gray, and R. Blanchard, “A complete monolithic
sample/hold amplifier,” IEEE J. Solid-State Circuits, vol. SC-9, pp.
381–387, Dec. 1974.
[5] M. Ehlert and H. Klar, “A 12-bit medium-time analog storage device
in a CMOS standard process,” IEEE J. Solid-State Circuits, vol. 33, pp.
1139–1143, July 1998.
[6] G. Cauwenberghs, “Analog VLSI long-term dynamic storage,” in Proc.
IEEE Int. Symp. Circuits and Systems, vol. 3, 1996, pp. 334–337.
[7] P. Heim and E. Vittoz, “Precise analog synapse for Kohonen feature
maps,” IEEE J. Solid State Circuits, vol. 29, pp. 982–985, Aug. 1994.
[8] M. Nahebi and B. Wooley, “A 10-bit video BiCMOS track-and-hold
amplifier,” IEEE J. Solid-State Circuits, vol. 24, pp. 1507–1516, Dec.
1989.
[9] B. Hochet, “Multivalued MOS memory for variable-synapse neural networks,” Electron. Lett., vol. 25, no. 10, pp. 669–670, May 1989.
[10] R. Nelson and C. Harbourt, “Long term storage circuit using a sampling technique,” IEEE J. Solid-State Circuits, vol. SC-2, pp. 49–53,
June 1967.
[11] A. Kramer, V. Hu, C. K. Sin, B. Gupta, R. Chu, and P. K. Ko, “EEPROM
device as a reconfigurable analog element for neural networks,” in Tech.
Dig. IEEE IEDM, 1989, pp. 259–262.
[12] C. Diorio, S. Mahajan, P. Hasler, B. Minch, and C. Mead, “A high-resolution nonvolatile analog memory cell,” in IEEE Int. Symp. Circuits and
Systems, vol. 3, May 1995, pp. 2233–2236.
[13] V. Linares-Barranco and T. Serrano-Gotarredona, “On the design and
characterization of femtoampere current-mode circuits,” IEEE J. SolidState Circuits, vol. 38, pp. 1353–1363, Aug. 2003.
[14] Y. P. Tsividis, Operation and Modeling of the MOS Transistor, 2nd
ed. New York: McGraw-Hill, 1999.
[15] D. A. Johns and K. Martin, Analog Integrated Circuit Design. New
York: Wiley, 1997, pp. 346–347.
[16] J. McCreary and P. R. Gray, “All-MOS charge redistribution analog-todigital conversion techniques–Part I,” IEEE J. Solid-State Circuits, vol.
SC-10, pp. 371–379, Dec. 1975.
[17] R. Sarpeshkar, R. F. Lyon, and C. A. Mead, “A low-power
wide-linear-range transconductance amplifier,” Analog Integrated
Circuits and Signal Processing, vol. 13, no. 1/2, May/June 1997.
[18] J. J. Sit and R. Sarpeshkar, “A micropower logarithmic A/D with offset
and temperature compensation,” IEEE J. Solid-State Circuits, vol. 39,
pp. 308–319, Feb. 2004.
[19] R. A. Pease, “Understand capacitor soakage to optimize analog systems,” in Proc. EDN, Oct. 13, 1990, pp. 125–129.
Micah O’Halloran received B.S. degrees in electrical and computer engineering from the University
of Florida, Gainesville, in 2000, and the M.S. degree
in electrical engineering from the Massachusetts
Institute of Technology (MIT), Cambridge, in 2002.
He is now a Ph.D. candidate working with the
Analog VLSI and Biological Systems Group at MIT.
His research interests include low-power analog
and mixed-signal design, adaptive systems, and
control theory.
Rahul Sarpeshkar (M’97) received Bachelor’s degrees in electrical engineering and physics from the
Massachusetts Institute of Technology (MIT). After
completing his Ph.D. at Caltech, he joined Bell Labs
as a member of the technical staff.
Since 1999, he has been on the faculty of MIT’s
Electrical Engineering and Computer Science Department where he heads a research group on Analog
VLSI and Biological Systems, and is currently the
Robert J. Shillman Associate Professor. He holds
over a dozen patents and has authored several publications, including one that was featured on the cover of Nature. His research
interests include analog and mixed-signal VLSI, ultra-low-power circuits and
systems, biologically inspired circuits and systems, and control theory.
Dr. Sarpeshkar has received several awards, including the Packard Fellow
Award given to outstanding young faculty, the ONR Young Investigator Award,
and the NSF Career Award. He was recently awarded the Junior Bose Award for
Excellence in Teaching at MIT.