Download A Bidirectional Wireless Link for Neural Prostheses that Minimizes Implanted Power Consumption

A Bidirectional Wireless Link for Neural Prostheses
that Minimizes Implanted Power Consumption
Soumyajit Mandal and Rahul Sarpeshkar
Department of Electrical Engineering and Computer Science
Massachusetts Institute of Technology, Cambridge MA 02139
Email: [email protected]
the external unit is less critical since its batteries may be
easily changed. We also need a relatively low-bandwidth
data link from the external unit to the implanted unit for
control, programming and feedback information. We term this
the downlink. Our system minimizes implanted power during
downlink as well.
Abstract— We describe a bidirectional impedance-modulation
wireless data link for implanted neural prostheses. The link
uses near-field inductive coupling between the implanted system
and an external transceiver. It is designed to minimize power
consumption in the implanted system and support high data
rates in the uplink direction (from the implanted to the external
system). Experimental results demonstrate data transfer rates up
to 5.8Mbps in the uplink direction and 300kbps in the downlink
direction at a link distance of 2cm. The link dissipates 100µW in
the implanted system and 2.5mW in the external system, making
it among the most power-efficient inductive data links reported.
II. S YSTEM D ESIGN
The link is designed to be half-duplex, i.e., either uplink
or downlink data (but not both) can be transmitted at any
given time. We use impedance modulation to transmit uplink
data. In impedance modulation one side (the primary) of a
coupled pair of resonators is driven with a sinusoidal source.
The impedance of the other, secondary resonator is switched
between two or more discrete states to transmit data. The
resultant amplitude and/or phase modulation of the primary
waveform is detected to receive the data. The coupling between the resonators can be near-field (inductive) or far-field
(radiative) in nature.
In our case, binary data is transmitted in an inductivelycoupled system by either opening or closing a switch connected in parallel with the secondary (internal) resonator.
This causes the impedance looking into the primary (external)
resonator to be modulated by a fraction m, where m is known
as the modulation depth. It can be shown that
I. I NTRODUCTION
Inductively-coupled near-field wireless links have been extensively used for various implanted medical devices [1]–[3].
Some far-field links have also been reported [4]. Many of these
links have been used to transmit power to the implanted device
in addition to carrying data signals. System design issues for
a proposed multiple-electrode neural prosthesis [5], however,
impart a somewhat different set of constraints on the wireless
transcutaneous link under consideration (see Fig. 1).
UPLINK
SKIN
SKULL
BRAIN
Fig. 1.
(multiplexed
neural data)
EXTERNAL UNIT
wireless link
DOWNLINK
(control signals)
INTERNAL UNIT
electrode array
m ≈ k 2 Q1 Q2
Simplified view of the neural prosthesis system described in [5].
where m is assumed to be 1, which is usually the case,
k is the mutual coupling coefficient between the coils and
Q1 and Q2 are their quality factors. The strong dependence
of m on k makes impedance modulation unsuitable for longrange links (where k is low). For short-range links, however, it
possesses the great advantage of dissipating almost no power
on the secondary side of the link. This allows the implanted
system to transfer data while keeping its power consumption
to a minimum; most of the power is dissipated in the external
system. A slightly different form of impedance modulation is
used to transmit downlink data (see Section III).
The implanted system (and other fully implanted systems
of the future) does not need continuous wireless power transfer since it can use a rechargeable battery. Only occasional
wireless battery recharges are needed. In this paper we shall
therefore focus only on data (not power) transfer through the
link. A discussion of RF power link design may be found in
[6]. The number of useful battery recharges is, however, limited (typically to about 103 ), which imposes severe constraints
on the power of the implanted system. In many applications,
such as prosthetics for paralysis [7], a high data rate link
(a few Mbps) is needed from the implanted system to an
external unit. We term this the uplink. Sending high-bandwidth
data on the uplink is expensive in power. In this paper, we
describe an impedance-modulation wireless link that solves
this problem by pushing as much of the power and complexity
to the external unit as possible. The power consumption of
1-4244-1525-X/07/$25.00 © 2007 IEEE
(1)
III. E XTERNAL T RANSCEIVER
Separate internal and external transceiver chips were designed and built. A simplified schematic of the external
transceiver is shown in Fig. 2. All analog circuits on the chip
are biased using an on-chip 2µA CMOS current reference.
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VDDL
The primary resonator forms part of an RF oscillator that
runs continuously when the external transceiver is receiving
data (T X is low). The internal transceiver turns the secondary
resonator on and off, causing modulation of the oscillator
envelope. The positive and negative sides of the envelope move
differentially and are individually tracked. The difference
between them is amplified and fed into a comparator. The
output of the comparator is passed into a hold timer. The
hold timer is essentially a low-pass filter that works on logiclevel signals. It eliminates pulses that are shorter than a certain
fixed duration, thus rejecting multiple transitions around data
edges because of noise. The overall effect is similar to using
a hysteretic comparator. Its output is fed into a phase-locked
loop (PLL) for clock and data recovery (CDR).
COUPLING TO
INTERNAL UNIT
L1
OFF-CHIP
ON-CHIP
C1
OUT
VDDH
R2
C2
VDDH
DATA
VDDL
Fig. 3.
The primary-side (external) RF oscillator.
VREF
−
IN
+
OSC
COUPLING TO
INTERNAL UNIT
TX
L1
VDDL
+
VDDH
VREF
−
HOLD
TIMER
OUT
+
OFF-CHIP
−
ON-CHIP
VREF
Fig. 2. Simplified schematic of the external transceiver. The output of the
hold timer is fed into a PLL (not shown in this figure).
Fig. 3 shows the RF oscillator. All components except L1
are on-chip. The oscillator uses a resonant tank (L1 and C1 )
as the main frequency-selective element. A CMOS inverter
in its high-gain region is used to provide enough loop gain
to induce oscillations. Operation in this region is ensured
by setting VDDL ≈ VDDH /2, where VDDH is the power
supply for the inverter and the rest of the chip. The voltages
VDDL and VDDH can be created by connecting two batteries
in series. The amplitude of the oscillation, Vosc (and power
consumption) increases with the aspect ratio of the NMOS in
parallel with L1 and C1 . Since m is fixed by link geometry,
the transistor is sized so that the detected signal amplitude
Vsignal = mVosc provides enough signal-to-noise ratio to
ensure an acceptably low bit error rate (BER). The high-pass
filter formed by R2 and C2 acts as a negative delay element
(predictor) that cancels out the inverter delay [8].
Increasing the oscillation frequency fosc increases the quality factors of the inductors, which increases m and allows
smaller Vosc and thus power consumption. However, at very
high frequencies losses in skin and other body tissues increase
and the coils eventually self-resonate. In our case a good
compromise between these competing factors was obtained
around 25MHz, which is where we operate.
The PLL, shown in Fig. 4, allows the uplink to use nonreturn-to-zero (NRZ) data, which maximizes data rate for
given link bandwidth. It uses a Hogge-type phase detector
(PD) [9], a cascoded charge pump and a passive, third-order
loop filter. The charge pump uses differential switching to
reduce charge injection errors. The output of the loop filter is
converted to a current by a wide-linear-range transconductor
(WLR) [10] that combines a well-input differential pair and
other linearization techniques to achieve over 1.5V of input
linear range. The output current of the WLR is fed into a
current-starved ring oscillator (CCO). The loop bandwidth is
set to 20KHz (about 1% of the nominal data rate, which is
2Mbps) to allow good CDR. The loop locks when the CCO
frequency is twice the data rate (a result of using the Hogge
PD, which also outputs re-timed data with edges synchronized
to the clock).
RESET
TIMER
FREQUENCY
LOCKED
LOOP
SEL
DATA
PHASE
DETECTOR
CHARGE
PUMP
LOOP
FILTER
−
Gm
+
IBIAS
CLK
SEL
CURRENT
CONTROLLED
OSCILLATOR
Fig. 4.
Block diagram of the phase-locked loop. The timer enables an
auxiliary frequency-locked loop after a system reset occurs.
True phase detectors, such as the Hogge, do not provide
much frequency error information. This property enables a
CDR PLL to remain locked when missing edges appear in the
input data stream, but reduces its capture range. As a result,
CDR PLL’s usually need additional circuitry to aid acquisition
of lock. We have designed a frequency-locked loop (FLL) for
this purpose. The FLL is shown in Fig. 5. A timer activates
it for a fixed number of clock cycles after a system reset (see
Fig. 4). During this period the main PLL is disabled and the
internal unit transmits a synchronization sequence consisting
of alternating ’0’ and ’1’ bits. The FLL is a first-order loop that
counts clock and data edges and sets the bias current of the
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CCO so that their rates are equal. It does this by using a digital
accumulator (which acts as the loop filter) and current DAC.
Each data edge (rising or falling) increments the accumulator,
while the divide-by-2 circuit ensures that only rising clock
edges decrement it. Therefore the FLL, like the PLL itself,
is locked when the clock runs at double the data rate. When
the timer disables the FLL the CCO is already running close
to the right frequency, so the PLL locks more easily. In our
implementation, the accumulator and DAC have five bits each,
which limits the initial frequency error that must be handled
by the PLL to less than 1/25 ≈ 3% of the data rate.
OFF-CHIP ON-CHIP
C2
COUPLING TO
EXTERNAL UNIT
Vdd
VDDH
ONE-SHOT
D
RST
ACC
DIVIDE
BY 2
Fig. 6.
HOLD
PWM
TIMER
DEMOD
OUT
R2
Simplified block diagram of the internal transceiver.
The output of the hold timer is fed into a pulse-width
demodulator circuit that regenerates the downlink data stream
from the PWM waveform. The demodulator circuit uses two
identical capacitors and charges them using matched current
sources when the PWM waveform is high and low, respectively. At the end of a bit period, the voltage across the
capacitors is compared to determine if the bit transmitted was
a ’0’ (high pulse = 25% of bit period) or a ’1’ (high pulse
= 75% of bit period). The capacitors are then reset and the
process starts again for the next bit.
DAC
LATCH
ONE-SHOT
CURRENT
CONTROLLED
OSCILLATOR
Fig. 5.
−
1x
RX IN
IREF
INCR
+
16x
C1 C2
VDDH
DATA
L1
R2
Block diagram of the frequency-locked loop.
V. E XPERIMENTAL R ESULTS
Fig. 7 shows the primary and secondary printed circuit
boards that were used to test the wireless link. Identical
transmit and receive coils were printed on the boards. Each coil
was square, 3.5cm on a side and had two turns. The designed
inductance was 500nH with a simulated quality factor of
30 at 25MHz. Packaged chips were surface mounted on the
boards and they were aligned parallel to each other at various
separations for testing. No external components were needed
apart from the coils, decoupling capacitors and power supplies.
During the transmit phase (T X is high) data is sent
to the implanted system via on-off keying (OOK). In this
phase the data signal turns the oscillator on and off (see
Fig. 3). Downlink data is encoded using 25 / 75% pulsewidth modulation (PWM) before transmission using a counterbased on-chip modulator. PWM, Manchester encoding and
other return-to-zero (RZ) encoding schemes are spectrally
inefficient. However, it makes sense to use an RZ scheme for
the downlink since the data rate is low in this direction. Every
bit period in RZ data contains at least one level transition that
can be used as a clock edge. Therefore a PLL is not needed
for CDR in the implanted system, minimizing its complexity
and power consumption.
IV. I NTERNAL T RANSCEIVER
A simplified block diagram of the internal transceiver is
shown in Fig. 6. All analog circuits on the chip are biased
using an on-chip 0.2µA CMOS current reference. During the
transmit phase (RX is low), the NRZ data stream to be
transmitted turns the switch in parallel with the secondary
resonator on and off. During the receive phase (RX is high)
the switch is turned off and an envelope detector is used to
track the voltage on the secondary resonator. This voltage
follows the PWM-encoded OOK bitstream transmitted from
the external transceiver. The output of the envelope detector
is compared with a reference voltage. The comparator output
goes high only if the envelope detector voltage exceeds the
reference by an amount greater than φt ln(16) = 72mV
at room temperature, where φt is the thermal voltage. A
hold timer, similar to the one in the external transceiver, is
used to remove spurious transitions in the comparator output
waveform due to noise.
Fig. 7. Primary and secondary test boards used for making experimental
measurements.
Fig. 8 shows transmitted and received data and recovered
clock waveforms measured for the uplink at 5.8Mbps. The
PLL synchronizes rising edges of the recovered clock to data
transitions. Falling edges of the clock therefore appear in the
middle of each bit and are used to sample the data stream. The
PLL was observed to lock over data rates varying between
1Mbps and 5.8Mbps.
Fig. 9 shows transmitted and received data waveforms
(before and after pulse-width demodulation) measured for the
downlink at 200kbps. Recovered data transitions are aligned
with rising edges of the pulse-width modulated signal. Falling
edges of this signal can therefore be used to sample the data
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−1
10
2
0
−2
−1
4
Clock
0
0.5
1
1.5
2
2.5
10
3
2
0
−1
4
−0.5
0
0.5
1
1.5
2
2.5
3
2
0
−1
4
−0.5
0
0.5
1
1.5
2
2.5
3
−0.5
0
0.5
1
Time (μs)
1.5
2
2.5
3
−4
10
−5
10
0
−6
10
Uplink data transmission at 5.8Mbps with the coils 2cm apart.
Fig. 10.
apart.
Tx Data (V)
PWM Data (V)
Output Data (V)
2
0
50
100
150
200
250
0
50
100
150
200
250
3
3.5
4
4.5
5
Data Rate (Mbps)
5.5
6
Measured bit error rate (BER) for the uplink with the coils 2cm
Parameter
Link distance
Center frequency
Uplink data rate
Uplink encoding
Downlink data rate
Downlink encoding
External power consumption
Internal power consumption
Fabrication process
Chip size
4
0
2.5
TABLE I
P ERFORMANCE S UMMARY
stream. The downlink was observed to operate over data rates
varying between 15kbps and 300kbps.
4
2
0
Value
tested up to 2cm
25MHz
1Mbps - 5.8Mbps
Non-return-to-zero (NRZ)
15kbps - 300kbps
Pulse-width modulation (PWM)
2.5mW (uplink) / 1.5mW (downlink)
100µW (uplink) / 140µW (downlink)
AMI 0.5µm CMOS
1.5mm×1.5mm (each transceiver)
4
R EFERENCES
2
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0
0
50
100
150
200
250
Time (μs)
Fig. 9.
−3
10
2
−1
Fig. 8.
−0.5
Bit Error Rate (BER)
Retimed Data
PLL Input
Tx Data
4
Downlink data transmission at 200kbps with the coils 2cm apart.
Fig. 10 shows experimentally measured bit error rates
(BER) for the wireless uplink when the coils were placed 2cm
apart. Error rates below 2.8Mbps were too low (less than 10−6 )
to be measured. The BER increases sharply for data rates that
exceed the available communication bandwidth because intersymbol interference (ISI) reduces the effective SNR. Available
bandwidth is limited both by the high-Q inductive link itself
and by the limited frequency response of on-chip circuits such
as the envelope detectors and front-end amplifier. We have also
measured BER for the downlink. Error rates in this direction
were found to be less than 10−5 over data rates between
15kbps and 300kbps.
Table I summarizes the measured performance of our bidirectional wireless link.
ACKNOWLEDGEMENT
The authors wish to thank Scott K. Arfin for help with figures and photography. We gratefully acknowledge the support
of the McGovern Institute Neurotechnology (MINT) program.
48