Download PS51277-A 数据资料DataSheet下载

MITSUBISHI
MITSUBISHI
SEMICONDUCTOR
SEMICONDUCTOR
<Intelligent
<Intelligent
Power
Power
Module>
Module>
PS51277-A
PS51277-A
TRANSFER-MOLD
TRANSFER-MOLD
TYPE
TYPE
INSULATED
INSULATED
TYPE
TYPE
PS51277-A
INTEGRATED POWER FUNCTIONS
• DC input, three-phase AC output inverter
• 600V, 15Arms (Input current)
INTEGRATED DRIVE, PROTECTION AND SYSTEM CONTROL FUNCTIONS
• IGBTS driver circuit
• Control supply under-voltage (UV) protection
• Input interface : 5~15V line CMOS/TTL compatible, Schmitt Trigger receiver circuit
APPLICATION
AC100~200V Active-Converter for PFC (Power Factor Correction), of Air-conditioner and so
on.
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Fig. 1 PACKAGE OUTLINES
Dimensions in mm
27×2.8(=75.6)
B
2.8±0.3
12 13
14 15 16 17 18 19 20 21
.2
22
23
24
25
26
8
20±0.3
67±0.3
1.8
0.8
0.6
79±0.5
1.4
N2
N2
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
14
15
16
17
18
19
20
21
22
23
24
25
26
GND
VD
VIN
GND
NC
NC
NC
NC
P
S
R
N
N
2
10±0.3 10±0.3 10±0.3
A
21 TERMINAL
8±0.5
2
±0
11.5±0.5
Type name , Lot No.
.5
-φ4
1
2
3
4
5
6
7
8
9
10
11
12
13
28±0.5
9 10 11
21.4±0.5
7 8
31±0.5
5 6
13.4±0.5
3 4
16±1
1 2
TERMINAL CODE
Detail A
9. 10. 11 TERMINAL
(71)
Heat sink
Detail B
Mar. 2003
MITSUBISHI SEMICONDUCTOR <Intelligent Power Module>
PS51277-A
TRANSFER-MOLD TYPE
INSULATED TYPE
MAXIMUM RATINGS (Tj = 25°C, unless otherwise noted)
MAIN CIRCUIT PART
Symbol
Vi
Supply Voltage
Parameter
Vi(surge)
Supply Voltage (surge)
VO
Output Voltage
Ratings
Conditions
Applied between : S-R
Applied between : S-R,
Surge value, Non-operating
264
Unit
Vrms
500
V
V
450
Applied between : P-N
Applied between : P-N,
VO(surge) Output Voltage (surge)
V
500
Surge value, Non-operating
Collector-Emitter Voltage
VCES
V
600
—
Repetitive Peak Reverse Voltage
VRRM
V
600
—
TC ≤ +90°C, Vi = 200V, VO = 300V,
Ii
Arms
Input Current (100% Load)
15
fPWM = 20kHz
TC ≤ +90°C, Vi = 200V, VO = 300V,
Input Current (125% Load)
Ii(125%)
Arms
18.7
fPWM = 20kHz, 1 min Non-repetitive
Value for 1msec of Surge Current
I2t
A 2s
I2t for Fu sing
75
Junction Temperature
(Note 1)
Tj
°C
–20~+125
Note 1 : The maximum junction temperature rating of the power chips integrated within the DIP-PFC is 150°C (@ TC ≤ 100°C) however, to ensure safe operation of the DIP-PFC, the average junction temperature should be limited to Tj(ave) ≤ 125°C (@ TC ≤ 100°C).
CONTROL (PROTECTION) PART
Symbol
VD
VIN
Condition
Applied between : VD-GND
Parameter
Control supply voltage
Control input voltage
Ratings
20
0~VD+0.5
Applied between : VIN-GND
Unit
V
V
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TOTAL SYSTEM
Symbol
TC
Tstg
Viso
Condition
Parameter
Module case operation temperature
Storage temperature
(Note 2)
60Hz, Sinusoidal, AC 1 minute, connection
pins to heat-sink plate
Isolation voltage
Ratings
–20~+100
–40~+125
Unit
°C
1500
Vrms
°C
Note 2 : TC MEASUREMENT POINT
Control Terminals
Heat sink
Tc
Tc
Heat sink boundary
Power Terminals
Mar. 2003
MITSUBISHI SEMICONDUCTOR <Intelligent Power Module>
PS51277-A
TRANSFER-MOLD TYPE
INSULATED TYPE
THERMAL RESISTANCE
Symbol
Rth(j-c)Q
Rth(j-c)F
Rth(c-f)
Parameter
Condition
Junction to case thermal
resistance
Inverter IGBT part
Inverter FWDi part
Contact thermal resistance
Case to fin, (per 1 module)
thermal grease applied
Limits
Unit
Min.
—
—
Typ.
—
—
Max.
2.05
°C/W
2.50
°C/W
—
—
0.067
°C/W
ELECTRICAL CHARACTERISTICS (Tj = 25°C, unless otherwise noted)
INVERTER PART
Symbol
Condition
Parameter
Limits
Min.
Typ.
Max.
Unit
VCE(sat)
Collector-emitter saturation
voltage
VD = 15V, VIN = 5V, IC = 30A
—
2.0
2.6
V
VF
ton
trr
tc(on)
toff
tc(off)
Forward voltage
IF = 30A
Switching times
VCC = 300V, VD = 15V
IC = 20A, Tj = 125°C, VIN = 5V ↔ 0V
—
—
—
—
—
—
—
—
—
—
1.6
0.23
0.14
0.14
0.43
0.23
—
—
—
—
2.2
—
—
—
—
—
1
10
1
10
V
µs
µs
µs
µs
µs
—
13
—
Inductive load
ICES
Collector-emitter cut-off
current
VCE = 600V
IR
Reverse current
VR = 600V
Tj = 25°C
Tj = 125°C
Tj = 25°C
Tj = 125°C
mA
mA
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Irr
FWDi reverse recovery
current
VCC = 300V, VD = 15V, IC = 20A, Tj = 25°C
A
CONTROL (PROTECTION) PART
Symbol
Parameter
VD
Control supply voltage
ID
Circuit current
IIN
Vth(on)
Vth(off)
Control input current
ON threshold voltage
OFF threshold voltage
Supply circuit under-voltage
protection
UVDt
UVDr
Condition
Applied between : VD-GND
Applied between : VD = 15V, VIN = 5V
VD-GND
VD = 15V, VIN = 0V
VD = 15V, VIN = 5V
Applied between : VIN-GND
Tj ≤ 125°C
Trip level
Reset level
Limits
Min.
13.5
—
—
—
—
1.3
10.3
10.8
Typ.
15.0
0.8
0.7
0.3
3.0
2.0
—
—
Max.
16.5
3.0
3.0
0.45
3.7
—
12.5
13.0
Unit
V
mA
mA
V
V
V
V
Mar. 2003
MITSUBISHI SEMICONDUCTOR <Intelligent Power Module>
PS51277-A
TRANSFER-MOLD TYPE
INSULATED TYPE
MECHANICAL CHARACTERISTICS AND RATINGS
Symbol
—
—
—
Limits
Condition
Parameter
Mounting torque
Weight
Heat-sink flatness
Mounting screw : M4
(Note 3)
Min.
0.98
—
–50
Typ.
1.18
54
—
Max.
1.47
—
100
Unit
N·m
g
µm
Note 3: Measurement point of heat-sink flatness
Measurement point
3mm
+ –
Place to contact
a heat sink
Heat sink
–
+
Heat sink
RECOMMENDED OPERATION CONDITIONS
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Symbol
Vi
VD
∆VD
fPWM
VIN(on)
VIN(off)
Parameter
Supply voltage
Control supply voltage
Control supply variation
PWM input frequency
Input ON threshold voltage
Input OFF threshold voltage
Condition
Applied between : S-R
Applied between : VD-GND
TC ≤ 100°C, Tj ≤ 125°C
Applied between : VIN-GND
Limits
Min.
Typ.
Max.
90
13.5
–1
—
—
15.0
—
20
4.0~VD
0~1.0
264
16.5
1
—
Unit
Vrms
V
V/µs
kHz
V
V
Mar. 2003
MITSUBISHI SEMICONDUCTOR <Intelligent Power Module>
PS51277-A
TRANSFER-MOLD TYPE
INSULATED TYPE
Fig. 2 THE DIP-PFC INTERNAL CIRCUIT
DIP-PFC
P
R
S
LVIC
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VD
VCC
ROUT
VIN
VIN
N2
SOUT
GND
GND
VNO
N
Mar. 2003
MITSUBISHI SEMICONDUCTOR <Intelligent Power Module>
PS51277-A
TRANSFER-MOLD TYPE
INSULATED TYPE
DIP-PFC Wiring Guidelines
Because DIP-PFC switches large current at a very high speed, considerable large surge voltage is generated easily between P and N terminals. Please pay attention to the following items:
• The area of P-Co-N shown in Fig. 3 should be as small as possible because the rectangle shaped switching current flows on this route. In
addition, please add a bypass condenser Co’ with good frequency response such as a polypropylene film condenser closely to the P and N
terminals.
• The two IGBT emitters are connected to the VNO terminal of LVIC inside the DIP-PFC. If the internal wiring inductance shown as L1 and L2
in Fig. 4 is too large, large surge voltage will be generated by di/dt. Especially, the lower the temperature, the faster the switching speed,
therefore the larger the di/dt. This surge voltage applies to the VNO and N terminals, which is possible to destruct LVIC.
• In order to suppress the surge voltage, the external wiring method shown in Fig. 4 is recommended. To reduce the parasitic wiring inductance, the wiring of the external terminals of N(N-1) and N(N-2) should be made as short as possible.
• Please mount a fast clamp diode (EG01Y@Sanken) between N and control GND terminals to prevent control GND potential variation from
the minus voltage of N terminal.
Fig. 3 DIP-PFC INTERFACE
DIP • PFC
P
R
N/F
+
S
Co'
Co
VD
LVIC
GND
N2
VNO
N
(N-1, N-2)
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VIN
Control IC
MCU
Fig. 4 RECOMMENDED WIRING METHOD
N2
N2
P
+
S
R
L2
N-1
To restrain the IPM surge voltage,
mount the condenser closely to the
terminals
L1
GND
VD
VIN
To reduce the parasitic inductance,
this wire should close to N terminal
N-2
+
VD
Control input
GND
Insert a diode here
Mar. 2003