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Shobhit Jaiswal / International Journal of Engineering Research and Applications
(IJERA)
ISSN: 2248-9622
www.ijera.com
Vol. 2, Issue 6, November- December 2012, pp.1136-1140
Low Power- HTSCR and CMOS Structure for On-chip ESD
Protection and Performance Comparison
Shobhit Jaiswal
(Senior Design Engineer)
Associated Electronics Research Foundation, NOIDA
Abstract
Low power ESD protection circuits are
implemented in 0.13µm technology [2,7]. This is
confirmed by transient ESD simulation under
varying condition of temperature and case
sensitivity; the results converge to a low power
on chip ESD protection based on the
comparison of performance.
M4
V1
5Vdc
MbreakpD
0
V
R4
Index terms: Electrostatic discharge (ESD),
M1
V1 = 2000V
V2 = 0V
Human Body Model (HBM), High triggered SCR
(HTSCR), Total power dissipation (TPD), Salicide
diffusion.
V2
M2
1k
MbreaknD
M3
MbreakND
MbreakND
V
TD = 10ns
TR = 50ns
TF = 150ns
PW = 1ns
PER = 500ns
1. Introduction
0
Fig.1 (b) Combination Resistor/ Transistor
rotection.
Different technology have been introduced
to implement ESD protection circuits on chip or
off chip with a progression of advancement in
performance over the previous ones [1,2,4]. These
are not area specific that’s why it is always
beneficial to protect IC or chip with such
technologies. Ironically, high performance
computing system characterized by large power
dissipation also drives the low power needs.
Another major demand for low power chips and
systems comes from environmental concerns. Here,
different types of ESD protection circuits are
shown with power down mode and their
performance comparison in case of HBM [3,6].
HBM: According to the industry standards, ESD
robustness requires the protection device to be able
to block a minimum HBM ESD event of 2KV with
a typical decay time of 150ns [2].
2. Types of ESD protection circuits:-
V1
5V
0
M1
M2
MbreakpD
M3
MbreakPD
MbreakpD
R1
V1 = 2000v
V2 = 0v
1k
V
V2
V
TD = 10ns
TR = 50ns
TF = 150ns
M4
M5
M6
PW = 1ns
MbreakND
PER = 500ns
MbreakND
MbreaknD
0
0
Fig.1
(c)
CMOS
circuit.
ESD
protection
V1
M3
V1
5V
M4
2
2
5Vdc
MbreakpD
MbreakPD
D1
D3
0
1
1N4376
1
0
1N4376
M7
M8
MbreakND
MbreakND
R2
1k
Q3
V
V
M10
V1 = 2000V
R3
M6
QbreakP
Q2
MbreakND
V
1k
QbreakN
2
V2
2
V2 = 0V
MbreaknD
R1
TD = 10ns
D4
D2
1N4376
M2
MbreaknD
M9
1N4376
1
M1
1
TR = 50ns
V
1k
MbreakND
V1 = 2000v
MbreakND
V2 = 0v
TF = 150ns
V2
TD = 10ns
PW = 1ns
0
TR = 50ns
TF = 150ns
PER = 500ns
PW = 1ns
0
PER = 500ns
0
0
0
Fig.1 (a) ESD diode protection circuit.
0
Fig.1
(d) ESD
HTSCR.
protection
circuit
using
1136 | P a g e
Shobhit Jaiswal / International Journal of Engineering Research and Applications
(IJERA)
ISSN: 2248-9622
www.ijera.com
Vol. 2, Issue 6, November- December 2012, pp.1136-1140
3. Input ESD pulse for above circuits in HBM
case: (Input ESD pulse Parametersare
according to the industrial specifications) [2].
6.0V
2.0KV
4.0V
1.5KV
2.0V
1.0KV
0.5KV
0V
0s
0.1us
V(M2:g)
0.2us
0.3us
V(M3:d)
0.4us
0.5us
0.6us
0.7us
0.8us
0.9us
1.0us
Time
0V
0s
0.1us
V(V1:-) V(V2:+)
0.2us
0.3us
0.4us
0.5us
0.6us
0.7us
0.8us
0.9us
1.0us
Fig. 3 (c) Simulation result for Fig. 1 (c)
Time
Fig.2. Input ESD waveform.
6.0V
4. Transient Analysis with Case Sensitivity/
Worst Case at Temperature (Sweep): 27⁰C,
45⁰C, 70⁰C, 100⁰C, 250⁰C.
4.0V
2.0KV
2.0V
1.5KV
0V
0s
1.0KV
0.1us
V(M1:s)
0.2us
0.3us
V(Q1A:B)
0.4us
0.5us
0.6us
0.7us
0.8us
0.9us
1.0us
Time
Fig. 3 (d) Simulation result for Fig. 1 (d)
0.5KV
0V
0s
0.1us
V(V2:+)
0.2us
0.3us
V(D1:A)
0.4us
0.5us
0.6us
0.7us
0.8us
0.9us
1.0us
Time
Fig. 3 (a) Simulation result for Fig. 1 (a).
2.0KV
1.0KV
0V
-1.0KV
0s
0.1us
V(M1:d)
0.2us
0.3us
V(M3:d)
0.4us
0.5us
0.6us
0.7us
0.8us
0.9us
1.0us
Time
Fig. 3 (b) Simulation result for Fig.1 (b).
1137 | P a g e
Shobhit Jaiswal / International Journal of Engineering Research and Applications
(IJERA)
ISSN: 2248-9622
www.ijera.com
Vol. 2, Issue 6, November- December 2012, pp.1136-1140
Circuit
Type
At
27⁰
Celsius
At 45⁰
Celsius
At 70⁰
Celsiu
s
At 100⁰
Celsius
At 250⁰
Celsius
TPD (W)
Impact due to increase
in temp.
Diode
4.9809V/2
KV
4.9790
V/2KV
4.9762
V
/2KV
4.9726V/
2KV
4.9326V/2
KV
1.20E-01
O/P Voltage Decrease
(1.223E9)/ 2KV
(1.36E09)/
2KV
(2.488
E-09)/
2KV
(31.70E09)/ 2KV
0.0026
/ 2KV
2.89E+03
O/P Voltage Decrease
CMOS
4-9809V
/2KV
49791V
/2KV
49763V
/ 2KV
4-9728V
/ 2KV
4-9485V
/ 2KV
2.08E+04
O/P Voltage Decrease
SCR
5.0V
/ 2KV
5.0V
/ 2KV
5.0V
/ 2KV
5.0V
/ 2KV
5.0V
/2KV
2.08E+04
O/P Voltage
Constant
Var.
resistor
&
Tr an- sistor
5. Table I. Comparison of ESD performance among HTSCR, CMOS, Var. resistor/ Transistor, Diode
protection circuits:
6. Graph I. on the basis of above table:
6
5
SCR
4
CMOS Transistor
3
Diode
2
Var. Resistor/
Transistor
1
0
27⁰ C
45⁰ C
70⁰ C 100⁰ C 250⁰ C
1138 | P a g e
Shobhit Jaiswal / International Journal of Engineering Research and Applications
(IJERA)
ISSN: 2248-9622
www.ijera.com
Vol. 2, Issue 6, November- December 2012, pp.1136-1140
and also the size of the ESD Clamp protection
7. Conclusion:
Graph I. shows that ESD protection circuit
using SCR gives better output stability over others
by increasing the sustainability of the Integrated
Circuits (ICs) on higher temperature.
From above it is clear that ESD protection
circuit using CMOS, clamps higher voltage than a
SCR but is not so fast to detect ESD transient
pulse, this is owing to lower ON resistance of SCR
and a more uniform distribution of electric field of
the device [7]. The SCR also works with salicided
diffusions [6]. In terms of stability, CMOS does not
bestow stable o/p as temperature increases
gradually.
circuit is same, then the parasitic capacitance of the
metal layer is 1fF/µm2 [5]. To, turn these circuits
with power down mode, supply Voltage. 1.2V is
the optimum voltage at which these circuits may
operate satisfactorily.
8.(c) CMOS ESD protection circuit at supply
voltage 1.2V
V1
1.2Vdc
0
1.200V
M1
8. Low Power ESD protection circuits
(CMOS and HTSCR):
M2
MbreakpD
M3
MbreakPD
MbreakpD
2.052V
8. (a) Power consumption for
circuit shown in Fig.1 (c):
R1
V1 = 2000v
2.000KV
1k
10W
V2 = 0v
V2
632.7mV
V
TD = 10ns
382.3mV
TR = 50ns
TF = 150ns
M4
M5
M6
0V
PW = 1ns
5W
MbreakND
PER = 500ns
0
MbreaknD
MbreakND
0V
0
0W
Fig.5 (a)
Power Consumption at 1.2V:
2.0KV
-5W
0s
0.1us
0.2us
0.3us
0.4us
0.5us
0.6us
0.7us
0.8us
0.9us
1.0us
W(V1)
Time
Fig.4 (a)
1.5KV
8.(b) Power consumption for circuit shown in
Fig.1 (d):
10W
1.0KV
5W
0.5KV
0W
0V
0s
0.1us
0.2us
0.3us
0.4us
0.5us
0.6us
0.7us
0.8us
0.9us
V(V2:+)
Time
-5W
0s
0.1us
0.2us
0.3us
0.4us
0.5us
0.6us
0.7us
0.8us
0.9us
1.0us
W(V1)
Time
Fig.4 (b)
From the equation of power dissipation:
P = CLV2f ………………. (I)
i.
The capacitance CL is constant.
ii. The voltage V is constant.
iii.
Clock frequency f.
Fig.5 (b)
8.(d) SCR ESD protection circuit at supply
voltage 1.2V
Assuming that in the above power equation the
operating frequency for both the circuits is same
1139 | P a g e
1.0us
Shobhit Jaiswal / International Journal of Engineering Research and Applications
(IJERA)
ISSN: 2248-9622
www.ijera.com
Vol. 2, Issue 6, November- December 2012, pp.1136-1140
Conclusion
V1
1.2V
0
M7
M8
MbreakND
5.000V
MbreakND
R2
1k
Q3
5.852V
M10
MbreaknD
5.000V
M6
QbreakP
3.992mV
MbreakND
R3
Q2
V
1k
20.01nV
QbreakN
R1
M9
1k
2.000KV
This paper has described the methodology
for low power CMOS and HTSCR ESD protection
circuit and their performance comparison. Spice
simulation was used to verify the results. From the
above we have deduced 75.95% reduction in power
consumption for the SCR circuit by reducing the
voltage from 5V to 1.2V. Similarly, if we compare
the above with CMOS, we have 60.16% reduction
in power consumption at the lower trigger edge of
the pulse. Low power ESD protection circuits
simulation with analysis has been demonstrated in
this work.
MbreakND
0V
V1 = 2000v
V2 = 0v
V2
TD = 10ns
0
TR = 50ns
TF = 150ns
PW = 1ns
0V
0
PER = 500ns
ig.5 (c)
Power consumption at 1.2V:
3.0W
2.0W
1.0W
0W
-1.0W
0s
0.1us
0.2us
0.3us
0.4us
0.5us
0.6us
0.7us
0.8us
0.9us
1.0us
W(V1)
Time
Fig.5 (d)
Reference:
[1]
G. Langguth, C. Russ, W. Soldner,
B.Stein, H. Gossner, “ESD Challenge in
Advanced CMOS Systems on Chip” 9781-4244-5775-0/2010IEEE.
[2]
Ming-Dou Ker, Wan-Yen Lin, ChengCheng Yen, Che-Ming Yang, Tung-yang
Chen, Shih-Fan Chen, “On-Chip ESD
Detection Circuits for System-Level ESD
Protection Design” 978-1-4244- 57984/10/2010IEEE.
[3]
Rafael Fried, Yaron Blecher and Shimon.
Friedman
“CMOS
ESD
Protection Structures... Characteristics
and Performance comparison”0-78032647- 4/951/1995 IEEE.
[4]
Stephen
G.
Beebe
“CHARACTERIZATION, MODELING,
AND DESIGN OF ESD PROTECTION
CIRCUITS.”
[5]
Yang Chen and Ming-Dou Ker “Design
on ESD Protection Circuit with Very Low
and Constant Input Capacitance” Tung- 07695-1025-6/ 2001 IEEE.
[6]
9. Table II. Power consumption
At 1.2V
Circuit
Type
At 5V
CMOS
9.969
W
mW
W
9.969
W
6.4970
mW
W
HTSCR
At
low
trigger edge
At
high
trigger edge
16.309
2.3973
[7]
H. Feng, R. Zhan, Q. Wu, G. Chen and
A.Z. Wang “RC-SCR: verv-low-voltage
ESD protection circuit in plain CMOS”
ELECTRONlCS LETTERS 12th September
2002 Vol. 38 No. 79.
F. Ma, Y. Han, S. Dong, B. Song, M.Miao
and K. Zhu “Investigation of boundaryMOS-triggered SCR structures for on-chip
ESD
protection”
ELECTRONICS
LETTERS 17th February 2011 Vol. 47 No.
4.
2.3973
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