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Transcript
Course Introduction Purpose This Part-B course discusses design techniques that are used to reduce noise problems in large-scale integration (LSI) devices. Objectives Learn approaches and design methods for minimizing electromagnetic interference emitted by LSI devices. Gain insight into how Renesas applies these techniques for handling noise problems in its microcomputer products. Content Learning Time 26 pages 30 minutes 1 © 2008, Renesas Technology America, Inc., All Rights Reserved Reducing EMI EMI reduction is a goal shared by the semiconductor experts who design LSI devices and by the system engineers who apply those devices. Process encompasses techniques for reducing the electromagnetic interference emitted by a specific system, circuit or device that causes other devices/circuits to operate incorrectly. 2 © 2008, Renesas Technology America, Inc., All Rights Reserved Explanation of Terms Core A microcontroller chip is composed of a core, I/O ports, and power supply circuitry. The core consists of the CPU, ROM, RAM, and blocks implementing timers, communication, and analog functions. CPG Clock Pulse Generator Driver buffer Output circuit transistors as well as output circuits for driving signals with large load capacitance and I/O port output transistors. Clock/bus driver, signals between blocks, etc. EMC Electromagnetic Compatibility EMI Electromagnetic Interference EMS Electromagnetic Susceptibility Harness Cables (wires) connecting a board and power supply or connecting one unit in a system to another. I/O Input/Output Port OSC Oscillator PLL Phase Locked Loop POR/LVD Power-On Reset/Low-Voltage Detect functions Power supply Two power supplies are applied to the LSI: Vcc and Vss. The core power supply internal to the LSI is VCL (internal step-down). The Vss-based power supply routed through the LSI is VSL. SSCG Spread-Spectrum Clock Generator WDT Watchdog Timer 3 © 2008, Renesas Technology America, Inc., All Rights Reserved Oscillator Circuit Design For minimum EMI, oscillator’s output should be a sine wave "H" Vcc Rf External components Vss Desired output waveform Excessive gain in the oscillator circuit’s inverting amplifier can causeVcc clipping. Vss The EMI that results contaminates power supply lines and other circuits Clipped waveform produces EMI 4 © 2008, Renesas Technology America, Inc., All Rights Reserved Adjusting Gain of Oscillator EMI can be reduced by adjusting the drive-capacity (gain) of the oscillator’s amplifier circuit Manual adjustment is via an external resistor, RD Ø Rf LSI device Xin Automatic or software-controlled capacity-switching uses logiccontrolled circuits to implement high and low drive Xout RD VSS "H” Low drive capacity High gain “L” High drive capacity Low gain 5 © 2008, Renesas Technology America, Inc., All Rights Reserved Phase-locked Loop Circuit PLL allows frequency of oscillator circuit to be lowered (decreased by a factor of 1/N), thereby reducing higher frequency harmonics and EMI Circuit can be built with jitter function to disperse high-frequency noise, thereby decreasing overall noise level PLL Circuit fs fo fo = N x fs 6 © 2008, Renesas Technology America, Inc., All Rights Reserved On-chip Oscillator Circuit OCO = Built-in alternative, high-performance oscillator circuit Provides backup for primary crystalcontrolled oscillator circuit Protects application against failure due to loss of system clock Allows system operation to continue or lets application shut down safely Pads I/O System clock Oscillation stop detect (OSD) feature provides automatic switching for fail-safe operation Primary oscillator (+ PLL) CPG OCO On-chip oscillator circuit I/O 7 © 2008, Renesas Technology America, Inc., All Rights Reserved Supplied to cores and functions I/O Spread-spectrum Clock Generator SSCG is an ideal solution for high-speed products Is combined with the PLL circuit in LSI devices Produces modulated waveform with wider spectrum Reduces noise emissions Is a very useful noise reduction technique for devices that can withstand variations in clock frequency Example of SSCG modulation waveform Noise emissions data 33kHz f Gain (dB) Without SSCG -7 to -10 dB With SSCG -0.5% f0 = 1.0GHz -0.5% Time 8 © 2008, Renesas Technology America, Inc., All Rights Reserved f0 Freq Clock and Bus Driver Capacity Capacity should be matched to the operating frequency and signal load of the lines being driven I/O Excess capacity wastes power and generates unnecessarily high levels of EMI Inadequate capacity causes performance degradation Design challenge is to optimize clock and bus lines and their drive circuits System clock Oscillator (+ PLL) CPG I/O 9 © 2008, Renesas Technology America, Inc., All Rights Reserved To cores and functions I/O Clock and Bus Signal Lines Signal lines with high frequencies and high drive levels should be kept as short as possible ROM RAM CPG COMMUNICATION CPU TIMERS Clock line Bus line 10 © 2008, Renesas Technology America, Inc., All Rights Reserved Transistors in Logic Circuits Transistors should be carefully selected so that size (current capacity) is as small as it can be, considering the design function, to minimize chip area, power, and EMI Can be selected from a large library of different sizes Typical On-chip Module Some transistors are drawn physically large here to indicate a large current capacity. In reality, this may not be the case 11 © 2008, Renesas Technology America, Inc., All Rights Reserved I/O-port Transistors Transistors should match characteristic impedance of circuit-board wiring ~100Ω to ~ 150Ω (~100 to 150 when parts are mounted) Mismatches cause ringing at port, producing EMI Impedance Mismatch Impedance Match Vcc Vcc ~100Ω ~ ~50Ω ~ ~100Ω ~ ~100Ω ~ GND GND Vcc If required, an external series resistor, (R = 50Ω to 1kΩ) can be used to stabilize the output ~50Ω ~ R1 GND 12 © 2008, Renesas Technology America, Inc., All Rights Reserved ~100Ω ~ I/O-port Rush Current Reduction Rush current can be reduced in various ways 1. Staggering timing of I/O port lines P00 V 2. Using slew-rate control to limit shoot-through current Delay ckt Delay ckt t P01 V Delay ckt Delay ckt t • • • • • • P07 V Port triggered • • • V • • • V Delay ckt Delay ckt t 13 © 2008, Renesas Technology America, Inc., All Rights Reserved NMOS turns on after PMOS turns off t I/O-port Rush Current Reduction Rush current can be reduced in various ways 3. Connecting multiple transistors in parallel to I/O terminal output buffers and turning them on in stages 1 1 + 2 4. Using feedback capacitors in the I/O buffers to broaden the output waveform 1 + 2 + 3 Vdd t1 t2 t3 Vdd Feedback capacitors Vss Vss 1 2 3 14 © 2008, Renesas Technology America, Inc., All Rights Reserved Rush Current Reduction in Core Rush current in core can be reduced by using capacitors to store a signal’s excess charge over a period of time Examples: Clock driver circuit, bus driver circuit Clock driver circuit Bus driver circuit Vdd Vdd C1 CLK Put capacitors near bus-driver transistors C2 Pooled charge BUS Pooled charge Vss Vss 15 © 2008, Renesas Technology America, Inc., All Rights Reserved Rush Current Reduction in Core Rush current can be decreased in core by implementing in the step-up circuit a circuit that limits the current that charges the large storage capacitor Example: Flash ROM Current-limit circuit Vpp Stepup circuit Flash ROM memory array C Vcc Vss 16 © 2008, Renesas Technology America, Inc., All Rights Reserved Rush Current Reduction in Core Another way to reduce rush current in the core is sequence the activation of the various power supplies that drive the core circuits • • • • • I/O • 5V • • • • • • • • • Step-down circuit Peripheral modules Vcl Vcc RAM C1 CPU Vsl or Vss Vss ROM • • • • • • A/D, D/A • • • 17 © 2008, Renesas Technology America, Inc., All Rights Reserved Vdd Module-stop Function The Module-stop function disconnects the supply voltage to a module not being used This saves power and eliminates the noise the module produces I/O CPU ROM System controller BUS Indicates module-stop signal CLOCK RAM TIMER-1 SCI TIMER-2 IIC TIMER-3 CAN 18 © 2008, Renesas Technology America, Inc., All Rights Reserved Clock-signal Control EMI is reduced when the clock distributed within the module is turned off when it isn’t needed I/O CPU ROM Module-stop signal Clock signal inside module BUS CLOCK RAM TIMER-1 SCI TIMER-2 IIC TIMER-3 CAN Clock to module Indicates main clock signal 19 © 2008, Renesas Technology America, Inc., All Rights Reserved -pin Output Control The clock is turned off in Single-chip mode and also when it isn’t required for clock synchronization in Extended mode Can be implemented using a switch at the output driver Performs best when the clock control is configured at the source I/O Clock line for System clock line Oscillator circuit CPG 20 © 2008, Renesas Technology America, Inc., All Rights Reserved Traditional Method The clock is turned off in Single-chip mode and also when it isn’t required for clock synchronization in Extended mode Can be implemented using a switch at the output driver Performs best when the clock control is configured at the source I/O Traditional design (not recommended) Clock line for remains active System clock line Oscillator circuit CPG 21 © 2008, Renesas Technology America, Inc., All Rights Reserved Innovative Method The clock is turned off in Single-chip mode and also when it isn’t required for clock synchronization in Extended mode Can be implemented I/O using a switch at the output driver Performs best when the clock control is configured at the source Clock line to driver is disconnected Oscillator circuit Improved design CPG 22 © 2008, Renesas Technology America, Inc., All Rights Reserved System clock line Independent High-speed Clock The built-in high-speed clock is generated by an on-chip oscillator and supplied only to peripherals that require it Can be used as a backup for the main system clock CPU Switch Divide by 2 20MHz I/O Osc. ckt. ROM BUS SYSTEM CLOCK RAM TIMER-1 SCI TIMER-2 IIC High-speed on-chip (40MHz) oscillator CAN 40MHz 20MHz 23 © 2008, Renesas Technology America, Inc., All Rights Reserved 40MHz Low-speed Clock Some Renesas LSI devices have a low-speed clock that is software switched and supplied to the peripheral modules that can operate at lower frequencies I/O CPU ROM BUS SYSTEM CLOCK RAM PSC SCI TIMER-1 TIMER-2 10MHz 20MHz Osc. Ckt. IIC CAN TIMER-3 10MHz 20MHz 24 © 2008, Renesas Technology America, Inc., All Rights Reserved 10MHz Estimating EMI Noise Levels Can be performed by making simplifying assumptions about the chip, then performing SPICE simulation CPG Internal capacitance of chip Package equivalent circuit Internal stepdown circuit EMI noise evaluation circuit equivalent circuit Simulation circuit diagram (conceptualization) Oscillator buffer R+L 25 © 2008, Renesas Technology America, Inc., All Rights Reserved Vcc Vss Course Summary Techniques for reducing EMI in oscillator circuits Ways to optimize the capacity of clock and bus drivers and clock and bus lines Methods for reducing rush current Ways to slow down a device’s overall operating rate Technology for estimating noise levels For more information on specific devices and related support products and material, please visit our Web site: http://america.renesas.com 26 © 2008, Renesas Technology America, Inc., All Rights Reserved