Download Vernier Delay Line

Literature Review –
Delay Measurement Techniques
Yuta Toriyama
[email protected]
August 20, 2010
Outline
 Introduction
 Problem statement
 Significance of stated problem
 Techniques
 Analog
 Digital Counter
 Ring Oscillator
 Vernier Delay Line
 Summary
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Problem Statement
 Design a circuit that can

measure the time difference
between the rising edge of
one signal to the rising edge
of another
Factors:
 Resolution
 Complexity of circuitry
 Test time
 etc…
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Significance of Delay Measurement ICs
 In General:
 Characterization


 Increased sensitivity/variation in deep sub-micron technologies
 Higher clock rates, more signal paths critically timed
Yield
Increasing difficulty of signal access for external test
 My case: Characterization of STTRAM
 Read delay measurement
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Charging A Capacitor
 Create an analog voltage across the capacitor depending
on how long the EN pulse is high
 Requires ADC; all elements of circuit need to be ideal; etc.
5
Digital Counter
 Count the number of rising edges of a fast clock
 Simple to implement
 Resolution limited by clock frequency
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Digital Counter
 Count the number of rising edges of a fast clock
 Simple to implement
 Resolution limited by clock frequency
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Ring Oscillator
 Count the number of rising edges w/ CUT included
 High Resolution (limited by mux delay)
 Signal delay being measured must occur multiple times
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Vernier Delay Line
 Two delay lines with slightly different delays in each buffer
 Detect where in the delay line the edges occur at the same
time
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Vernier Delay Line (cont.)
 Very fine resolution
 Sensitive to supply, layout
 Variation can cause non-linearity / non-monotonicity!
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Summary
 Tradeoff
 Resolution/Accuracy
 Complexity
 Test time
 STTRAM chip
 Digital Counter implemented for read delay measurement
 In simulation: ~100ps resolution (Richard)
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References
 Farahat, M.A.; Farag, F.A.; Elsimary, H.A.; , "Only digital technology
analog-to-digital converter circuit," Micro-NanoMechatronics and Human
Science, 2003 IEEE International Symposium on , vol.1, no., pp. 178- 181
Vol. 1, 27-30 Dec. 2003.
 Jochen Rivoir; , "Fully-Digital Time-To-Digital Converter for ATE with
Autonomous Calibration," Test Conference, 2006. ITC '06. IEEE
International , vol., no., pp.1-10, Oct. 2006.
 Sunter, S., “BIST Techniques for Delay and Jitter inNanometer Technology
ICs,” Southwest DFT Conference, May 2007.
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