Download Homework #4 -- Complex Flip-Flops and Sequential Logic

EE 2310 Homework #4 – Complex Flip Flops and Sequential Logic
Name ___________________________________ CE _________ EE _________
Note: All CLO’s in this problem set tie to ABET program-level criterion a.
1. (CLO 4—Seq. Logic) The FF shown is a master-slave T FF. The clock is shown in the
timing diagram, and the T input is activated as shown. Assume that the FF is initially
in the Reset state. Then plot Q and Q-Not for the number of clock pulses shown.
“Q”
“Q-Not”
“T”
Clock
2. (CLO 4—Seq. Logic) Using two of the T FF’s shown below, draw a modulo-4
standard binary counter. Then add a decoder that decodes count “3” and outputs it
as “Clock 2,” a digital signal with ¼ the frequency and a duty cycle of 25/75. Show
the timing below. Assume the two FF’s are reset at time 0, and then the clock and
counter both run continuously. Note: The T FF is master-slave.
T
Q
CR
“Clock 2”
Bit x
Bit y
Clock In
1
2
3
4
5
6
3. (CLO 4—Seq. Logic) A three-bit synchronous (parallel) counter is to be constructed,
and three events decoded from its output. The binary numbers 2, 3, and 5 are to be
decoded, ANDed with the inverted clock pulse, and transmitted to another circuit.
Signals “2,” “3,” and “5” last ½ clock cycle, after the counter outputs are true (thus
they are true only when clock is low). The counter is free-running, and is only cleared
at start-up by a common reset pulse tied to all the ff reset inputs. In summary:
T Q
• Counter inputs are clock and reset
CR
• Counter outputs are signals “2,” “3,” and “5”
• Input signals come from the left, output signals exit to the right
• Use the T ff shown to the right, and show the timing diagram on the form below.
(Note: Supports CLO 4—Seq. Logic, and also CLO 3—Comb. Logic)
“Five”
“Three”
“Two”
Bit 3 (MSB)
Bit 2
Bit 1 (LSB)
Clock
1
2
3
4
5
6
7
Timing of Decoded Pulses
2
EE 2310, Homework #4
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4. (CLO 4—Seq. Logic) Construct a modulo-7 parallel (synchronous) down-counter from
the three T master-slave FF’s shown. That is, the counter counts backwards. Assume
the counter starts at 0, then goes 0-6-5-4-3-2-1-0 and then back to 6, counting
continuously. The counter stages are x, y, and z (x = most significant digit). The Tinputs of the stages are then Tx, Ty, and Tz. Remember that for each ff to toggle when
the clock cycles, the T input must be “1.” Construct a timing diagram for the three
outputs of the counter on the chart below. Use the Karnaugh map method, NOT the
“short-cut” method to design the counter. Since the flip-flops are master-slave, all
outputs change on the down-going or “backside” edge of the clock. In the truth table
below, x=Qx. Y=Qy, and z=Qz. Note that count “7” is a “don’t care.”
(Note: Supports CLO 4—Seq. Logic, and also CLO 3—Comb. Logic)
yz
00
01
11
10
x 0
00
01
yz
yz
11
10
x 0
1
1
Tz
y
z
0
1
1
1
0
0
0
0
0
1
0
0
1
1
0
0
0
0
1
0
1
0
1
0
01
x 0
1
x
00
Ty
Tx
Tx Ty Tz
Truth Table for Determining T’s
x (MSB)
y
z (LSB)
Clock
1
2
3
4
5
6
7
Timing of Modulo-7 Counter
3
EE 2310, Homework #4
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10
5. (CLO 4—Seq. Logic) A “ring counter” is a group of master-slave D flip-flops
connected in sequence output-to-input, to make a circular shift register. One or
more of the D FF’s is set to one and the rest are set to 0. Since the flip-flops are
connected in a “ring,” the pattern of bits continually rotates around the shift
register. If one stage of the shift register is arbitrarily selected as the “output,” this
stage will output 0’s and 1’s in the sequence that the 1 and 0 values pass that
particular output.
If only one 1 is set into the register, then a 1 passes the chosen output only 1 clock
pulse in every N pulses, N being the number of D FF’s in the ring. The ring counter
in this case creates a new clock, with a frequency of 1/N compared to the regular
clock. More complex ring counters can be constructed, however, such as the one
below. In the case shown, two D FF’s are set to 1 (#’s 2 and 5), and the rest to 0 by
the “Reset”” pulse. However, the outputs of FF’s 2 and 4 are OR’ed together to
produce a very complex output sequence. After the Reset pulse shown on the timing
diagram, the clock starts and runs continually. Show the output “f” for the number
of clock cycles indicated below.
Output “f”
“Reset”
Clock
1
2
3
4
5
6
7
4
8
9
10
11
12
13
14
EE 2310, Homework #4
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