Download Logic Gates 1

Gate Behavior
Gate Characteristics
 Logic gate delay.
 Logic gate power consumption.
 Driving large loads.

FPGA-Based System Design: Chapter 2
Copyright  2004 Prentice Hall PTR
Gate Logic levels

Solid logic 0/1
– defined by VSS/VDD.

Inner bounds of logic
– values VL/VH are not directly determined by circuit properties, as
in some other logic families.
VDD
logic 1
unknown
VSS
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VH
VL
logic 0
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Logic level matching

Logic level matching
– Levels at output of one gate must be sufficient
to drive next gate.
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Transfer characteristics

Transfer curve
– shows static input/output relationship—hold
input voltage, measure output voltage.
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Inverter transfer curve
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Logic thresholds

Choose threshold voltages
– at points where slope of transfer curve = -1.

Inverter has a high gain
– between VIL and VIH points
– low gain at outer regions of transfer curve.

Note that logic 0 and 1 regions
– are not equal sized—in this case
– high pullup resistance leads to smaller logic 1 range.
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Noise margin

Noise margin
– voltage difference between output of one gate
and input of next.
– Noise must exceed noise margin to make
second gate produce wrong output.

In static gates
– t= voltages are VDD and VSS
– so noise margins are VDD-VIH and VIL-VSS.
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Delay

Assume ideal input (step), RC load.
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Delay assumptions

Assume that only one transistor is on at a
time. This gives two cases:
– rise time, pullup on;
– fall time, pullup off.

Assume resistor model for transistor.
– Ignores saturation region and mischaracterizes
linear region, but results are acceptable.
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Current through transistor

Transistor starts in saturation region
– then moves to linear region.
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Resistive model for transistor

Average V/I at two voltages:
– maximum output voltage
– middle of linear region
Voltage is Vds, current is given Id at that
drain voltage.
 Step input means that Vgs = VDD always.

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Resistive approximation
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Ways of measuring gate delay

Delay
– time required for gate’s output to reach 50% of
final value.

Transition time
– time required for gate’s output to reach 10%
(logic 0) or 90% (logic 1) of final value.
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Inverter delay circuit

Load is resistor + capacitor, driver is
resistor.
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Inverter delay with t model

t model
– gate delay based on RC time constant t.
– Vout(t) = VDD exp{-t/(Rn+RL)/ CL}
– tf = 2.2 R CL

For pullup time
– use pullup resistance.
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t model inverter delay

90 nm process:
– Rn = 11.1 kW
– Cl = 0.12 fF

So
– tf = 2.2 x 11.1E3 x 0.12E-15 = 2.9 ps.
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Quality of RC approximation
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Quality of step input
approximation
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Results of using small pullup
FPGA-Based System Design: Chapter 2
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Other models

Current source model (used in power/delay
studies):
– tf = CL (VDD-VSS)/Id
– = CL (VDD-VSS)/0.5 k’ (W/L) (VDD-VSS -Vt)2

Fitted model: fit curve to measured circuit
characteristics.
FPGA-Based System Design: Chapter 2
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Body effect and gates
Difference between source and substrate
voltages causes body effect.
 Source for gates in middle of network may
not equal substrate:

0
Source above VSS
0
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Body effect and gate input
ordering

To minimize body effect, put early arriving
signals at transistors closest to power
supply:
Early arriving signal
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Power consumption analysis
Dynamic power consumption comes from
switching behavior.
 Static power dissipation comes from
leakage currents.
 Surprising result: dynamic power
consumption is independent of the sizes of
the pullups and pulldowns.

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Power consumption circuit

Input is square wave.
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Power consumption
A single cycle requires one charge and one
discharge of capacitor: E = CL(VDD - VSS)2 .
 Clock frequency f = 1/t.
 Energy E = CL(VDD - VSS)2.
 Power = E x f = f CL(VDD - VSS)2.

FPGA-Based System Design: Chapter 2
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Observations on power
consumption
Resistance of pullup/pulldown drops out of
energy calculation.
 Power consumption depends on operating
frequency.

– Slower-running circuits use less power (but not
less energy to perform the same computation).
FPGA-Based System Design: Chapter 2
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Speed-power product
Also known as power-delay product.
 Helps measure quality of a logic family.
 For static CMOS:

– SP = P/f = CV2.

Static CMOS speed-power product is
independent of operating frequency.
– Voltage scaling depends on this fact.
– Considers only dynamic power.
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Sources of leakage






Weak inversion current (subthreshold current)
Gate-induced drain leakage at the gate/drain
overlap.
Drain-induced barrier lowering of the source.
Punchthrough currents.
Reverse-biased pn junctions.
etc.
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Subthreshold leakage current
Strong function of the threshold voltage Vt.
 Important in 90 nm and below technologies.
 Can adjust threshold by changing substrate
bias.
 Leakage through a chain of transistors is
lower than leakage through a single
transistor.

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Driving large loads

Sometimes, large loads must be driven:
– off-chip;
– long wires on-chip.

Sizing up the driver transistors only pushes
back the problem—driver now presents
larger capacitance to earlier stage.
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Cascaded driver circuit
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Optimal sizing
Use a chain of inverters, each stage has
transistors a larger than previous stage.
 Minimize total delay through driver chain:

– ttot = n(Cbig/Cg)1/n tmin.

Optimal number of stages:
– nopt = ln(Cbig/Cg).

Driver sizes are exponentially tapered with
size ratio a.
FPGA-Based System Design: Chapter 2
Copyright  2004 Prentice Hall PTR