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Chapter 3 – Computer System Structure Computer-System Structure Device Controller Interface ... busy Command done Status Error code ... busy done 0 0 idle 0 1 finished 1 0 working 1 1 (undefined) Data 0 Data 1 Logic Data n-1 Computer System Operation Each device controller is in charge of a particular device type (disk drive, video displays etc). I/O devices and the CPU can execute concurrently. Each device controller has a local buffer. CPU moves data from/to main memory to/from local buffers I/O is from the device to local buffer of controller. Device controller informs CPU that it has finished its operation by causing an interrupt. I/O Devices How does the computer communicate with an I/O device? device controller has a set of registers: Command reg., Status reg., Data regs., Address regs, etc. Status reg.: tells the computer the status of device: idle, busy, non functional, etc. A process can request an operation from device by placing a command in device’s Command reg. Data regs. Are used to exchange data Address regs: used to indicate address of source/destination Performing a Write Operation while(deviceNo.busy || deviceNo.done) <waiting>; deviceNo.data[0] = <value to write> deviceNo.command = WRITE; while(deviceNo.busy) <waiting>; deviceNo.done = TRUE; • Devices much slower than CPU • CPU waits while device operates • Would like to multiplex CPU to a different process while I/O is in process … CPU Ready Processes Ready Processes Ready Processes CPU-I/O Overlap … CPU Device … CPU Device I/O Operation Device Uses CPU External Interrupts Def 1. An external interrupt is a temporal suspension of a process caused by an event external to that process and performed in such a way that the process can be resumed. Def 2. An event external to the currently executing process that causes a change in the normal flow of instruction execution; usually generated by hardware devices external to the CPU Why Interrupt? People like connecting devices A computer is much more than the CPU Keyboard, mouse, screen, disk drives, Scanner, printer, sound card, camera, etc. These devices occasionally need CPU service But we can’t predict when External events typically occur on a macroscopic timescale We want to keep the CPU busy between events Need a way for CPU to find out devices need attention Possible Solution: Polling CPU periodically checks each device to see if it needs service Takes CPU time even when no requests pending can be efficient if events arrive rapidly “Polling is like picking up your phone every few seconds to see if you have a call. …” Alternative: Interrupts Give each device a wire (interrupt line) that it can use to signal the processor When interrupt signaled, processor executes a routine called an interrupt handler to deal with the interrupt No overhead when no requests pending “Polling is like picking up your phone every few seconds to see if you have a call. Interrupts are like waiting for the phone to ring.” Hardware Interrupt Handling Hardware Interrupt Handling CPU checks for interrupts after each instruction. If no interrupts, then fetch next instruction of current program. If an interrupt is pending, then suspend execution of the current program. The processor sends an acknowledgement signal to the device that issued the interrupt so that the device can remove its interrupt signal. Interrupt architecture saves the address of the interrupted instruction (and values of other registers). Interrupt transfers control to the interrupt service routine (Interrupt Handler), generally through the interrupt vector, which contains the addresses of all the service routines. Interrupt Handler A program that determines nature of the interrupt and performs whatever actions are needed Upon an interrupt, control is transferred to this program Generally part of the operating system Instruction Cycle with Interrupts Dealing with Multiple Interrupts Disable interrupt while processor is executing an interrupt (i.e. process the interrupts sequentially). Interrupts remain pending until the processor enables interrupts. After interrupt handler routine completes, the processor checks for additional interrupts. Assign priorities to interrupts. Higher priority interrupts cause lower-priority interrupts to wait. Causes a lower-priority interrupt handler to be interrupted. Example: when input arrives from communication line, it needs to be absorbed quickly to make room for more input. Dealing with Multiple Interrupts Traps A trap is a software-generated interrupt caused by an error, for example: arithmetic overflow/underflow division by zero execute illegal instruction reference outside user’s memory space Dual-Mode Operation Sharing system resources requires that the operating system ensures a level of protection to the users: an incorrect program can not cause other programs to execute incorrectly that a user program cannot have access resource for it does not have permission some operations should not be performed by user programs Provide hardware support to differentiate between at least two modes of operations. User mode Monitor mode (also kernel mode or system mode) – execution done on behalf of operating system. Dual-Mode Operation Mode bit was added to computer hardware (in Status Register) to indicate the current mode: monitor/system (0) or user (1). When an interrupt occurs, trap hardware switches to monitor mode, at the correct service routine in the monitor address space - safe! Must ensure that a user program could never gain control of the computer in monitor mode and privileged Instructions can be executed only in monitor mode. Going from User Mode to Supervisor Mode When a user program needs service from the OS (e.g. open a file, read, write, allocate memory etc.), it makes a system call: i.e. a call to one of the OS functions. OS functions must run in supervisor mode. User processes run in user mode. computer designers had to come up with some kind of approach that would allow a user process to miraculously change the CPU mode to supervisor and branch to one of these OS functions simultaneously. The trap instruction is just the ticket. Trap Instruction A trap instruction is a machine-level instruction that: Switches the CPU mode to supervisor Looks up the address of the target function in a kernel-space trap table Branches to the entry point of the kernel-space function using the address from the trap table The trick is that the instruction does all three of these steps rather than just one or two. And trap is the only instruction that sets the CPU mode bit to supervisor. Trap Instruction The system call is translated into a trap instruction the trap instruction is a machine level instruction that is part of the instruction set of the processor The trap instruction will do the following: change mode-bit to supervisor mode jump to a trap handler which will determine which OS function is being requested etc. Dual-Mode Operation (Cont.) Processor must provide the following: A Mode-bit flag Instruction set: privileged instructions and nonprivileged instructions A trap instruction CS4315 A. Berrached:CMS:UHD 24 Dual-Mode Operation Interrupt/fault/trap user monitor set user mode Trap instruction is used to switch to monitor mode I/O Protection All I/O devices need to be protected from wrongdoing by the users. Instruction to change the mode must be privileged All I/O instructions are privileged instructions. Thus user cannot issue I/O instructions directly. Given the I/O instructions are privileged, how does the user program perform I/O? Solution: System Calls (from user programs) I/O Protection When a system call is made, a trap instruction is executed: sets the mode to supervisor mode OS function verifies that parameters are correct and legal, executes the request, sets mode to user mode, and returns control to user program Use of A System Call to Perform I/O Memory Protection Must provide memory protection at least for the interrupt vector and the interrupt service routines. In general, OS should be protected from user programs and user programs from each other as well. In order to have memory protection, add two registers that determine the range of legal addresses a program may access: Base register – holds the smallest legal physical memory address. Limit register – contains the size of the range Example of Memory Protection Memory Protection CPU Protection A user program must be prevented from getting stuck in an infinite loop and never returning control to the OS. To accomplish this, a timer is used. A Timer interrupts computer after specified period to ensure operating system maintains control. Timer is decremented every clock tick. When timer reaches the value 0, an interrupt occurs. Timer commonly used to implement time sharing. Load-timer is a privileged instruction.