Download Cornelius et. al: Shadow Transistors

Encountering Gate Oxide Breakdown with
Shadow Transistors to Increase Reliability
Claas Cornelius1, Frank Sill2, Hagen Sämrow1, Jakob Salzmann1,
Dirk Timmermann1, Diógenes Cecílio da Silva Jr.2
1University
of Rostock, Germany
2 Federal University of Minas Gerais (UFMG), Brazil
Gramado, 3rd September 2008
1
Focus / Main ideas
1. Reliability regarding oxide breakdown
2. Transistor / Gate level approach
3. Selective insertion / thick oxide devices
Cornelius et. al: Shadow Transistors
2
Outline
 Motivation
– Technology development
– Error classification
– Time-Dependent Dielectric Breakdown (TDDB)
 Shadow Transistors
– Used model
– Main Ideas
– Algorithm
 Results
 Conclusion
Cornelius et. al: Shadow Transistors
3
Motivation
Technology development
[Mill.]
Transistors [Mill.]
Transistors
130 nm
400
400
90 nm
300
300
100
100
0
0
100 nm
Yonah
65 nm
151 Mill.
200
200
150 nm
Technology
Wolfdale
410 Mill.
500
500
Prescott
125 Mill.
45 nm
50 nm
Northwood
55 Mill.
Yonah,
151 Mill.
0 nm
2002
2002
2004
2004
Year
Year
2006
2006
2008
2008
Probability for failures increases due to:
 Increasing transistor count
 Shrinking technology
Cornelius et. al: Shadow Transistors
4
Motivation
Error classification
Error
Temporary
Permanent
Soft errors, Voltage
drop, Coupling, …
Reduced Performance
Process variations, Electromigration,
Oxide
wearout ...
Oxide
wearout
Cornelius et. al: Shadow Transistors
Malfunction
Electromigration,
Oxide breakdown ...
Oxide breakdown
5
Motivation
Time-Dependent Dielectric Breakdown (TDDB)

Tunneling currents
Wear out of gate oxide

Creation of conducting path
between Gate and Substrate,
Drain, Source

Depending on electrical field over
gate oxide, temperature (exp.),
Source: Pey&Tung
and gate oxide thickness (exp.)

Also: abrupt damage due to
extreme overvoltage (e.g. ElectroStatic Discharge)
Source: Pey&Tung
Cornelius et. al: Shadow Transistors
6
Motivation
TDDB ─ Trends
10000
16
Current Density Jox
Reliability (Weibull slope β)
Increasing probability for Gate-Oxide-Breakdown
12
8
4
0
1000
100
high-k?
10
1
0
2
4
6
8
10
12
Gate Oxide Thickness [nm]
Source: Kauerauf, EDL, 2002
Cornelius et. al: Shadow Transistors
180 nm 90 nm
45 nm
22 nm
Technology
Source: Borkar, Intel
7
Shadow Transistors
Applied model
TDDB between gate and channel
Gate
For an Inverter, 65nm-BPTM:
Gate Oxide
Source
Drain
100%
20
75%
15
50%
Model:
RGC
W
W1
W2
W= W1+W2
Cornelius et. al: Shadow Transistors
Vout/VDD
rel. delay
10
25%
5
0%
0
- RGC [kΩ] →
Based on: Segura et. al., “A Detailed Analysis of GOS Defects
in MOS Transistors: Testing Implications at Circuit Level” 1995.
8
Shadow Transistors
Applied model
TDDB between gate and source/drain
Gate
For an Inverter, 65nm-BPTM:
Gate Oxide
Source
Drain
100%
75%
Vout/VDD
50%
Model:
25%
RGD
RGS
W
W
0%
-RGC [kΩ] →
Based on: Segura et. al., “A Detailed Analysis of GOS Defects
in MOS Transistors: Testing Implications at Circuit Level” 1995.
Cornelius et. al: Shadow Transistors
9
Shadow Transistors
Main idea (1) ─ Parallel transistors
1. Insertion of additional transistors in
parallel to vulnerable transistors
Shadow transistors (ST)
VDD/Vout
Relative Delay
10
8
6
4
2
0
100%
wo/ ST
75%
w/ ST
50%
w/ ST
wo/ ST
25%
0%
R
- GC [kΩ] →
-R
GC
[kΩ] →
For an Inverter, 65nm-BPTM
Cornelius et. al: Shadow Transistors
10
Shadow Transistors
Main idea (2) ─ Thick gate oxides
H-Vt/To
2. Application of H-Vt/To transistors with:
– Higher threshold voltage
– Thicker gate oxide
Less vulnerable to TDDB
10
tox
0.22
MTTF – Mean Time To Failure
0.15
MTTFH Vt / To
 10 0.22  4.81
MTTFLVt / To
Source: Srinivasan, “RAMP: A Model for Reliability Aware Microprocessor Design”
Stathis, J., “Reliability Limits for the Gate Insulator in CMOS Technology”
Cornelius et. al: Shadow Transistors
11
Shadow Transistors
Main idea (3) ─ Selective insertion
3. Selective insertion of shadow transistors in parallel to vulnerable
transistors:
– Component reliability depends on
Activity, state, temperature, size, fabrication …
Most vulnerable can be identified
Netlist
modification
Cornelius et. al: Shadow Transistors
Shadow transistors
only added in parallel
to most vulnerable
devices.
12
Shadow Transistors
Main idea (3) ─ Selective insertion
3. Selective insertion of shadow transistors in parallel to vulnerable
transistors:
– Component reliability depends on
Our Approach



Activity, state, temperature, size, fabrication …
Estimation of stress factors
Most vulnerable can be identified
Determination of components reliability
Adding redundancy only at most vulnerable components
 Advantage: Lower area, power and delay penalty compared to
complete redundancy or random insertion [Sri04]
Shadow transistors
Source:
[Sri04]
Sirisantana, D&T, 2004
Netlist
only added in parallel
modification
to most vulnerable
devices.
Cornelius et. al: Shadow Transistors
13
Shadow Transistors
Main ideas ─ Discussion
Advantages
 Increased reliability in respect to TDDB
 H-Vt/To: Reliability increases by ~5x (for Δtox = 0.15 nm)
 Remarkable increase of system life time
Drawbacks


Higher input capacity → higher delay and dynamic power dissipation
Area increase
Remarks


Only slight improvements for Gate-Drain/Source breakdown
H-Vt/To has to be supported by technology
Cornelius et. al: Shadow Transistors
14
Shadow Transistors
Algorithm
Estimation of logical Signal
Probabilities (SP)
Insertion of Shadow transistors
where SP is lower (PMOS) than
threshold value SPth or higher
(NMOS) than 1 - SPth
Modification of SPth
depending on Δtd / MTTF
Estimation of delay increase Δtd
and new Mean Time To Failure
(MTTF)
Cornelius et. al: Shadow Transistors
15
Results
Improvemnet of MTTF as regards TDDB
Improvement MTTF (L-Vt/To)
≈ 23 % additional transistors
20%
15%
10%
5%
0%
c17
c432 c499
c880 c1355 c1908 c2670 c3540 c5315 c6288 c7552
our algorithm
random insertion
Insertion of L-Vt/To Shadow Transistors
Cornelius et. al: Shadow Transistors
16
Results
Performance Reduction (L-Vt/To)
≈ 23 % additional transistors
Increase of circuit's delay
20%
15%
10%
5%
0%
c17
c432 c499
c880 c1355 c1908 c2670 c3540 c5315 c6288 c7552
our algorithm
random insertion
Insertion of L-Vt/To Shadow Transistors
Cornelius et. al: Shadow Transistors
17
Results
Application of H-Vt/To-ST
Improvemnet of MTTF as regards TDDB
≈ 23 % additional transistors
60%
45%
30%
15%
0%
c432
c499
c880 c1355 c1908 c2670 c3540 c5315 c6288 c7552
H-Vt/To-ST
Cornelius et. al: Shadow Transistors
L-Vt-To-ST
18
Results
Improvemnet of MTTF as regards TDDB
Modification of Ccrit
250%
200%
150%
100%
50%
0%
c432 c499 c880 c1355 c1908 c2670 c3540 c5315 c6288 c7552
SPth = 30
SPth = 55
Insertion of H-Vt/To Shadow Transistors
Cornelius et. al: Shadow Transistors
19
Conclusion
 System reliability decreases with shrinking technologies and rising
transistor count
 Increasing probability of Time-Dependent Dielectric Breakdown
(TDDB)
 Insertion of Shadow Transistors (ST) increases system lifetime
 Remarkable improvements by application of transistors with thick
gate-oxide
 Selective insertion of ST improves trade-off between reliability and
performance
 Impact and amount of redundant transistors can be adapted by the
threshold value SPth
Cornelius et. al: Shadow Transistors
20
Thank you!
[email protected]
[email protected]
Cornelius et. al: Shadow Transistors
21