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Lecture #19 ANNOUNCEMENTS • • • • Midterm 2 Thursday Nov. 18, 12:40-2:00 pm A-L initials in F295 Haas Business School M-Z initials in Sibley auditorium Closed book, except for an 8.5 x 11 inch sheet of notes, calculator OK, no cell phones. • HW 9 will be due no later than 4 pm Friday Nov. 12 because of the Veteran’s Day holiday Nov. 11 OUTLINE – The CMOS inverter (cont’d) – CMOS logic gates – The body effect Reading (Rabaey et al.) Chapter 5.5.1 (p.220 – original book’s pagination) EECS40, Fall 2004 Lecture 19, Slide 1 Prof. White Features of CMOS Digital Circuits • The output is always connected to VDD or GND in steady state Full logic swing; large noise margins Logic levels are not dependent upon the relative sizes of the devices (“ratioless”) • There is no direct path between VDD and GND in steady state no static power dissipation EECS40, Fall 2004 Lecture 19, Slide 2 Prof. White The CMOS Inverter: Current Flow during Switching N: sat P: sat VOUT N: off P: lin VDD VDD S G i VOUT A D G C N: sat P: lin D VIN B D E N: lin P: sat S N: lin P: off 0 VDD 0 EECS40, Fall 2004 i Lecture 19, Slide 3 VIN Prof. White Power Dissipation due to Direct-Path Current VDD VDD vIN: S G D i vIN S VT 0 Ipeak vOUT D G VDD-VT i: 0 tsc Energy consumed per switching period: EECS40, Fall 2004 Lecture 19, Slide 4 time Edp t scVDD I peak Prof. White N-Channel MOSFET Operation An NMOSFET is a closed switch when the input is high A A B B Y X Y X Y = X if A and B Y = X if A or B NMOSFETs pass a “strong” 0 but a “weak” 1 EECS40, Fall 2004 Lecture 19, Slide 5 Prof. White P-Channel MOSFET Operation A PMOSFET is a closed switch when the input is low A A B B Y X Y X Y = X if A and B = (A + B) Y = X if A or B = (AB) PMOSFETs pass a “strong” 1 but a “weak” 0 EECS40, Fall 2004 Lecture 19, Slide 6 Prof. White Pull-Down and Pull-Up Devices • In CMOS logic gates, NMOSFETs are used to connect the output to GND, whereas PMOSFETs are used to connect the output to VDD. – An NMOSFET functions as a pull-down device when it is turned on (gate voltage = VDD) – A PMOSFET functions as a pull-up device when it is turned on (gate voltage = GND) VDD A1 input signals A2 AN A1 A2 AN EECS40, Fall 2004 Pull-up network PMOSFETs only F(A1, A2, …, AN) Pull-down network Lecture 19, Slide 7 NMOSFETs only Prof. White CMOS NAND Gate VDD A A B 0 0 0 1 1 0 1 1 B F 1 1 1 0 F A B EECS40, Fall 2004 Lecture 19, Slide 8 Prof. White CMOS NOR Gate VDD A B 0 0 0 1 1 0 1 1 A F 1 0 0 0 B F B EECS40, Fall 2004 A Lecture 19, Slide 9 Prof. White CMOS Pass Gate A Y X Y = X if A A EECS40, Fall 2004 Lecture 19, Slide 10 Prof. White The “Body Effect” VT is a function of VSB: VT VT 0 2F VSB 2F kT N B where F ln q ni is the body effect coefficient When the body-source pn junction is reverse-biased, |VT| increases. Usually, we want to minimize so that IDsat will be the same for all transistors in a circuit. EECS40, Fall 2004 Lecture 19, Slide 11 Prof. White Example (0.25mm CMOS technology) 0.9 0.85 0.8 0.75 VT (V) 0.7 0.65 0.6 0.55 0.5 0.45 0.4 -2.5 -2 -1.5 -1 V BS EECS40, Fall 2004 -0.5 0 (V) Lecture 19, Slide 12 Prof. White