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A few notes for your design
 Finger and multiplier in schematic design
 Parametric analysis
 Monte-Carlo analysis
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Multi-Fingered Transistors
One finger
Two fingers (folded)
Less diffusion capacitance
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Digital Integrated
Circuits
A Design Perspective
Jan M. Rabaey
Anantha Chandrakasan
Borivoje Nikolić
Designing Combinational
Logic Circuits
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Multistage Networks
N
Delay   t p 0  pi  g i  f i 
i 1
Stage effort: hi = gi fi
Path electrical effort: F = Cout / Cin
Path logical effort: G = g1g2…gN
Path effort: H = GF
Path delay D = Sdi = Spi + Shi
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Optimum Effort per Stage
When each stage bears the same effort:
hN  H
hN H
Stage efforts: g1f1 = g2f2 = … = gNfN
Effective fanout of each stage: f i  h g i
Minimum path delay
Dˆ   gi f i  pi   NH 1/ N  P
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Example: Optimize Path
1
a
g1 = 1
g2 = 5/3
b
c
5
g3 = 5/3
g4 = 1
Effective fanout F = 5, G = 25/9  H = GF=125/9=13.9  h=1.93
so, f1=h/g=1.93, f2=1.93*3/5=1.16, f3=1.16, f4=1.93
(note fi: effective fanout for the ith stage)
a = f1*g1/g2=1.16 (of minimum-size 3-input NAND gate)
(a*g2/g1*1=f1)
b = f1*f2*g1/g3 = 1.34 (of minimum-size 2-input NOR gate)
(b*g3/g2*a=f2)
c = f1*f2*f3*g1/g4 = 2.59 (of minimum-size inverter)
(c*g4/g3*b=f3)
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Add Branching Effort
Branching effort:
b
Con path  Coff  path
Con path
A parameter used to account for how
much sizing is attributed to the critical path
fi 
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Con  Coff
Ci
Con (b  1)Con


 f i ,old b
Ci
Ci
8
Combinational Circuits
Multistage Networks
N
Delay   t p 0  pi  g i  f i 
i 1
Stage effort: hi = gi fi
Path electrical effort: F = Cout / Cin
Path logical effort: G = g1g2…gN
Branching effort: B = b1b2…bN
Path effort: H = GFB
Path delay D = Sdi = Spi + Shi
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Example – 8-input AND
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Optimal Number of Stages
For a given load,
and given input capacitance of the first gate
Find optimal number of stages and optimal sizing
D  NH 1/ N  Npinv
D
  H 1/ N ln H 1/ N  H 1/ N  pinv  0
N


Substitute ‘best stage effort’
hH
1/ Nˆ
best number of stages N ~ log4H
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Method of Logical Effort

Compute the path effort: H = GFB

Find the best number of stages N ~ log4H

Compute the stage effort h = H1/N

Sketch the path with this number of stages

Work from either end, find sizes
Reference: Sutherland, Sproull, Harris, “Logical Effort”, Morgan-Kaufmann, 1999.
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Summary
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Power consumption of static gates
 It is a strong function of transistor sizes (which affects
physical capacitance), input and output rise and fall time,
device thresholds, temperature and switching activity.
 Switching activity is a strong function of logic function to
be implemented (nature of the gate), also input signal
statistics such as inter-signal dependency.
 Estimate switching activity for the overall chip is a very
difficult task.
eg. For NOR gate, PA, PB the probabilities that input A and
B stays at 1. Transition probability is then:
∂0->1 = [1-(1-PA)(1-PB)] (1-PA)(1-PB)
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Complementary MOS Properties
Full rail-to-rail swing; high noise margins
 Logic levels not dependent upon the relative
device sizes; ratioless
 Always a path to Vdd or Gnd in steady state;
low output impedance
 Extremely high input resistance; nearly zero
steady-state input current
 No direct path steady state between power
and ground; no static power dissipation
 Propagation delay as function of load
capacitance and resistance of transistors

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Summary: Static Complementary Gates
 Static CMOS Complementary Gates is highly robust,
scalable and easy to be designed.
 One possible drawback is 2N number of transistors to
implement an N-input logic function.
 Another drawback is that parasitic capacitance is
significant (driving two devices for fan-in and fan-out)
 This opens the door for alternative logic design styles
(either simpler or faster)
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Ratioed Logic
Static/dynamic
Ratioed/ratioless
Complementary/noncomplementary
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Ratioed Logic
VDD
Resistive
Load
VDD
Depletion
Load
RL
PDN
VSS
(a) resistive load
PMOS
Load
VSS
VT < 0
F
In1
In2
In3
VDD
F
In1
In2
In3
PDN
VSS
(b) depletion load NMOS
F
In1
In2
In3
PDN
VSS
(c) pseudo-NMOS
Goal: to reduce the number of devices over complementary CMOS
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Ratioed Logic
In ratioed logic, the entire PUN is replaced with a single
unconditional load device that pulls up the output for logic “1”
VDD
• N transistors + Load
Resistive
Load
• VOH = V DD
RL
• VOL =
F
In1
In2
In3
Not zero!!
RPN + RL
• Assymetrical response
PDN
• Static power consumption
VSS
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• tpL= 0.69 RLCL
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Active Loads
Voltage swing now depend on the ratio of NMOS/PMOS (in
contrast to ratioless complementary logic), so named ratioed
VDD
Depletion
Load
VDD
PMOS
Load
VT < 0
VSS
F
In1
In2
In3
PDN
VSS
depletion load NMOS
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F
In1
In2
In3
PDN
VSS
pseudo-NMOS
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Combinational Circuits
Pseudo-NMOS
A
VDD
B
C
D
F
CL
VOH = VDD (similar to complementary CMOS)
Linear
region
2
V OL
kp


2
k n  VDD – V Tn  V OL – -------------  = ------  V DD – VTp 
2 
2

kp
V OL =  VDD – V T  1 – 1 – ------ (assuming that V T = V Tn = VTp )
kn
SMALLER AREA & LOAD BUT STATIC POWER DISSIPATION!!!
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Pseudo-NMOS inverter VTC
Fix W/L=2 for NMOS transistor
3.0
2.5
W/L
2.0
p
=4
[V]
1.5
V
ou t
W/L
p
=2
1.0
W/L
p
= 0.5
W/L
0.5
W/L
p
p
=1
= 0.25
0.0
0.0
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0.5
1.0
1.5
2.0
2.5
V
in
[V]22
Combinational Circuits
Ratioed logic with better loads
 It is possible to create a ratioed logic that completely
eliminates static currents and provides rail-to-rail swing
 Such logic combines two concepts: differential logic and
positive feedback (make sure that load device is turned off
when not needed)
 An example of such a logic family is called DCVSL
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Improved Loads
V DD
M1
V DD
M2
Out
Out
A
A
B
B
PDN1
PDN2
V SS
V SS
Both the logic and its inverse are simultaneously implemented
Differential Cascode Voltage Switch Logic (DCVSL)
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DCVSL Example
It is possible to share transistors among the two pull-down
networks. DCVSL gives rail-to-rail swing and eliminates static
power dissipation. But short-circuit power may be a problem.
Out
Out
B
B
A
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B
B
A
XOR-NXOR gate
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Combinational Circuits
DCVSL Transient Response
Delay:
2.5
In->out 197ps
V ol ta ge [V]
AB
1.5
In->out’ 321ps
AB
VS
A, B
A,B
0.5
-0.5
0
0.2
200ps for
Static MOS
0.4
0.6
0.8
1.0
Time [ns]
Still ratioed since sizing of PMOS/NMOS critical to function
Short-circuit path due to simultaneous on of PMOS/NMOS
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Pass-Transistor
Logic
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Pass-Transistor Logic
Inputs
B
Switch
Out
A
Out
Network
B
B
• N transistors
• No static consumption
Allow inputs to drive source/drain terminals as well as
gate terminals
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Example: AND Gate
NMOS only
B
A
B
F = AB
0
Is B redundant?
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NMOS-Only Logic
Unfortunately, NMOS passes strong 0 but weak 1 (the
situation is even worsened by body effect)
3.0
In
In
VDD
x
Out
0.5m/0.25m
0.5m/0.25m
V o lt a ge [V]
1.5m/0.25m
Out
2.0
x
1.0
0.0
0
0.5
1
1.5
2
Time [ns]
Avoid cascading multiple pass-logic without buffering!!!
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NMOS-only Switch
C=
A=
2.5 V
C=
A=
2.5 V
C
2.5 V
L
M
2
M
1
B
M
B
2.5 V
n
VB does not pull up to 2.5V, but 2.5V - VTN
Though smaller voltage swing causes smaller dynamic
power consumption, threshold voltage loss causes
static power consumption of following inverters
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