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Digital Integrated Circuits A Design Perspective Designing Combinational Logic Circuits November 2002. EE141 Integrated © Digital Circuits2nd 1 Combinational Circuits Combinational vs. Sequential Logic In In Out Out Combinational Output = f(In) EE141 Integrated © Digital Circuits2nd Sequential Output = f(In, Previous In) 2 Combinational Circuits Static CMOS Circuit 1. At every point in time (except during the switching transients) each gate output is connected to either VDD or Vss via a low-resistive path. 2. The outputs of the gates assume at all times the value of the Boolean function, implemented by the circuit (ignoring, once again, the transient effects during switching periods). 3. This is in contrast to the dynamic circuit class, which relies on temporary storage of signal values on the capacitance of high impedance circuit nodes. EE141 Integrated © Digital Circuits2nd 3 Combinational Circuits Static Complementary CMOS VDD In1 In2 PUN InN In1 In2 InN PMOS only F(In1,In2,…InN) PDN NMOS only PUN and PDN are dual logic networks EE141 Integrated © Digital Circuits2nd 4 Combinational Circuits NMOS Transistors in Series/Parallel Connection Transistors can be thought as a switch controlled by its gate signal NMOS switch closes when switch control input is high A B X Y Y = X if A and B A X B Y Y = X if A OR B NMOS Transistors pass a “strong” 0 but a “weak” 1 EE141 Integrated © Digital Circuits2nd 5 Combinational Circuits PMOS Transistors in Series/Parallel Connection PMOS switch closes when switch control input is low A B X Y Y = X if A AND B = A + B A X B Y Y = X if A OR B = AB PMOS Transistors pass a “strong” 1 but a “weak” 0 EE141 Integrated © Digital Circuits2nd 6 Combinational Circuits Threshold Drops VDD PUN VDD S D VDD D 0 VDD VGS S CL VDD 0 PDN D VDD S EE141 Integrated © Digital Circuits2nd CL 0 VDD - VTn CL VGS VDD |VTp| S CL D 7 Combinational Circuits Complementary CMOS Logic Style EE141 Integrated © Digital Circuits2nd 8 Combinational Circuits Example Gate: NAND EE141 Integrated © Digital Circuits2nd 9 Combinational Circuits Example Gate: NOR EE141 Integrated © Digital Circuits2nd 10 Combinational Circuits Complex CMOS Gate B A C D OUT = D + A • (B + C) A D B EE141 Integrated © Digital Circuits2nd C 11 Combinational Circuits Cell Design Standard Cells General purpose logic Can be synthesized Same height, varying width Datapath Cells For regular, structured designs (arithmetic) Includes some wiring in the cell Fixed height and width EE141 Integrated © Digital Circuits2nd 12 Combinational Circuits Standard Cells N Well VDD Cell height 12 metal tracks Metal track is approx. 3 + 3 Pitch = repetitive distance between objects Cell height is “12 pitch” In 2 Cell boundary EE141 Integrated © Digital Circuits2nd Out GND Rails ~10 13 Combinational Circuits Standard Cells VDD 2-input NAND gate VDD B A B Out A GND EE141 Integrated © Digital Circuits2nd 14 Combinational Circuits Stick Diagrams Contains no dimensions Represents relative positions of transistors VDD VDD Inverter NAND2 Out Out In GND EE141 Integrated © Digital Circuits2nd GND A B 15 Combinational Circuits Stick Diagrams Logic Graph A j X C C B X = C • (A + B) C i A B A B C EE141 Integrated © Digital i X VDD j B Circuits2nd PUN GND A PDN 16 Combinational Circuits Two Stick Layouts of !(C • (A + B)) A C B A B C VDD VDD X X GND GND uninterrupted diffusion strip EE141 Integrated © Digital Circuits2nd 17 Combinational Circuits Consistent Euler Path An uninterrupted diffusion strip is possible only if there exists a Euler path in the logic graph Euler path: a path through all nodes in the graph such that each edge is visited once and only once. X C i X B VDD j GND A A B C For a single poly strip for every input signal, the Euler paths in the PUN and PDN must be consistent (the same) 18 EE141 Integrated Circuits2nd © Digital Combinational Circuits Example:1. Draw Logic Graph EE141 Integrated © Digital Circuits2nd Identify each transistor by a unique name of its gate signal (A, B, C, D, E in the example of Figure 1). Identify each connection to the transistor by a unique name (1,2,3,4 in the example of Figure 1). 19 Combinational Circuits Example:2. Define Euler Path EE141 Integrated © Digital Circuits2nd Euler paths are defined by a path the traverses each node in the path, such that each edge is visited only once. The path is defined by the order of each transistor name. If the path traverses transistor A then B then C. Then the path name is {A, B, C} The Euler path of the Pull up network must be the same as the path of the Pull down network. Euler paths are not necessarily unique. It may be necessary to redefine the function to find a Euler path. F = E + (CD) + (AB) = (AB) +E + (CD) 20 Combinational Circuits Example:3.Connection label layout EE141 Integrated © Digital Circuits2nd 21 Combinational Circuits Example:4.VDD, VSS and Output Labels EE141 Integrated © Digital Circuits2nd 22 Combinational Circuits Example:5.Interconnected EE141 Integrated © Digital Circuits2nd 23 Combinational Circuits OAI22 Logic Graph A C B D X D X = (A+B)•(C+D) C D A B EE141 Integrated © Digital Circuits2nd C VDD X B A B C D PUN A GND PDN 24 Combinational Circuits Example: x = ab+cd x x c b VDD x a c b VD D x a d GND d GND (a) Logic graphs for (ab+cd) (b) Euler Paths {a b c d} VD D x GND a b c d (c) stick diagram for ordering {a b c d} EE141 Integrated © Digital Circuits2nd 25 Combinational Circuits CMOS Properties Full rail-to-rail swing; high noise margins Logic levels not dependent upon the relative device sizes; ratioless Always a path to Vdd or Gnd in steady state; low output impedance Extremely high input resistance; nearly zero steady-state input current No direct path steady state between power and ground; no static power dissipation Propagation delay function of load capacitance and resistance of transistors EE141 Integrated © Digital Circuits2nd 26 Combinational Circuits Switch Delay Model Req A A Rp A Rp Rp B Rn Rp CL Rn A Cint INV NAND2 Circuits2nd Cint A A EE141 Integrated © Digital Rp A B Rn B CL Rn Rn A B CL NOR2 27 Combinational Circuits Input Pattern Effects on Delay Delay is dependent on the pattern of inputs Low to high transition Rp A Rp B Rn both inputs go low – delay is 0.69 Rp/2 CL CL one input goes low B Rn – delay is 0.69 Rp CL Cint A High to low transition both inputs go high – delay is 0.69 2Rn CL EE141 Integrated © Digital Circuits2nd 28 Combinational Circuits Delay Dependence on Input Patterns 3 Input Data Pattern Delay (psec) A=B=01 67 A=1, B=01 64 A= 01, B=1 61 0.5 A=B=10 45 0 A=1, B=10 80 A= 10, B=1 81 A=B=10 2.5 Voltage [V] 2 A=1 0, B=1 1.5 A=1, B=10 1 -0.5 0 100 200 time [ps] EE141 Integrated Circuits2nd © Digital 300 400 NMOS = 0.5m/0.25 m PMOS = 0.75m/0.25 m CL = 100 fF 29 Combinational Circuits Transistor Sizing Rp 2 A Rp B Rn 2 B 2 Rn A EE141 Integrated © Digital Circuits2nd Rp 4 B 2 CL Cint Rp 4 Cint A 1 Rn Rn A B CL 1 30 Combinational Circuits Transistor Sizing a Complex CMOS Gate A B 8 6 C 8 6 4 3 D 4 6 OUT = D + A • (B + C) A D 1 B EE141 Integrated © Digital Circuits2nd 2 2C 2 31 Combinational Circuits Fan-In Considerations A B C D A CL B C3 C C2 D C1 EE141 Integrated © Digital Circuits2nd Distributed RC model (Elmore delay) tpHL = 0.69 Reqn(C1+2C2+3C3+4CL) Propagation delay deteriorates rapidly as a function of fan-in – quadratically in the worst case. 32 Combinational Circuits tp as a Function of Fan-In 1250 quadratic tp (psec) 1000 Gates with a fan-in greater than 4 should be avoided. 750 tpH 500 tp L 250 tpL linear H 0 2 4 6 8 10 12 14 16 fan-in EE141 Integrated © Digital Circuits2nd 33 Combinational Circuits tp as a Function of Fan-Out tpNOR2 tpNAND2 tpINV tp (psec) 2 All gates have the same drive current. Slope is a function of “driving strength” 4 6 8 10 12 14 16 eff. fan-out EE141 Integrated © Digital Circuits2nd 34 Combinational Circuits tp as a Function of Fan-In and Fan-Out Fan-in: quadratic due to increasing resistance and capacitance Fan-out: each additional fan-out gate adds two gate capacitances to CL tp = a1FI + a2FI2 + a3FO EE141 Integrated © Digital Circuits2nd 35 Combinational Circuits Fast Complex Gates: Design Technique 1 Transistor sizing as long as fan-out capacitance dominates Progressive InN sizing CL MN In3 M3 C3 In2 M2 C2 In1 M1 C1 EE141 Integrated © Digital Circuits2nd Distributed RC line M1 > M2 > M3 > … > MN (the fet closest to the output is the smallest) Can reduce delay by more than 20%; decreasing gains as technology shrinks 36 Combinational Circuits Fast Complex Gates: Design Technique 2 Transistor ordering critical path charged CL In3 1 M3 In2 1 M2 C2 charged In1 M1 01 C1 charged delay determined by time to discharge CL, C1 and C2 EE141 Integrated © Digital Circuits2nd critical path 01 In1 M3 CLcharged In2 1 M2 C2 discharged In3 1 M1 C1 discharged delay determined by time to discharge CL 37 Combinational Circuits Fast Complex Gates: Design Technique 3 Alternative logic structures F = ABCDEFGH EE141 Integrated © Digital Circuits2nd 38 Combinational Circuits Fast Complex Gates: Design Technique 4 Isolating fan-in from fan-out using buffer insertion CL EE141 Integrated © Digital Circuits2nd CL 39 Combinational Circuits Fast Complex Gates: Design Technique 5 Reducing the voltage swing tpHL = 0.69 (3/4 (CL VDD)/ IDSATn ) = 0.69 (3/4 (CL Vswing)/ IDSATn ) linear reduction in delay also reduces power consumption But the following gate is much slower! Or requires use of “sense amplifiers” on the receiving end to restore the signal level (memory design) EE141 Integrated © Digital Circuits2nd 40 Combinational Circuits Ratioed Logic EE141 Integrated © Digital Circuits2nd 41 Combinational Circuits Ratioed Logic VDD Resistive Load VDD Depletion Load RL PDN VSS (a) resistive load PMOS Load VSS VT < 0 F In1 In2 In3 VDD F In1 In2 In3 PDN VSS (b) depletion load NMOS F In1 In2 In3 PDN VSS (c) pseudo-NMOS Goal: to reduce the number of devices over complementary CMOS EE141 Integrated © Digital Circuits2nd 42 Combinational Circuits Ratioed Logic VDD • N transistors + Load Resistive Load • VOH = V DD RL • VOL = F In1 In2 In3 RPN + RL • Assymetrical response PDN • Static power consumption VSS EE141 Integrated © Digital RPN Circuits2nd • tpL= 0.69 RLCL 43 Combinational Circuits Active Loads VDD Depletion Load VDD PMOS Load VT < 0 VSS F In1 In2 In3 PDN VSS depletion load NMOS EE141 Integrated © Digital Circuits2nd F In1 In2 In3 PDN VSS pseudo-NMOS 44 Combinational Circuits Pseudo-NMOS VDD A B C D F CL VOH = VDD (similar to complementary CMOS) 2 V OL kp 2 k n VDD – V Tn V OL – ------------- = ------ V DD – VTp 2 2 kp V OL = VDD – V T 1 – 1 – -----(assuming that V T = V Tn = VTp ) kn SMALLER AREA & LOAD BUT STATIC POWER DISSIPATION!!! EE141 Integrated © Digital Circuits2nd 45 Combinational Circuits Pseudo-NMOS VTC 3.0 2.5 W/Lp = 4 Vout [V] 2.0 1.5 W/Lp = 2 1.0 0.5 W/Lp = 0.5 W/Lp = 1 W/Lp = 0.25 0.0 0.0 0.5 1.0 1.5 2.0 2.5 Vin [V] EE141 Integrated © Digital Circuits2nd 46 Combinational Circuits Improved Loads VDD M1 Enable M2 M1 >> M2 F A B C D CL Adaptive Load EE141 Integrated © Digital Circuits2nd 47 Combinational Circuits Improved Loads (2) VDD M1 VDD M2 Out A A B B Out PDN1 PDN2 VSS VSS Differential Cascode Voltage Switch Logic (DCVSL) EE141 Integrated © Digital Circuits2nd 48 Combinational Circuits DCVSL Example Out Out B B A B B A XOR-NXOR gate EE141 Integrated © Digital Circuits2nd 49 Combinational Circuits DCVSL Transient Response V olta ge [V] 2.5 AB 1.5 0.5 -0.5 0 EE141 Integrated © Digital Circuits2nd AB A,B 0.2 A,B 0.4 0.6 Time [ns] 0.8 1.0 50 Combinational Circuits Pass-Transistor Logic EE141 Integrated © Digital Circuits2nd 51 Combinational Circuits Pass-Transistor Logic Inputs B Switch Out A Out Network B B • N transistors • No static consumption EE141 Integrated © Digital Circuits2nd 52 Combinational Circuits NMOS-Only Logic 3.0 In 1.5m/0.25m VDD x Out 0.5m/0.25m 0.5m/0.25m Voltage [V] In Out 2.0 x 1.0 0.0 0 0.5 1 1.5 2 Time [ns] EE141 Integrated © Digital Circuits2nd 53 Combinational Circuits NMOS-only Switch C = 2.5V C = 2.5 V M2 A = 2.5 V A = 2.5 V B B Mn CL M1 VB does not pull up to 2.5V, but 2.5V - VTN Threshold voltage loss causes static power consumption NMOS has higher threshold than PMOS (body effect) EE141 Integrated © Digital Circuits2nd 54 Combinational Circuits NMOS Only Logic Solution 1: Level Restoring Transistor VDD VDD Level Restorer Mr B A Mn M2 X Out M1 • Advantage: Full Swing • Restorer adds capacitance, takes away pull down current at X • Ratio problem EE141 Integrated © Digital Circuits2nd 55 Combinational Circuits Solution 2: Single Transistor Pass Gate with VT=0 VDD VDD 0V 2.5V VDD 0V Out 2.5V WATCH OUT FOR LEAKAGE CURRENTS EE141 Integrated © Digital Circuits2nd 56 Combinational Circuits Complementary Pass Transistor Logic A A B B Pass-Transistor F Network (a) A A B B B Inverse Pass-Transistor Network B B A F B B A A B F=AB A B F=A+B F=AB AND/NAND EE141 Integrated © Digital Circuits2nd A F=AÝ (b) A A B B F=A+B B OR/NOR A F=AÝ EXOR/NEXOR 57 Combinational Circuits Solution 3: Transmission Gate C A C A B B C C C = 2.5 V A = 2.5 V B CL C=0V EE141 Integrated © Digital Circuits2nd 58 Combinational Circuits Resistance of Transmission Gate 30 2.5 V Resistance, ohms Rn 20 Rp 2.5 V Rn Vou t Rp 0V 10 Rn || Rp 0 0.0 EE141 Integrated © Digital 1.0 Circuits2nd Vou t , V 2.0 59 Combinational Circuits Pass-Transistor Based Multiplexer S S S S VDD S A VDD M2 F S M1 B S GND In1 EE141 Integrated © Digital Circuits2nd In2 60 Combinational Circuits Transmission Gate XOR B B M2 A A F M1 M3/M4 B B EE141 Integrated © Digital Circuits2nd 61 Combinational Circuits Transmission Gate Full Adder P VDD Ci A P A A P B VDD Ci A P Ci VDD S Sum Generation Ci P B VDD A P Co Carry Generation Ci A Setup P Similar delays for sum and carry EE141 Integrated © Digital Circuits2nd 62 Combinational Circuits Dynamic Logic EE141 Integrated © Digital Circuits2nd 63 Combinational Circuits Dynamic CMOS In static circuits at every point in time (except when switching) the output is connected to either GND or VDD via a low resistance path. fan-in of n requires 2n (n N-type + n P-type) devices Dynamic circuits rely on the temporary storage of signal values on the capacitance of high impedance nodes. requires on n + 2 (n+1 N-type + 1 P-type) transistors EE141 Integrated © Digital Circuits2nd 64 Combinational Circuits Dynamic Gate Clk Clk Mp off Mp on Out In1 In2 In3 Clk CL PDN 1 Out ((AB)+C) A C B Me Clk off Me on Two phase operation Precharge (Clk = 0) Evaluate (Clk = 1) EE141 Integrated © Digital Circuits2nd 66 Combinational Circuits Conditions on Output Once the output of a dynamic gate is discharged, it cannot be charged again until the next precharge operation. Inputs to the gate can make at most one transition during evaluation. Output can be in the high impedance state during and after evaluation (PDN off), state is stored on CL EE141 Integrated © Digital Circuits2nd 67 Combinational Circuits Properties of Dynamic Gates Logic function is implemented by the PDN only number of transistors is N + 2 (versus 2N for static complementary CMOS) Full swing outputs (VOL = GND and VOH = VDD) Faster switching speeds reduced load capacitance due to lower input capacitance (Cin) reduced load capacitance due to smaller output loading (Cout) no Isc, so all the current provided by PDN goes into discharging CL Overall power dissipation usually higher than static CMOS Low noise margin (NML) Needs a precharge/evaluate clock EE141 Integrated © Digital Circuits2nd 68 Combinational Circuits Issues in Dynamic Design 1: Charge Leakage CLK Clk Mp Out CL A Clk Evaluate VOut Me Precharge Leakage sources Dominant component is subthreshold current EE141 Integrated © Digital Circuits2nd 69 Combinational Circuits Solution to Charge Leakage Keeper Clk Mp A Mkp CL Out B Clk Me Same approach as level restorer for pass-transistor logic EE141 Integrated © Digital Circuits2nd 70 Combinational Circuits Issues in Dynamic Design 2: Clk Mp Out A CL B=0 Clk Charge Sharing Charge stored originally on CL is redistributed (shared) over CL and CA leading to reduced robustness CA Me EE141 Integrated © Digital CB Circuits2nd 71 Combinational Circuits Charge Sharing Example Clk A A B B B Cc=15fF C C Ca=15fF Out CL=50fF !B Cb=15fF Cd=10fF Clk EE141 Integrated © Digital Circuits2nd 72 Combinational Circuits Charge Sharing VDD case 1) if V out < VTn VDD Clk Mp Mp Out Out CL A A == BB 00 Clk CL Ma Ma M Mb b Mee M EE141 Integrated © Digital XX a CC a CC bb Circuits2nd C L VDD = C L Vout t + Ca VDD – V Tn V X or Ca V out = Vout t – V DD = – -------- V DD – V Tn V X CL case 2) if V out > VTn Ca --------------------- Vout = –V DD C + C a L 73 Combinational Circuits Solution to Charge Redistribution Clk Mp Mkp Clk Out A B Clk Me Precharge internal nodes using a clock-driven transistor (at the cost of increased area and power) EE141 Integrated © Digital Circuits2nd 74 Combinational Circuits Issues in Dynamic Design 3: Clk Mp A=0 Backgate Coupling Out1 =1 CL1 Out2 =0 CL2 In B=0 Clk Me Dynamic NAND EE141 Integrated © Digital Circuits2nd Static NAND 75 Combinational Circuits Backgate Coupling Effect 3 2 Out1 1 Clk 0 In Out2 2 Time, ns -1 0 EE141 Integrated © Digital Circuits2nd 4 6 76 Combinational Circuits Issues in Dynamic Design 4: Clk Mp A Out CL B Clk Me EE141 Integrated © Digital Circuits2nd Clock Feedthrough Coupling between Out and Clk input of the precharge device due to the gate to drain capacitance. So voltage of Out can rise above VDD. The fast rising (and falling edges) of the clock couple to Out. 77 Combinational Circuits Clock Feedthrough Clock feedthrough Clk Out 2.5 In1 1.5 In2 In3 In & Clk 0.5 In4 Out Clk -0.5 0 0.5 Time, ns 1 Clock feedthrough EE141 Integrated © Digital Circuits2nd 78 Combinational Circuits Other Effects Capacitive coupling Substrate coupling Minority charge injection Supply noise (ground bounce) EE141 Integrated © Digital Circuits2nd 79 Combinational Circuits Cascading Dynamic Gates V Clk Clk Mp Mp Out1 Clk Me Out2 In In Clk Clk Me Out1 VTn V Out2 t Only 0 1 transitions allowed at inputs! EE141 Integrated © Digital Circuits2nd 80 Combinational Circuits Domino Logic Clk In1 In2 In3 Clk EE141 Integrated © Digital Mp 11 10 PDN Me Circuits2nd Out1 Clk Mp Mkp Out2 00 01 In4 In5 Clk PDN Me 81 Combinational Circuits Why Domino? Clk Ini Inj Clk PDN Ini Inj PDN Ini Inj PDN Ini Inj PDN Like falling dominos! EE141 Integrated © Digital Circuits2nd 82 Combinational Circuits Properties of Domino Logic Only non-inverting logic can be implemented Very high speed static inverter can be skewed, only L-H transition Input capacitance reduced – smaller logical effort EE141 Integrated © Digital Circuits2nd 83 Combinational Circuits Designing with Domino Logic VDD VDD VDD Clk Mp Clk Mp Out1 Mr Out2 In1 In2 In3 PDN PDN In4 Can be eliminated! Clk Me Clk Me Inputs = 0 during precharge EE141 Integrated © Digital Circuits2nd 84 Combinational Circuits np-CMOS Clk In1 In2 In3 Mp 11 10 PDN Clk Me Out1 Clk Me In4 In5 PUN 00 01 Clk Mp Out2 (to PDN) Only 0 1 transitions allowed at inputs of PDN Only 1 0 transitions allowed at inputs of PUN EE141 Integrated © Digital Circuits2nd 85 Combinational Circuits