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Combinatorial Logic Circuits © Digital Integrated Circuits2nd EE141 1 Combinational Circuits Index Basic CMOS gates: Properties Ratioed Logic Pass transistor Logic Dynamic Logic Adapted from © Digital Integrated Circuits2nd EE141 2 Combinational vs. Sequential Logic In Combinational Logic Circuit In Out Combinational Logic Circuit Out State Combinational Sequential Output = f(In, Previous In) Output = f(In) Adapted from © Digital Integrated Circuits2nd EE141 3 Static CMOS Circuit At every point in time (except during the switching transients) each gate output is connected to either VDD or Vss via a low-resistive path. The outputs of the gates assume at all times the value of the Boolean function, implemented by the circuit (ignoring, once again, the transient effects during switching periods). This is in contrast to the dynamic circuit class, which relies on temporary storage of signal values on the capacitance of high impedance circuit nodes. Adapted from © Digital Integrated Circuits2nd EE141 4 Static Complementary CMOS VDD In1 In2 F(In1,In2,…InN)=1 produce F=Vdd PUN PMOS only InN In1 In2 InN F(In1,In2,…InN) PDN NMOS only F(In1,In2,…InN)=0 produce F=GND PUN and PDN are dual logic networks Adapted from © Digital Integrated Circuits2nd EE141 5 NMOS Transistors in Series/Parallel Connection Transistors can be thought as a switch controlled by its gate signal NMOS switch closes when switch control input is high A B X Y Y = X if A and B A X B Y Y = X if A OR B NMOS Transistors pass a “strong” 0 but a “weak” 1 Adapted from © Digital Integrated Circuits2nd EE141 6 PMOS Transistors in Series/Parallel Connection PMOS switch closes when switch control input is low A B X Y Y = X if A AND B = A + B A X B Y Y = X if A OR B = AB PMOS Transistors pass a “strong” 1 but a “weak” 0 Adapted from © Digital Integrated Circuits2nd EE141 7 Complementary CMOS Logic Style Adapted from © Digital Integrated Circuits2nd EE141 8 Example Gate: NAND Adapted from © Digital Integrated Circuits2nd EE141 9 Example Gate: NOR Adapted from © Digital Integrated Circuits2nd EE141 10 Complex CMOS Gate B A C D OUT = D + A • (B + C) A D B Adapted from © Digital Integrated Circuits2nd C EE141 11 Constructing a Complex Gate VDD VDD C F SN1 SN4 F A SN3 D B C B SN2 A D A B D C F (a) pull-down network (b) Deriving the pull-up network hierarchically by identifying sub-nets A D B C (c) complete gate Adapted from © Digital Integrated Circuits2nd EE141 12 Cell Design Standard Cells General purpose logic Can be synthesized Same height, varying width Datapath Cells For regular, structured designs (arithmetic) Includes some wiring in the cell Fixed height and width Adapted from © Digital Integrated Circuits2nd EE141 13 Standard Cell Layout Methodology – 1980s Routing channel VDD signals GND 2nd EE141 from © Digital Adapted Integrated © Digital Circuits Integrated Circuits2nd 14 Combinational Circuits Standard Cell Layout Methodology – 1990s Mirrored Cell No Routing channels VDD VDD M2 M3 GND Mirrored Cell 2nd EE141 from © Digital Adapted Integrated © Digital Circuits Integrated Circuits2nd GND 15 Combinational Circuits Standard Cells N Well VDD Cell height 12 metal tracks Metal track is approx. 3 + 3 Pitch = repetitive distance between objects Cell height is “12 pitch” 2 In Out GND Cell boundary 2nd EE141 from © Digital Adapted Integrated © Digital Circuits Integrated Circuits2nd Rails ~10 16 Combinational Circuits Standard Cells VDD A 2-input ??? gate B Out GND 2nd EE141 from © Digital Adapted Integrated © Digital Circuits Integrated Circuits2nd 17 Combinational Circuits Stick Diagrams Contains no dimensions Represents relative positions of transistors VDD VDD Inverter NAND2 Out Out In GND 2nd EE141 from © Digital Adapted Integrated © Digital Circuits Integrated GND Circuits2nd A B 18 Combinational Circuits Stick Diagrams Logic Graph A j X C C B A i X X = C • (A + B) C PUN i B VDD j B GND A B C Adapted from © Digital Integrated Circuits2nd EE141 A PDN 19 Two Versions of C • (A + B) A C B A B C VDD VDD X GND X GND Permutation of input signals that produce uninterrupted active strips is important ! 2nd EE141 from © Digital Adapted Integrated © Digital Circuits Integrated Circuits2nd 20 Combinational Circuits Euler Paths There is a systematic approach to uninterrupted strips of active. Two steps: Step 1: Construction of logic graph Step 2: Identification of Euler graphs Euler path is a path through all nodes such that every edge is visited once. Euler path is equivalent to an uninterrupted A-strip (succesive S and D connections) Consistency: Same ordering for PUN and PDN Adapted from © Digital Integrated Circuits2nd EE141 21 Euler Path Node X C i X B Edge = Transistor Adapted from © Digital Integrated Circuits2nd VDD j GND EE141 A A B C 22 OAI22 Logic Graph A C B D X D X = (A+B)•(C+D) C D A B C VDD X B A B C D Adapted from © Digital Integrated Circuits2nd A GND EE141 PUN PDN 23 Example: x = ab+cd x x c b VDD x a c b VD D x a d GND d GND (a) Logic graphs for (ab+cd) (b) Euler Paths {a b c d} VD D x GND a b c d (c) stick diagram for ordering {a b c d} Adapted from © Digital Integrated Circuits2nd EE141 24 CMOS Gates Static Properties of gates Delay characteristics Fan-in and Fan-out considerations Adapted from © Digital Integrated Circuits2nd EE141 25 Static Properties Depend on input pattern 3V a) A=B=0 → 1 Vout c) B=1, A=0 → 1 b) A=1, B=0 → 1 0V 0V 3V Vin a) Two pull-up transistors in parallel are more difficult to turn off than one b) One pull-up transistor, one pull-down. Dynamically, the internal node has to be discharged (slower) c) Vds1 produces bulk effect during discharge. More Vin is needed Adapted from © Digital Integrated Circuits2nd EE141 26 Switch Delay Model Req A A Rp A Rp Rp B Rn Rp Rp A CL A Cint A NAND2 Adapted from © Digital Integrated Circuits2nd Cint A Rn B Rn B INV EE141 CL Rn Rn A B CL NOR2 27 Input Pattern Effects on Delay Rp A Rp B Rn both inputs go low CL Cint A delay is 0.69 Rp CL when N transistor A goes off, internal node has to be charged High to low transition both inputs go high Adapted from © Digital Integrated Circuits2nd delay is 0.69 Rp/2 CL one input goes low B Rn Delay is dependent on the pattern of inputs Low to high transition EE141 delay is 0.69 2Rn CL 28 Delay Dependence on Input Patterns 3 Input Data Pattern Delay (psec) A=B=01 67 A=1, B=01 64 A= 01, B=1 61 0.5 A=B=10 45 0 A=1, B=10 80 A= 10, B=1 81 2.5 A=B=10 2 A=1 0, B=1 Voltage [V] 1.5 1 -0.5 A=1, B=10 0 100 200 300 time [ps] when N transistor A goes off, internal node has to be charged (slower) Adapted from © Digital Integrated Circuits2nd EE141 400 NMOS = 0.5m/0.25 m PMOS = 0.75m/0.25 m CL = 100 fF 29 Transistor Sizing Rp 2 A Rp B Rn 2 B 2 Rn Rp 4 B 2 CL Rp 4 Cint A Cint 1 A Rn Rn A B CL 1 NAND based implementations are preferred over NOR … Adapted from © Digital Integrated Circuits2nd EE141 30 Transistor Sizing a Complex CMOS Gate A B 8 6 C 8 6 4 3 D 4 6 OUT = D + A • (B + C) A D 2 1 B Adapted from © Digital Integrated Circuits2nd 2C EE141 2 31 Fan-In Considerations A B C D A Distributed RC model (Elmore delay) CL B C3 C C2 D C1 tpHL = 0.69 Re (C1+2C2+3C3+4CL) = Re C1+2 Re C2+3Re C3+4Re CL * Propagation delay deteriorates rapidly as a function of fan-in – quadratically in the worst case. (prop. to R×C) * Internal nodes important !! Adapted from © Digital Integrated Circuits2nd EE141 32 tp as a Function of Fan-In 1250 quadratic 1000 tp (psec) Intrinsec C increases linearly Series transistors cause a double slowdown 750 tpHL Parallel transistors increase C tp 500 tpLH 250 linear 0 2 4 6 8 fan-in 10 12 14 16 Gates with a fan-in greater than 4 should be avoided. Adapted from © Digital Integrated Circuits2nd EE141 33 tp as a Function of Fan-Out tpNOR2 tpNAND2 tpINV tp (psec) 2 All gates have the same drive current. Slope is a function of “driving strength” 4 6 8 10 12 14 16 eff. fan-out Adapted from © Digital Integrated Circuits2nd EE141 34 tp as a Function of Fan-In and Fan-Out Fan-in: quadratic due to increasing resistance and capacitance Fan-out: each additional fan-out gate adds two gate capacitances to CL tp = a1FI + a2FI2 + a3FO Adapted from © Digital Integrated Circuits2nd EE141 35 Fast Complex Gates: Design Technique 1 Transistor sizing as long as fan-out capacitance dominates Progressive sizing Distributed RC line InN MN In3 M3 C3 In2 M2 C2 In1 M1 C1 CL Adapted from © Digital Integrated Circuits2nd M1 > M2 > M3 > … > MN (the fet closest to the output is the smallest) Lower caps see smaller R Can reduce delay by more than 20%; decreasing gains as technology shrinks EE141 36 Fast Complex Gates: Design Technique 2 Transistor ordering Transistor with more activity or with latest changes on top critical path In3 1 M3 critical path 01 In1 M3 charged CL In2 1 M2 C2 charged In1 M1 01 C1 charged delay determined by time to discharge CL, C1 and C2 Adapted from © Digital Integrated Circuits2nd CLcharged In2 1 M2 C2 discharged In3 1 M1 C1 discharged delay determined by time to discharge CL EE141 37 Fast Complex Gates: Design Technique 3 Alternative logic structures F = ABCDEFGH There are techniques to minimize switching time: logical effort Adapted from © Digital Integrated Circuits2nd EE141 38 Fast Complex Gates: Design Technique 4 Isolating fan-in from fan-out using buffer insertion CL CL Adapted from © Digital Integrated Circuits2nd EE141 39 Fast Complex Gates: Design Technique 5 Reducing the voltage swing tpHL = 0.69 (3/4 (CL VDD)/ IDSATn ) = 0.69 (3/4 (CL Vswing)/ IDSATn ) linear reduction in delay (only when variation of Req is not substantial; after this, delay gets worse) also reduces power consumption But the following gate is much slower! Or requires use of “sense amplifiers” on the receiving end to restore the signal level (memory design) Adapted from © Digital Integrated Circuits2nd EE141 40 Stages with general logic What happens in the general case: no longer inverters Suppose we drive a load using a non-inverter stage increase the transistors by a factor g so that we have the same driving as the inverter (per input) The input capacitance is g times bigger We t p kReq Cint CL kReq Cint fCint t p kReq gCINV fgCINV t po p g f / there’s more than one input Adapted from © Digital Integrated Circuits2nd EE141 tpo is the intrinsic time of a min. size inv. 41 Logical Effort t p t p0 p g f / f – effective fanout p – intrinsic delay factor (multiple times of the inverter intrinsic delay) g – logical effort (ratio of its input capacitance to the inverter capacitance when sized to deliver the same current). Increases with gate complexity. Depends only on topology Adapted from © Digital Integrated Circuits2nd EE141 42 Logical Effort Logical effort quantifies how much less driving strength a gate has compared to an inveter VDD A VDD A 2 2 B 2 F F A A VDD B 4 A 4 2 F 1 A B Inverter g=1 1 B 1 2 2-input NAND g = 4/3 Adapted from © Digital Integrated Circuits2nd EE141 2-input NOR g = 5/3 43 Intrinsic delay factors Gate Type P Inverter 1 N-input NAND N N-input NOR N N-way mux 2N XOR, NXOR Adapted from © Digital Integrated Circuits2nd N 2^(N-1) EE141 44 Normalized delay (d) Logical Effort of Gates t pNAND g = 4/3 p=2 d = (4/3)h+2 t pINV g=1 p=1 d = h+1 F(Fan-in) 1 2 Adapted from © Digital Integrated Circuits2nd 3 4 5 Fan-out (h) EE141 6 7 45 Logical Effort of Gates 5 2-input NAND: p=2; g=4/3 Inverter: P=1; g=1 4 3 Effort Delay 2 Normalized Delay 1 Intrinsic Delay 1 2 Adapted from © Digital Integrated Circuits2nd 3 Fanout f EE141 4 5 46 Multistage Networks N Delay t p 0 pi g i f i i 1 Stage effort: hi = gifi Path electrical effort: F = Cout/Cin Path logical effort: G = g1g2…gN F fi / B Branching effort: B = b1b2…bN Path effort: H = GFB Path delay D t p 0 N p h i 1 Adapted from © Digital Integrated Circuits2nd i EE141 i 47 Add Branching Effort Branching effort: b Con path Coff path Adapted from © Digital Integrated Circuits2nd Con path EE141 48 Optimum Effort per Stage When each stage bears the same effort: hN H hN H Stage efforts: g1f1 = g2f2 = … = gNfN Effective fanout of each stage: f i h g i Adapted from © Digital Integrated Circuits2nd EE141 49 Sizing After the fi’s have been obtained, the sizing factors si’s are calculated starting from the first one: The others are obtained iteratively Reference: Sutherland, Sproull, Harris, “Logical Effort, MorganKaufmann 1999. Adapted from © Digital Integrated Circuits2nd EE141 50 Example: Optimize Path 1 g=1 f=a b a g = 5/3 f = b/a Adapted from © Digital Integrated Circuits2nd c 5 g = 5/3 f = c/b EE141 g=1 f = 5/c 51 Adapted from © Digital Integrated Circuits2nd EE141 52 Example – 8-input AND Adapted from © Digital Integrated Circuits2nd EE141 53 Summary Sutherland, Sproull Harris Adapted from © Digital Integrated Circuits2nd EE141 54 Ratioed Logic © Digital Integrated Circuits2nd EE141 55 Combinational Circuits Ratioed Logic VDD Resistive Load VDD Depletion Load RL PDN F In1 In2 In3 VSS (a) resistive load PMOS Load VSS VT < 0 F In1 In2 In3 VDD PDN VSS (b) depletion load NMOS F In1 In2 In3 PDN VSS (c) pseudo-NMOS Goal: to reduce the number of devices over complementary CMOS Adapted from © Digital Integrated Circuits2nd EE141 56 Ratioed Logic VDD • N transistors + Load Resistive Load • VOH = V DD RL • VOL = RPN + RL F In1 In2 In3 RPN • Assymetrical response PDN • Static power consumption • tpL= 0.69 RLCL VSS Adapted from © Digital Integrated Circuits2nd EE141 57 Active Loads VDD Depletion Load VDD PMOS Load VT < 0 VSS F In1 In2 In3 F In1 In2 In3 PDN VSS VSS depletion load NMOS Adapted from © Digital Integrated Circuits2nd PDN pseudo-NMOS EE141 58 Pseudo-NMOS VDD A B C D F CL VOH = VDD (similar to complementary CMOS) 2 V OL kp 2 k n VDD – V Tn V OL – ------------- = ------ V DD – VTp 2 2 V OL = VDD – V T 1 – kp 1 – ------ (assuming that V T = V Tn = VTp ) kn SMALLER AREA & LOAD BUT STATIC POWER DISSIPATION!!! Adapted from © Digital Integrated Circuits2nd EE141 59 Pseudo-NMOS VTC 3.0 The bigger P, the fastest the L to H transition, but more power and higher Vol 2.5 W/Lp = 4 Vout [V] 2.0 1.5 W/Lp = 2 i 1.0 0.5 W/Lp = 0.5 W/Lp = 1 W/Lp = 0.25 0.0 0.0 0.5 1.0 1.5 2.0 2.5 Vin [V] VOL Adapted from © Digital Integrated Circuits2nd EE141 V’OL v 60 Performance of a P-NMOS inverter Size Vol Static P Tplh 4 0.693 564W 14 ps 2 0.273 298 W 56 ps 1 0.133 160 W 123 ps ½ 0.064 80 W 268 ps 1/4 0.031 41 W 569 ps Adapted from © Digital Integrated Circuits2nd EE141 61 Improved Loads (2) VDD VDD M1 M2 Out A A B B Out PDN1 PDN2 VSS VSS Differential Cascode Voltage Switch Logic (DCVSL) Adapted from © Digital Integrated Circuits2nd EE141 62 DCVSL Transient Response Out AB B A B B A V olta ge [V] AB Out B 2.5 AB 1.5 0.5 -0.5 0 XOR-NXOR gate Adapted from © Digital Integrated Circuits2nd EE141 AB A,B 0.2 A,B 0.4 0.6 Time [ns] 0.8 1.0 63 Pass-Transistor Logic © Digital Integrated Circuits2nd EE141 64 Combinational Circuits Pass-Transistor Logic Inputs B Switch Out A Out Network B B • N transistors • No static consumption Adapted from © Digital Integrated Circuits2nd EE141 65 Example: AND Gate B Bottom ensures low impedance path B=1 and A=1 produces a weak 1 ouput A B Worsened by body effect Fewer gates Smaller capacitance F = AB 0 Adapted from © Digital Integrated Circuits2nd EE141 66 NMOS-Only Logic 3.0 In In VDD x 0.5m/0.25m Out 0.5m/0.25m Voltage [V] 1.5m/0.25m Out 2.0 x 1.0 0.0 0 0.5 1 1.5 2 Time [ns] Tail end of transient very slow due to the small current available Adapted from © Digital Integrated Circuits2nd EE141 67 Series cascade Adapted from © Digital Integrated Circuits2nd EE141 68 NMOS-only Switch C = 2.5V C = 2.5 V M2 A = 2.5 V A = 2.5 V B Mn B M1 CL Vb does not pull up to 2.5V, but to 2.5V - Vtn Threshold voltage loss causes static power consumption NMOS has higher threshold than PMOS (body effect) Adapted from © Digital Integrated Circuits2nd EE141 69 NMOS Only Logic: Level Restoring Transistor VDD VDD Level Restorer Mr B A Mn M2 X Out M1 • Advantage: Full Swing • Restorer adds capacitance, takes away pull down current at X • Ratio problem: Mn has to be able to pull down node X from Vdd to GND Adapted from © Digital Integrated Circuits2nd EE141 70 Restorer Sizing Voltage [V] 3.0 2.0 W/Lr =1.75/0.25 W/L r =1.50/0.25 1.0 W/Lr =1.0/0.25 0.0 0 100 200 W/L r =1.25/0.25 300 Time [ps] 400 • Upper limit on restorer size • Pass-transistor pull-down can have several transistors in stack • Fall time is accelerated, rise is slowed down 500 Transistor Mn is fixed and size of Feedback (Mr) is increased (Switching threshold of inverter is mid-rail). Adapted from © Digital Integrated Circuits2nd EE141 71 Complementary Pass Transistor Logic A A B B Pass-Transistor F Network (a) A A B B B Inverse Pass-Transistor Network B B A F B B A A B F=AB A B F=A+B F=AB AND/NAND A F=AÝ (b) A A B B F=A+B B OR/NOR Adapted from © Digital Integrated Circuits2nd EE141 A F=AÝ EXOR/NEXOR 73 Complementary Pass Transistor Logic Complementary data inputs and outputs are always available Output are always connected to low-impedance Design is very modular. The same topology is used. Permutation of inputs is used. Complementary signals have to be routed Restorer has to be used, otherwise static consumption Adapted from © Digital Integrated Circuits2nd EE141 74 Solution 3: Transmission Gate C A C A B B C C C = 2.5 V A = 2.5 V B CL C=0V Adapted from © Digital Integrated Circuits2nd EE141 75 Pass-Transistor Based Multiplexer S S S S VDD S A VDD M2 F S M1 B S GND In1 Adapted from © Digital Integrated Circuits2nd EE141 In2 76 Transmission Gate XOR B B M2 A A F M1 M3/M4 B B Adapted from © Digital Integrated Circuits2nd EE141 77 Resistance of Transmission Gate R [kΩ] 30 2. 5 V Resistance, ohms Rn 20 Rp 2.5 V Rn Vou t Rp 10 0 0.0 0V Rn || Rp 1.0 2.0 Vou t , V It has a series resistance that can be assumed constant, and equal to a couple of KΩ Adapted from © Digital Integrated Circuits2nd EE141 78 Delay in Transmission Gate Networks 2.5 2.5 V1 In 2.5 Vi Vi-1 C 0 2.5 C 0 Vn-1 Vi+1 C 0 Vn C C 0 (a) Req Req V1 In Req Vi C Vn-1 Vi+1 C C Req Vn C C (b) m Req Req Req Req Req Req In C CC C C CC C (c) Adapted from © Digital Integrated Circuits2nd EE141 79 Delay Optimization mopt is typically 3 or 4 .. Adapted from © Digital Integrated Circuits2nd EE141 80 Dynamic Logic © Digital Integrated Circuits2nd EE141 81 Combinational Circuits Dynamic CMOS In static circuits at every point in time (except when switching) the output is connected to either GND or VDD via a low resistance path. fan-in of n requires 2n (n N-type + n P-type) devices Dynamic circuits rely on the temporary storage of signal values on the capacitance of high impedance nodes. requires on n + 2 (n+1 N-type + 1 P-type) transistors Adapted from © Digital Integrated Circuits2nd EE141 82 Dynamic Gate Clk Clk Mp off Mp on Out In1 In2 In3 Clk CL 1 Out ((AB)+C) A PDN C B Me Clk off Me on Two phase operation Precharge (Clk = 0) Evaluate (Clk = 1) Adapted from © Digital Integrated Circuits2nd EE141 84 Conditions on Output Once the output of a dynamic gate is discharged, it cannot be charged again until the next precharge operation. Inputs to the gate can make at most one transition during evaluation. Output can be in the high impedance state during and after evaluation (PDN off), state is stored on CL Adapted from © Digital Integrated Circuits2nd EE141 85 Properties of Dynamic Gates Logic function is implemented by the PDN only number of transistors is N + 2 (versus 2N for static complementary CMOS) Full swing outputs (VOL = GND and VOH = VDD) Non-ratioed - sizing of the devices does not affect the logic levels Faster switching speeds reduced load capacitance due to lower input capacitance (Cin) reduced load capacitance due to smaller output loading (Cout) no Isc, so all the current provided by PDN goes into discharging CL Adapted from © Digital Integrated Circuits2nd EE141 86 Properties of Dynamic Gates Overall power dissipation usually higher than static CMOS no static current path ever exists between VDD and GND (including Psc) no glitching higher transition probabilities due to periodic charge and discharge extra load on Clk PDN starts to work as soon as the input signals exceed VTn, so VM, VIH and VIL equal to VTn low noise margin (NML) Needs a precharge/evaluate clock Adapted from © Digital Integrated Circuits2nd EE141 87 Issues in Dynamic Design: Charge Leakage CLK Clk Mp Out CL A Clk Me Evaluate VOut Precharge Leakage sources Dominant component is subthreshold current Adapted from © Digital Integrated Circuits2nd EE141 88 Solution to Charge Leakage Keeper Clk Mp A Mkp CL Out B Clk Me Same approach as level restorer for pass-transistor logic Adapted from © Digital Integrated Circuits2nd EE141 89 Issues in Dynamic Design: Charge Sharing Clk Mp Out A CL B=0 Clk Charge stored originally on CL is redistributed (shared) over CL and CA leading to reduced robustness CA Me CB Adapted from © Digital Integrated Circuits2nd EE141 90 Charge Sharing VDD case 1) if V out < VTn VDD Clk Mp Mp Out Out CL A A = BB 00 Clk CL Ma Ma M Mb b Mee M XX a CC a CC bb C L VDD = C L Vout t + Ca VDD – V Tn V X or Ca V out = Vout t – V DD = – -------- V DD – V Tn V X CL case 2) if V out > VTn Ca --------------------- Vout = –V DD C + C a L Adapted from © Digital Integrated Circuits2nd EE141 91 Solution to Charge Redistribution Clk Mp Mkp Clk Out A B Clk Me Precharge internal nodes using a clock-driven transistor (at the cost of increased area and power) Adapted from © Digital Integrated Circuits2nd EE141 92 Issues in Dynamic Design: Backgate Coupling Clk Mp A=0 Out1 =1 CL1 Out2 =0 CL2 In B=0 Clk Me Dynamic NAND Adapted from © Digital Integrated Circuits2nd Static NAND EE141 93 Backgate Coupling Effect 3 2 Out1 1 Clk 0 In Out2 2 Time, ns -1 0 Adapted from © Digital Integrated Circuits2nd EE141 4 6 94 Issues in Dynamic Design 4: Clock Feedthrough Clk Mp A Out CL B Clk Me Coupling between Out and Clk input of the precharge device due to the gate to drain capacitance. So voltage of Out can rise above VDD. The fast rising (and falling edges) of the clock couple to Out. Signal levels above VDD may cause the normally reverse-biased junction diodes become forward-biased causing electrons to be injected into the substrate: a) possible latch-up, b) other nodes disturbed Adapted from © Digital Integrated Circuits2nd EE141 95 Clock Feedthrough Clock feedthrough Clk Out 2.5 In1 In2 1.5 In3 In & Clk 0.5 In4 Clk Out -0.5 0 0.5 Time, ns 1 Clock feedthrough Adapted from © Digital Integrated Circuits2nd EE141 96 Other Effects Capacitive coupling Substrate coupling Minority charge injection Supply noise (ground bounce) Adapted from © Digital Integrated Circuits2nd EE141 97 Cascading Dynamic Gates V Clk Mp Clk Mp Out1 Clk Out2 In In Clk Me Clk Me Out1 VTn V Out2 t Due to finite discharge time of first stage, the second stage output drops when it shouldn’t Adapted from © Digital Integrated Circuits2nd EE141 98 Domino Logic Clk In1 In2 In3 Clk Mp 11 10 Out1 PDN Me Clk Mp Mkp Out2 00 01 In4 In5 Clk PDN Me Output transition always starts at 0, and only 0 →1 transitions occur Adapted from © Digital Integrated Circuits2nd EE141 99 Why Domino? Clk Ini Inj Clk PDN Ini Inj PDN Ini Inj PDN Ini Inj PDN Like falling dominos! Adapted from © Digital Integrated Circuits2nd EE141 100 Properties of Domino Logic Only non-inverting logic can be implemented Very high speed static inverter can be skewed, only L-H transition Input capacitance reduced – smaller logical effort Adapted from © Digital Integrated Circuits2nd EE141 101 Summary Static CMOS: Performance is a strong function of fanin. Speed is a linear function of fan-in Ratioed logic: reduction of complexity at the expense of static consumption and asymmetrical response Pass-transistor logic: simple for some functions. Long switch networks have quadratic delay. NMOS only networks are even simpler, but suffer from power consumption and reduced margins Dynamic logic: Trades off noise margins for performance. Sensitive to leakage, coupling and charge sharing. Cascading can cause problems Adapted from © Digital Integrated Circuits2nd EE141 102 Appendix I Elmore Delay © Digital Integrated Circuits2nd EE141 103 Combinational Circuits Y. Ismail, Equivalent Elmore Delays for RLC Trees, DAC 1999 EE141 Adapted from © Digital Integrated Circuits2nd Proc. 104