Download Chapter 6

Digital Integrated
Circuits
A Design Perspective
Jan M. Rabaey
Anantha Chandrakasan
Borivoje Nikolić
Designing Combinational
Logic Circuits
EE141 Integrated
© Digital
Circuits2nd
1
Combinational Circuits
Combinational vs. Sequential Logic
Combinational
Logic
Circuit
In
In
Out
Out
Combinational
Logic
Circuit
State
Combinational
Output = f(In)
EE141 Integrated
© Digital
Circuits2nd
Sequential
Output = f(In, Previous In)
2
Combinational Circuits
Static CMOS Circuit
 At every point in time (except during the switching
transients) each gate output is connected to either
VDD or Vss via a low-resistive path.
 The outputs of the gates assume at all times the value
of the Boolean function, implemented by the circuit
(ignoring, once again, the transient effects during
switching periods).
 This is in contrast to the dynamic circuit class, which
relies on temporary storage of signal values on the
capacitance of high impedance circuit nodes.
EE141 Integrated
© Digital
Circuits2nd
3
Combinational Circuits
Static Complementary MOS
VDD
In1
In2
PUN
InN
In1
In2
PMOS only (make a connection from
Vdd to F when F(In1,…InN)=1
F(In1,In2,…InN)
PDN
NMOS only (make a connection from
Gnd to F when F(In1,…InN)=0
InN
The PUN and PDN are structured in a mutually exclusive fashion
such that only one of the them is conducting in steady-state
EE141 Integrated
© Digital
Circuits2nd
4
Combinational Circuits
Static Complementary CMOS
 Functionally, a transistor can be thought of as a switch. PDN is
on when input signal is high and off when low. PUN is on when
signal is low and off when high.
 PDN network is constructed using NMOS while PUN using
PMOS. The primary reason for this is that NMOS produce “strong
zeros” while PMOS generates “strong ones”, why?
EE141 Integrated
© Digital
Circuits2nd
5
Combinational Circuits
Threshold Drops
VDD
PUN
VDD
S
D
VDD
D
0  VDD
VGS
S
CL
VDD  0
PDN
D
VDD
S
CL
CL
VGS
VDD  |VTp|
S
EE141 Integrated
© Digital
CL
D
That is why PMOS is used in PUN, and NMOS in PDN
Circuits2nd
0  VDD - VTn
6
Combinational Circuits
NMOS Transistors
in Series/Parallel Connection
Transistors can be thought of as a switch controlled by its gate signal
NMOS switch closes when switch control input is high
A
B
X
X: GND
Y
Y = X if A and B
NAND
Y = X if A OR B
NOR
A
Y: output
X
B
Y
NMOS Transistors pass a “strong” 0 but a “weak” 1
EE141 Integrated
© Digital
Circuits2nd
7
Combinational Circuits
PMOS Transistors
in Series/Parallel Connection
PMOS switch closes when switch control input is low
A
B
X
X: VDD
Y
Y = X if A AND B = A + B
NOR
A
Y: output
X
B
Y
Y = X if A OR B = AB
NAND
PMOS Transistors pass a “strong” 1 but a “weak” 0
EE141 Integrated
© Digital
Circuits2nd
8
Combinational Circuits
Complementary CMOS Logic Style
• Number of transistors required to implement an Ninput logic gate is 2N
EE141 Integrated
© Digital
Circuits2nd
9
Combinational Circuits
Example Gate: NAND
EE141 Integrated
© Digital
Circuits2nd
10
Combinational Circuits
Example Gate: NOR
EE141 Integrated
© Digital
Circuits2nd
11
Combinational Circuits
Complex CMOS Gate
B
A
C
D
OUT = D + A • (B + C)
A
D
B
EE141 Integrated
© Digital
Circuits2nd
C
12
Combinational Circuits
Constructing a Complex Gate
VDD
VDD
C
F
SN4
F
SN1
A
SN3
D
B
C
B
SN2
A
D
A
B
D
C
F
(a) pull-down network
(b) Deriving the pull-up network
hierarchically by identifying
sub-nets
A
D
B
C
(c) complete gate
EE141 Integrated
© Digital
Circuits2nd
13
Combinational Circuits
OAI22 Logic Graph
A
C
B
D
XOR, XNOR ?
X = (A+B)•(C+D)
C
D
A
B
EE141 Integrated
© Digital
Circuits2nd
A
B
C
D
14
Combinational Circuits
Properties of Complementary CMOS Gates
Snapshot
• High noise margins
:
VOH and VOL are at VDD and GND, respectively.
• No static power consumption
:
There never exists a direct path between VDD and
VSS (GND) in steady-state mode.
• Comparable rise and fall times:
(under appropriate sizing conditions)
EE141 Integrated
© Digital
Circuits2nd
15
Combinational Circuits
Complementary MOS Properties
Full rail-to-rail swing; high noise margins
 Logic levels not dependent upon the relative
device sizes; ratioless
 Always a path to Vdd or Gnd in steady state;
low output impedance
 Extremely high input resistance; nearly zero
steady-state input current
 No direct path steady state between power
and ground; no static power dissipation
 Propagation delay as function of load
capacitance and resistance of transistors

EE141 Integrated
© Digital
Circuits2nd
16
Combinational Circuits
Voltage Transfer Characteristics
 Multi-dimensional
plot (can be obtained
using DC sweep analysis)
EE141 Integrated
© Digital
Circuits2nd
17
Combinational Circuits
Delay: Switch Delay Model
Req
A
A
Rp
A
Rp
Rp
B
Rn
Rp
CL
Rn
A
Cint
INV
NAND2
Circuits2nd
Cint
A
A
EE141 Integrated
© Digital
Rp
A
B
Rn
B
CL
Rn
Rn
A
B
CL
NOR2
18
Combinational Circuits
Input Pattern Effects on Delay
Delay is dependent on
the pattern of inputs
 Low to high transition

Rp
A
Rp
B
Rn
 both inputs go low
– delay is 0.69 Rp/2 CL
CL
 one input goes low
B
Rn
– delay is 0.69 Rp CL
Cint
A

High to low transition
 both inputs go high
– delay is 0.69 2Rn CL
EE141 Integrated
© Digital
Circuits2nd
19
Combinational Circuits
Delay Dependence on Input Patterns
3
Input Data
Pattern
Delay
(psec)
A=B=01
67
A=1, B=01
60
A= 01, B=1
64
0.5
A=B=10
45
0
A=1, B=10
80
A= 10, B=1
81
A=B=10
2.5
Voltage [V]
2
A=1 0, B=1
1.5
A=1, B=10
1
-0.5
0
100
200
time [ps]
300
400
NMOS = 0.5m/0.25 m
PMOS = 0.75m/0.25 m
CL = 100 fF
The difference between the later two cases of H-L has to
do with the internal node capacitance charging
20
EE141 Integrated Circuits2nd
© Digital
Combinational Circuits
Transistor Sizing
The goal is to size the gate so that it has approximately
the same delay (mostly worst-case delay) as an minimumsize inverter (9λ/2λ,3λ/2λ) Assumes Rp = Rn
Rp
1
A
2
Rp
1
B
B
Rn
2
CL
A
Cint
Rp
Cint
A
B
2 R
n
Rp
2
1 Rn
Rn
A
B
1
First-order estimate neglecting velocity saturation effects
(smaller for stacked transistor) and self-loading
EE141 Integrated
© Digital
Circuits2nd
CL
21
Combinational Circuits
EE141 Integrated
© Digital
Circuits2nd
22
Combinational Circuits
Transistor Sizing a Complex
CMOS Gate
Note: the number for
PMOS is with respect
to PMOS counterpart
3
(27λ/2λ) in minimum size
inverter, and NMOS to
3
NMOS counterpart
B
A
3
C
D
3
OUT = D + A • (B + C)
A
D
EE141 Integrated
© Digital
(6λ/2λ)
1
B
Circuits2nd
2
2C
2
23
Combinational Circuits
Fan-In Considerations
A
B
C
D
A
CL
B
C3
C
C2
D
C1
C1? C2? C3? CL?
C1: CdbD, CsbC, 2CgdD, 2CgsC
EE141 Integrated
© Digital
Circuits2nd
Distributed RC model
(Elmore delay)
tpHL = 0.69 Reqn(C1+2C2+3C3+4CL)
Propagation delay deteriorates
rapidly as a function of fan-in –
quadratically in the worst case.
24
Combinational Circuits
The Elmore Delay
RC Chain
EE141 Integrated
© Digital
Circuits2nd
25
Combinational Circuits
tp as a Function of Fan-In for NAND
1250
quadratic
1000
tp (psec)
750
tpHL
500
Assumes fixed
fan-out
tp
250
tpLH linear
0
2
4
6
8
fan-in
10
12
14
16
Gates with a fan-in greater than 4 should be avoided.
EE141 Integrated
© Digital
Circuits2nd
26
Combinational Circuits
tp as a Function of Fan-Out
tpNAND2
tp (psec)
tpNOR2
2
All gates are
scaled using the
switched delay
model. (why
delay of NOR2
and NAND2 still
lager?)
Intrinsic cap.
tpINV
4
6
8
10
12
14
16
eff. fan-out
EE141 Integrated
© Digital
Circuits2nd
27
Combinational Circuits
tp as a Function of Fan-In and Fan-Out
 Fan-in:
quadratic due to increasing
resistance and capacitance
 Fan-out:
each additional fan-out gate
adds two gate capacitances to CL
tp = a1FI + a2FI2 + a3FO
EE141 Integrated
© Digital
Circuits2nd
28
Combinational Circuits
Fast Complex Gates:
Design Technique 1
 Transistor
sizing
 as long as fan-out capacitance dominates
 Progressive
InN
sizing (non-uniform sizing)
CL
MN
In3
M3
C3
In2
M2
C2
In1
M1
C1
EE141 Integrated
© Digital
Circuits2nd
Distributed RC line
M1 > M2 > M3 > … > MN
(the transistor closest to the
output is the smallest)
Can reduce delay by more than
20%; decreasing gains as
technology shrinks (due to layout)
29
Combinational Circuits
Fast Complex Gates:
Design Technique 2
 An
input signal is called critical if it is
the last signal of all inputs to assume a
stable value
 The path through the logic which
determines the ultimate speed of the
structure is called the critical path
 Putting the critical path transistors
closer to the output of the gate can
result in a speed up
EE141 Integrated
© Digital
Circuits2nd
30
Combinational Circuits
Fast Complex Gates:
Design Technique 2
 Transistor
ordering
critical path
In3
1
In2
1
charged
CL
M3
M2
In1
M1
01
C2 charged
C1 charged
delay determined by time to
discharge CL, C1 and C2
EE141 Integrated
© Digital
Circuits2nd
critical path
01
In1
M3
CL
In2 1 M2
C2 discharged
In3 1 M1
C1 discharged
charged
delay determined by time to
discharge CL
31
Combinational Circuits
Fast Complex Gates:
Design Technique 3
 Alternative
logic structures
F = ABCDEFGH
EE141 Integrated
© Digital
Circuits2nd
32
Combinational Circuits
Fast Complex Gates:
Design Technique 4
 Isolating
fan-in from fan-out using buffer
insertion (inverter chains)
CL
EE141 Integrated
© Digital
Circuits2nd
CL
33
Combinational Circuits
Sizing Logic Paths for Speed

Frequently, input capacitance of a logic path is constrained

Logic also has to drive some capacitance

Example: ALU load in an Intel’s microprocessor is 0.5pF

How do we size the ALU datapath to achieve maximum
speed?

We have already solved this for the inverter chain – can we
generalize it for any type of logic?
EE141 Integrated
© Digital
Circuits2nd
34
Combinational Circuits
EE141 Integrated
© Digital
Circuits2nd
35
Combinational Circuits
Buffer Example
In
Out
1
2
N
CL
For given N: Ci+1/Ci = Ci /Ci-1
To find N: Ci+1/Ci ~ 4
How to generalize this to any logic path?
EE141 Integrated
© Digital
Circuits2nd
36
Combinational Circuits
Apply to Inverter Chain
In
Out
1
2
N
CL
tp = tp1 + tp2 + …+ tpN
 C gin, j 1 
 t pj ~ RunitC unit 1  f i 
t pj ~ RunitCunit 1 
 C

gin
,
j


N
N 
C gin, j 1 
, C gin, N 1  C L
t p   t p , j  t p 0  1 
 C

j 1
i 1 
gin, j 
EE141 Integrated
© Digital
Circuits2nd
37
Combinational Circuits
Optimal Tapering for Given N
Delay equation has N - 1 unknowns, Cgin,2 – Cgin,N
Minimize the delay, find N - 1 partial derivatives
Result: Cgin,j+1/Cgin,j = Cgin,j /Cgin,j-1
Size of each stage is the geometric mean of two neighbors
C gin, j  C gin, j 1C gin, j 1
- each stage has the same effective fanout (Cout/Cin)
- each stage has the same delay
EE141 Integrated
© Digital
Circuits2nd
38
Combinational Circuits
Optimum Delay and Number of
Stages
When each stage is sized by f and has same eff. fanout f:
f N  F  CL / Cgin,1
Effective fanout of each stage:
f NF
Minimum path delay

t p  Nt p 0 1  N F / 
EE141 Integrated
© Digital
Circuits2nd

39
Combinational Circuits
Generalized logic path
1
a
b
c
5
How to size this generalized logic path?
EE141 Integrated
© Digital
Circuits2nd
40
Combinational Circuits
Logical Effort
Logical effort is the ratio of input capacitance of a gate to the input
capacitance of an minimum-size inverter gate with the same
output current (considering worst case)
VDD
A
VDD
A
2
2
B
F
2
F
A
A
VDD
B
4
A
4
2
F
1
A
B
Inverter
g=1
EE141 Integrated
© Digital
Circuits2nd
1
B
1
2
2-input NAND
g = 4/3
2-input NOR
g = 5/3
41
Combinational Circuits
Normalizing the delay to inverter
Now, consider to normalize everything to an minimum-size inverter
(Assume  = 1). Then, (1) What is the load capacitance in each case for
an effective fan-out of 2 (with respect to one input) for example? (2) What
is the intrinsic delay in each case? (3) what is the external delay?
VDD
A
VDD
A
2
2
B
2
F
6
A
VDD
F
A
2
B
4
A
4
8
F
1
A
B
Inverter
B
1
10
2
2-input NAND
t p , INV  k  RunitCunit 1  2 t p , NAND
EE141 Integrated Circuits2nd
© Digital
1
8 

 k  RunitCunit  2  2 
6 

2-input NOR
 10 
t p , NOR  k  RunitCunit  2  2 
 42 6 
Combinational Circuits
Delay in a logic gate with minimum size
• So, if we normalize everything to an minimum-size inverter
with ginv =1, pinv = 1 (everything is measured in unit delays tinv
• And assume  = 1
• Then we can introduce

CL 
  t  p  g  f 
Delay  k  RunitCunit 1 
 Cin 
p – intrinsic delay factor
g – logical effort
f – effective fanout
EE141 Integrated
© Digital
Circuits2nd
43
Combinational Circuits
Logical effort
Gate delay:
d=h+p
effort delay
intrinsic delay
Effort delay:
h=gf
logical
effort
effective fanout (of
each stage) = Cout/Cin
Effective fanout (electrical effort) is a function of load/gate size
EE141 Integrated
© Digital
Circuits2nd
44
Combinational Circuits
Logical Effort

Inverter has the smallest logical effort and intrinsic delay of all
static CMOS gates

Logical effort represents the fact that for a given load, complex
gate has to work harder (in terms of transistor sizes) than an
inverter to get a similar delay).

In another way, complex gives more loading capacitance to the
previous gate when made comparable to inverter after sizing

How much harder? How to measure it?

Logical effort for a complex gate can be computed from the
ratio of its input capacitance to the inverter capacitance when
sized to deliver the same current (Logical effort is a function
of topology, independent of sizing)

Logical effort increases with the gate complexity
EE141 Integrated
© Digital
Circuits2nd
45
Combinational Circuits
Logical Effort
Reference: Sutherland, Sproull, Harris, “Logical Effort, Morgan-Kaufmann, 1999.
EE141 Integrated
© Digital
Circuits2nd
46
Combinational Circuits
Normalized delay (d)
Logical Effort of Gates
t pNAND
g=
p=
d=
t pINV
g=
p=
d=
F(Fan-in)
1
EE141 Integrated
© Digital
Circuits2nd
2
3
4
5
Fan-out (h)
6
7
47
Combinational Circuits
Normalized delay (d)
Logical Effort of Gates
t pNAND
g = 4/3
p=2
d = (4/3)f+2
t pINV
g=1
p=1
d = f+1
F(Fan-in)
1
2
3
4
5
Fan-out (h)
6
7
Intrinsic delay is increased by twice since the intrinsic
capacitance gets two times larger
EE141 Integrated
© Digital
Circuits2nd
48
Combinational Circuits
4/
3;
p
=
2
Logical Effort of Gates
=
D:
g
tN
AN
=
g
r:
e
t
er
1;
p=
1
v
in
3
pu
4
In
2-
Normalized Delay
5
Effort
Delay
2
1
Intrinsic
Delay
1
EE141 Integrated
© Digital
Circuits2nd
2
3
Fanout f
4
5
49
Combinational Circuits