Download Interconnect Layout Optimization Under Higher

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Transcript
R0 is far away from a Constant!
effective-resistance R0 for unit-width n-transistor
size = 400x
size = 100x
cl \ tt
0.225pf
0.425pf
0.825pf

0.10ns
12270
9719
8665
0.20ns
19180
12500
10250
cl \ tt
0.501pf
0.901pf
1.701pf
0.05ns
12200
11560
8463
0.10ns
15550
13360
9688
0.20ns
19150
17440
12470
R0 depends on size, input slope tt and output load cl


0.05ns
12200
8135
8124
May differ by a factor of 2
Using more accurate model like the table-based device
model has the potential of further delay reduction.

But easy to be trapped at local optimum, and tends to be even
worse than using simple model [Fishburn-Dunlop, ICCAD’85]